CN110556149B - Anti-interference programming method, device, equipment and storage medium - Google Patents
Anti-interference programming method, device, equipment and storage medium Download PDFInfo
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- CN110556149B CN110556149B CN201810547404.0A CN201810547404A CN110556149B CN 110556149 B CN110556149 B CN 110556149B CN 201810547404 A CN201810547404 A CN 201810547404A CN 110556149 B CN110556149 B CN 110556149B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3422—Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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Abstract
The embodiment of the invention discloses an anti-interference programming method, an anti-interference programming device, anti-interference equipment and a storage medium, wherein the method comprises the following steps: when detecting that the current pulse number on the target word line reaches a preset pulse number, acquiring the bit number to be programmed; and if the bit number to be programmed is less than or equal to a preset bit number, increasing the voltage on the adjacent word line of the target word line to a preset voltage. According to the technical scheme of the embodiment of the invention, the voltage of the adjacent word line of the target word line is dynamically adjusted, so that the error coding rate of the target word line and the adjacent word line transistor, the interference of the voltage of the adjacent word line on the array and the damage of the device are reduced, and the technical effect of prolonging the service life of the device is also improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to an anti-interference programming method, device, equipment and storage medium.
Background
The memory cell of flash memory is a three-terminal device and has the same name as a field effect transistor: a source, a drain and a gate. The flash memory is different from the field effect transistor in that the flash memory also comprises a floating grid which is arranged between the control grid and the substrate; a silicon dioxide insulating layer is arranged between the control gate and the silicon substrate and is used for protecting charges in the floating gate from leaking. Due to the structural characteristics of the flash memory, the storage unit of the flash memory has certain charge retention capability. The flash memory is also a voltage control type device, and the flash memory frequently used at present is a NAND type flash memory; the erasing and writing of the NAND flash memory are based on tunneling effect, and current passes through an insulating layer between a floating gate and a silicon substrate to charge (program data) or discharge (erase data) the floating gate.
When programming a NAND flash memory, a high voltage needs to be applied to a word line to be programmed, in order to distinguish each word line, the word line to be programmed is marked as WLn, that is, a high voltage Vpgm is applied to a control gate of WLn, the potential of a transistor substrate to be programmed is pulled to 0V, and due to a large voltage difference between the control gate and the substrate, electrons can pass through an insulating layer by the voltage difference to charge a floating gate (program and write data); the transistor which is not to be programmed needs to ensure that the voltage between the control gate and the substrate is less, and the voltage of the substrate needs to be raised to a certain potential because the voltage of the control gate on the WLn is certain, so that the voltage difference between the control gate and the substrate is less, and electrons cannot pass through the insulating layer to charge the floating gate. The voltage of the substrate can be determined by the voltage of the control gate on the word line adjacent to the word line.
It should be noted that, in the process of programming the transistors on the WLn word line, the rest word lines will also apply a certain voltage, and the voltage applied to the WLn +1 or WLn-1 control gate is denoted as Vpass1 or Vpass2, and Vpass < Vpgm, as shown in fig. 1. The higher the adjacent sub-line Vpass voltage, the higher the substrate potential of the transistor on the WLn word line which is not to be programmed is raised, thereby preventing the cell which is not to be programmed from being programmed. However, the high and low control gate voltages Vpass of WLn +1 or WLn 1 in practical applications may cause the transistors on the word line (WLn +1 or WLn 1) that are not desired to be programmed due to the large voltage difference, and the continuous application of higher voltages to the adjacent word lines may aggravate the damage and reduce the lifetime of the device.
Disclosure of Invention
The invention provides an anti-interference programming method, an anti-interference programming device, anti-interference equipment and an anti-interference storage medium, so that the error coding rate of a target word line and adjacent word line transistors, the interference of the voltage of the adjacent word lines on an array and the damage of a device are reduced, and the technical effect of prolonging the service life of the device is also improved.
In a first aspect, an embodiment of the present invention provides an anti-interference programming method, where the method includes:
when detecting that the current pulse number on the target word line reaches a preset pulse number, acquiring the bit number to be programmed;
and if the bit number to be programmed is less than or equal to a preset bit number, increasing the voltage on the adjacent word line of the target word line to a preset voltage.
Further, the method further comprises: if the bit number to be programmed is larger than the preset bit number, when the next pulse programming of the current pulse is finished, taking the next pulse as the current pulse, and repeatedly executing to obtain the bit number to be programmed; until the number of bits to be programmed at present is less than or equal to the preset number of bits.
Further, the currently programmed pulse voltage of the target word line is at least 5v higher than the adjacent word line voltage of the target word line.
Further, the bit number programmed on the word line reaches the programmed target bit number as one-time programming, and the pulse voltage programmed currently on the target word line is smaller than the pulse voltage programmed previously.
In a second aspect, an embodiment of the present invention provides a tamper-resistant programming apparatus, including:
the detection module is used for acquiring the bit number to be programmed when the current pulse number on the target word line reaches the preset pulse number;
and the execution module is used for increasing the voltage of the adjacent word line of the target word line to a preset voltage if the bit number to be programmed is less than or equal to a preset bit number.
Further, the apparatus further comprises: the loop module is used for taking the next pulse as the current pulse when the next pulse programming of the current pulse is finished and repeatedly executing to obtain the bit number to be programmed if the bit number to be programmed is larger than the preset bit number; until the number of bits to be programmed at present is less than or equal to the preset number of bits.
Further, the currently programmed pulse voltage of the target word line is at least 5v higher than the adjacent word line voltage of the target word line.
Further, the bit number programmed on the word line reaches the programmed target bit number as one-time programming, and the pulse voltage programmed currently on the target word line is smaller than the pulse voltage programmed previously.
In a third aspect, an embodiment of the present invention further provides an apparatus, where the apparatus includes:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement a tamper resistant programming method in accordance with any of the embodiments of the invention.
In a fourth aspect, embodiments of the present invention further provide a storage medium containing computer-executable instructions for performing the tamper-resistant programming method according to any one of the embodiments of the present invention when executed by a computer processor.
The technical scheme of the embodiment of the invention obtains the bit number to be programmed by detecting that the current pulse number on the target word line reaches the preset pulse number, increases the voltage on the adjacent word line of the target word line to the preset voltage if the bit number to be programmed is less than or equal to the preset bit number, namely dynamically adjusts the voltage of the adjacent word line according to the number of the flash memory programming pulses, solves the technical problems that although the transistor on the target word line is prevented from being wrongly programmed by continuously applying higher voltage on the adjacent word line of the target word line in the prior art, the continuously applied high voltage not only causes interference on the transistors on other word lines, but also aggravates the damage of the device and reduces the service life of the device, realizes that the voltage of the adjacent word line of the target word line is dynamically adjusted, not only reduces the wrong programming rate of the transistor of the target word line and the adjacent word line, the interference of the voltage of the adjacent word, and the technical effect of prolonging the service life of the device is also improved.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
FIG. 1 is a diagram illustrating different voltages applied to different word lines in the prior art;
fig. 2 is a schematic flowchart of an anti-interference programming method according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a variation of a pulse voltage according to cyclic writing and erasing of a target word line in an anti-interference programming method according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a voltage variation of a word line adjacent to a target word line according to cyclic writing and erasing of the target word line in an anti-interference programming method according to an embodiment of the present invention;
fig. 5 is another schematic diagram illustrating voltage changes of word lines adjacent to a target word line according to cyclic writing and erasing of the target word line in an anti-interference programming method according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating an anti-interference programming method according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram of an anti-interference programming apparatus according to a third embodiment of the present invention;
fig. 8 is a schematic structural diagram of an apparatus according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 2 is a schematic flowchart of an anti-interference programming method according to an embodiment of the present invention, where the method is applicable to dynamically adjusting voltages of adjacent word lines when a target word line is programmed, and the method can be executed by an anti-interference programming apparatus, and the apparatus can be implemented in a form of software and/or hardware.
As shown in fig. 2, the method of this embodiment includes:
s210, when the current pulse number on the target word line reaches the preset pulse number, the bit number to be programmed is detected.
It should be noted that, the erasing and writing of the NAND flash memory are based on the tunneling effect, and due to the large voltage difference between the control gate and the substrate, electrons can pass through the insulating layer between the floating gate and the silicon substrate to charge (program data) or discharge (erase data) the floating gate. When a voltage is applied to a word line to program a transistor, one transistor may be used as one bit number, for example, there are 100 transistors to be programmed on a target word line, and there are 50 transistors to be programmed, which may be referred to as 100 bit numbers on the target word line, and there are 50 bits to be programmed.
The target word line is a word line to which a high voltage is applied to the control gate when programming a memory cell of the NAND flash memory, and may be a word line to which the highest voltage is applied to the control gate in the memory cell, that is, the target word line. It should be noted that during the process of programming the transistors on the target word line, a lower voltage is also applied to the remaining word lines. The current programming voltage of the target word line is at least 5v higher than the voltage of the adjacent word line of the target word line, optionally, the voltage applied to the control gate of the target word line is 15v, so that the transistor is in a conducting state, and the voltages applied to the rest word lines are respectively 10v, 8v, 6v and the like, so that the transistor is in a floating state, namely, an off state.
In the process of programming the transistor on the target word line, at least one programming pulse may be applied to the target word line, wherein each programming pulse voltage is gradually increased, optionally, the number of programming pulses applied may be 5 programming pulses, 6 programming pulses, and the like, and the pulse voltage sequentially increases, and optionally, as the number of programming pulses increases, the pulse voltage may sequentially be 10v, 12v, and the like. It should be noted that the number of different program pulses and the program pulse voltage applied to the target word line are determined by the wear of the device itself and the number of bits to be programmed. Exemplarily, the transistors on the same word line are programmed for the first time and the second time respectively, wherein when the bit number of the target word line programming reaches the target bit number, the transistors are programmed for one time, the devices may have different degrees of loss, if the bit number to be programmed is 1000, when the transistor is programmed for the first time, the performance of the devices may be better, during the programming and writing process, the insulating layer of the transistor has better performance and larger resistance to be overcome, therefore, the number of pulses which may be needed is larger, the programming pulse voltage is larger, that is, the transistor needs to be written for multiple times, optionally, the number of required pulses is 8, and the pulse voltage is 16v, 17v, 18v, 19v, 20v, 21v, 22v, and 23 v; when the transistor on the word line is programmed for the second time, due to multiple uses, the device has a certain loss, and it is possible that programming writing is relatively easy, so the number of pulses required is less than the number of pulses required for programming writing for the first time, the programming pulse voltage is less than the first programming pulse voltage, optionally, the number of pulses for programming is 6, the programming pulse voltages are 14v, 15v, 16v, 17v, 18v, 19v, and the like, as shown in fig. 3, and so on, it can be known that the required pulse voltage is gradually reduced with the increase of the number of uses.
In practical application, when the number of current pulses applied to the target word line is detected, the target programming bit number on the target word line is optionally 1000, the target number of programming pulses is optionally 6, and the required programming pulse voltage is 20 v. In the process of applying pulses to the target word line, whether the number of currently applied pulses exceeds a preset number of pulses is detected, optionally, the preset number of pulses is 3, and it should be noted that a user can set the preset number of pulses according to actual conditions.
For example, if the number of currently applied pulses is detected, optionally, the currently applied pulse is the first pulse to program the transistor on the target word line, and the number of programming pulses does not reach the preset 3 pulses, so that the pulse voltage continues to be applied to the target word line until the current number of pulses reaches the preset number of pulses, optionally, if the number of previously applied programming pulses is 3, and the preset number of pulses has been reached, the number of bits to be programmed is obtained, and optionally, the number of bits to be programmed is 400. The advantage of obtaining the bit number to be programmed is that it can be judged according to the bit number to be programmed that the voltages on the adjacent word lines of the target word line need to be increased, so as to prevent the transistor writing 1 on the target word line from being wrongly written as 0, which can be understood as preventing the transistor not to be programmed on the target word line from being programmed.
And S220, if the bit number to be programmed is less than or equal to a preset bit number, increasing the voltage on the adjacent word line of the target word line to a preset voltage.
Illustratively, the bit number to be programmed on the target word line is 1000, 6 programming pulses are required, the pulse voltage is 20v, the number of preset pulses is 3, the preset bit number is 500, optionally, the bit number to be programmed is obtained at the 3 rd programming pulse, the optional bit number to be programmed is 400, at this time, the bit number to be programmed is smaller than the preset bit number, that is, 400 is smaller than 500, and when the preset condition is met, the voltage of the adjacent bit line of the target word line is increased to be equal to the preset voltage.
The advantage of increasing the voltage on the adjacent bit line of the target word line to the preset voltage is that on one hand, the voltage on the adjacent word line can be always in a lower voltage state, and only when the preset condition is reached, the voltage of the adjacent word line is increased, so that the technical problems of interference with programming of other word lines and reduction of device loss are avoided; on the other hand, the voltage of the substrate of the transistor for writing 1 on the target word line can be increased by increasing the voltage of the adjacent word line, so that the voltage difference between the control grid and the substrate is reduced, electrons cannot be written into the floating grid in the transistor, and the technical effect that the transistor which is not wanted to be programmed is not programmed is realized.
Certainly, in the process of practical application, there may be a case where the number of bits to be programmed is greater than the preset number of bits, and when the programming of the next pulse of the current pulse is finished, the next pulse is taken as the current pulse, and the number of bits to be programmed is obtained by repeating the execution; until the number of bits to be programmed at present is less than or equal to the preset number of bits.
Specifically, after the 3 rd pulse is applied to the target word line, the number of bits to be programmed is, optionally, 400, and the preset number of bits is set to 300, where the number of bits to be programmed is greater than the preset number of bits, which indicates that the preset condition is not yet met. Continuously applying a 4 th pulse to the target word line, acquiring a bit number to be programmed after applying the 4 th pulse, and increasing the voltage of the adjacent word line of the target word line to a preset voltage if the bit number to be programmed is less than or equal to a preset bit number; if the bit number to be programmed is still greater than the preset bit number, the operation S210 is repeatedly performed until the bit number to be programmed is less than or equal to the preset bit number.
The number of pulses applied to the target word line for programming is used up, and the number of pulses programmed on the target word line reaches the target bit number to be used as one-time programming. When the target word line is programmed again, there may be a certain loss of the device, and therefore the required pulse voltage may be reduced, and if the number of bits programmed on the target word line is smaller than the preset number of bits, the preset voltage increased by the voltage on the adjacent bit line of the target word line is also lower than the previous preset voltage, as shown in fig. 4.
It should be noted that, on the basis of the technical solution of the embodiment of the present invention, in the process of programming the target word line for multiple times, the pulse voltage applied to the target word line is gradually reduced, and the voltage on the corresponding adjacent bit line of the target word line is also gradually reduced, so that when the bit number to be programmed is lower than the preset bit number, the voltage on the adjacent bit line of the target word line can also be gradually adjusted, as shown in fig. 5.
The technical scheme of the embodiment of the invention obtains the bit number to be programmed by detecting that the current pulse number on the target word line reaches the preset pulse number, increases the voltage on the adjacent word line of the target word line to the preset voltage if the bit number to be programmed is less than or equal to the preset bit number, namely dynamically adjusts the voltage of the adjacent word line according to the number of the flash memory programming pulses, solves the technical problems that although the transistor on the target word line is prevented from being wrongly programmed by continuously applying higher voltage on the adjacent word line of the target word line in the prior art, the continuously applied high voltage not only causes interference on the transistors on the other word lines, but also aggravates the damage of the device and reduces the service life of the device, and realizes that the voltage of the adjacent word line of the target word line is dynamically adjusted, so that the false programming rate of the transistor of the target word line and the adjacent word line, the interference of the voltage of the adjacent word, and the technical effect of prolonging the service life of the device is also improved.
Example two
As a preferred embodiment of the foregoing embodiment, fig. 6 is a schematic flowchart of an anti-interference programming method provided in a second embodiment of the present invention, and as described in fig. 6, the method in the embodiment of the present invention includes:
s601, obtaining the number of current pulses on the target word line.
When programming the transistors on the target word line, a certain voltage and the number of pulses corresponding to the voltage need to be applied to the control gate. Illustratively, the number of bits to be programmed on the target word line is 1000, 8 pulses are required, a pulse voltage is applied to the control gate of the target word line, during the voltage application process, the number of pulses applied to the target word line can be obtained in real time, and optionally, 1 pulse, 2 pulses and the like are applied to the target word line.
S602, judging whether the number of the current pulses reaches the preset number of pulses, if so, executing S603, and if not, executing S601.
In the process of applying pulses to the control gate of the target word line, the number of current pulses can be acquired, in order to prevent the situation that the transistor not to be programmed is also programmed from occurring in the process of programming the transistor on the target word line, whether the number of current pulses reaches a preset number of pulses is judged, optionally, the preset number of pulses is 3, and if the number of pulses reaches 3, S603 is executed; if the number of pulses programmed on the target word line does not reach 3, continuing to apply the pulse voltage to the target word line, i.e. continuing to execute S601, programming the transistor on the target word line until the number of applied pulses reaches the preset number of pulses, and then executing S603.
S603, acquiring the bit number to be programmed.
When the number of the pulses reaches the preset number of pulses, optionally, the current pulse is the 3 rd pulse, and the preset number of pulses is 3, at this time, the number of bits to be programmed on the target word line is obtained, and optionally, the number of bits to be programmed is 400.
S604, judging whether the bit number to be programmed is less than or equal to a preset bit number, if so, executing S605; if not, S601 is executed.
The preset number of bits is set by the user according to experience, and optionally, the preset number of bits may be 300, 400, 500, and the like. It should be noted that the preset number of bits should be within the range of the target number of bits. At this time, it is determined whether the number of bits to be programmed is less than or equal to the preset number of bits, and if the preset number of bits is 500, it can be known that the number of bits to be programmed is 400, and the number of bits to be programmed is less than the preset number of bits, which indicates that the number of transistors to be programmed on the target word line is small, and S605 may be performed in order to prevent the transistors other than the 1000 transistors on the target word line from being programmed by mistake. If the preset bit number is 300, the bit number to be programmed is 400, and the bit number to be programmed is larger than the preset bit number, which indicates that the preset requirement is not met, the step of executing S601 is returned, and S601-S604 are repeated until the bit number to be programmed is smaller than or equal to the preset bit number.
And S605, increasing the voltage of the adjacent word line of the target word line to a preset voltage.
When the number of bits to be programmed on the target word line satisfies a preset condition, the voltage on the bit line adjacent to the target word line can be increased to a preset voltage. The advantage of increasing the voltage on the adjacent bit line of the target word line to the preset voltage is that on one hand, the voltage on the adjacent word line can be always in a lower voltage state, and only when the preset condition is reached, the voltage of the adjacent word line is increased, so that the technical problems of interference with programming of other word lines and reduction of device loss are avoided; on the other hand, the voltage of the substrate of the transistor for writing 1 on the target word line can be increased by increasing the voltage of the adjacent word line, so that the voltage difference between the control grid and the substrate is reduced, electrons cannot be written into the floating grid in the transistor, and the technical effect that the transistor which is not wanted to be programmed is not programmed is realized.
The technical scheme of the embodiment of the invention obtains the bit number to be programmed by detecting that the current pulse number on the target word line reaches the preset pulse number, increases the voltage on the adjacent word line of the target word line to the preset voltage if the bit number to be programmed is less than or equal to the preset bit number, namely dynamically adjusts the voltage of the adjacent word line according to the number of the flash memory programming pulses, solves the technical problems that although the transistor on the target word line is prevented from being wrongly programmed by continuously applying higher voltage on the adjacent word line of the target word line in the prior art, the continuously applied high voltage not only causes interference on the transistors on other word lines, but also aggravates the damage of the device and reduces the service life of the device, realizes that the voltage of the adjacent word line of the target word line is dynamically adjusted, not only reduces the wrong programming rate of the transistor of the target word line and the adjacent word line, the interference of the voltage of the adjacent word, and the technical effect of prolonging the service life of the device is also improved.
EXAMPLE III
Fig. 7 is a schematic structural diagram of an interference-free programming apparatus according to a third embodiment of the present invention, where the apparatus includes: a detection module 710 and an execution module 720. The detecting module 710 is configured to, when detecting that the current number of pulses on the target word line reaches a preset number of pulses, obtain a number of bits to be programmed; the executing module 720 is configured to increase the voltage on the adjacent word line of the target word line to a preset voltage if the bit number to be programmed is less than or equal to a preset bit number.
On the basis of the above technical solution, the apparatus further includes: the loop module is used for taking the next pulse as the current pulse when the next pulse programming of the current pulse is finished and repeatedly executing to obtain the bit number to be programmed if the bit number to be programmed is larger than the preset bit number; until the number of bits to be programmed at present is less than or equal to the preset number of bits.
On the basis of the technical solutions, the currently programmed pulse voltage of the target word line is at least 5v higher than the adjacent word line voltage of the target word line.
On the basis of the technical schemes, the bit number programmed on the word line reaches the programmed target bit number to be used as one-time programming, and the pulse voltage programmed currently on the target word line is smaller than the pulse voltage programmed at the previous time.
The technical scheme of the embodiment of the invention obtains the bit number to be programmed by detecting that the current pulse number on the target word line reaches the preset pulse number, increases the voltage on the adjacent word line of the target word line to the preset voltage if the bit number to be programmed is less than or equal to the preset bit number, namely dynamically adjusts the voltage of the adjacent word line according to the number of the flash memory programming pulses, solves the technical problems that although the transistor on the target word line is prevented from being wrongly programmed by continuously applying higher voltage on the adjacent word line of the target word line in the prior art, the continuously applied high voltage not only causes interference on the transistors on other word lines, but also aggravates the damage of the device and reduces the service life of the device, realizes that the voltage of the adjacent word line of the target word line is dynamically adjusted, not only reduces the wrong programming rate of the transistor of the target word line and the adjacent word line, the interference of the voltage of the adjacent word, and the technical effect of prolonging the service life of the device is also improved.
The anti-interference programming device provided by the embodiment of the invention can execute the anti-interference programming method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
It should be noted that, the units and modules included in the apparatus are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the embodiment of the invention.
Example four
Fig. 8 is a schematic structural diagram of an apparatus according to a fourth embodiment of the present invention. FIG. 8 illustrates a block diagram of an exemplary device 80 suitable for use in implementing embodiments of the present invention. The device 80 shown in fig. 8 is only an example and should not bring any limitation to the function and scope of use of the embodiments of the present invention.
As shown in FIG. 8, device 80 is embodied in a general purpose computing device. The components of device 40 may include, but are not limited to: one or more processors or processing units 801, a system memory 802, and a bus 803 that couples various system components including the system memory 802 and the processing unit 801.
The system memory 402 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)804 and/or cache memory 805. The device 80 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 806 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 8, and commonly referred to as a "hard drive"). Although not shown in FIG. 8, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 803 by one or more data media interfaces. Memory 802 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 808 having a set (at least one) of program modules 807 may be stored, for instance, in memory 802, such program modules 807 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may include an implementation of a network environment. Program modules 807 generally perform the functions and/or methodologies of embodiments of the present invention as described herein.
The processing unit 801 executes various functional applications and data processing by running programs stored in the system memory 802, for example, to implement a tamper resistant programming method provided by embodiments of the present invention.
EXAMPLE five
Embodiments of the present invention also provide a storage medium containing computer-executable instructions that, when executed by a computer processor, perform a method for tamper-resistant programming.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for embodiments of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A tamper-resistant programming method, comprising:
when detecting that the number of current programming pulses on a target word line reaches a preset number of pulses, acquiring the number of bits to be programmed;
and if the bit number to be programmed is less than or equal to a preset bit number, increasing the voltage on the adjacent word line of the target word line to a preset voltage.
2. The method of claim 1, further comprising:
if the bit number to be programmed is larger than the preset bit number, when the next pulse programming of the current pulse is finished, taking the next pulse as the current pulse, and repeatedly executing to obtain the bit number to be programmed; until the current bit number to be programmed is less than or equal to the preset bit number.
3. The method of claim 1, wherein a currently programmed pulse voltage of the target word line is at least 5v higher than an adjacent word line voltage of the target word line.
4. The method according to claim 1, wherein the programming is performed as one-time programming, in which the number of bits programmed on the word line reaches a target number of bits programmed, and the pulse voltage of the current programming on the target word line is smaller than the pulse voltage of the previous programming.
5. A tamper-resistant programming device, comprising:
the detection module is used for acquiring the bit number to be programmed when the number of the current programming pulses on the target word line reaches the preset pulse number;
and the execution module is used for increasing the voltage of the adjacent word line of the target word line to a preset voltage if the bit number to be programmed is less than or equal to a preset bit number.
6. The apparatus of claim 5, further comprising:
the loop module is used for taking the next pulse as the current pulse when the next pulse programming of the current pulse is finished and repeatedly executing to obtain the bit number to be programmed if the bit number to be programmed is larger than the preset bit number; until the current bit number to be programmed is less than or equal to the preset bit number.
7. The apparatus of claim 5, wherein a currently programmed pulse voltage of the target word line is at least 5v higher than an adjacent word line voltage of the target word line.
8. The apparatus of claim 5, wherein the programming is performed for one time when the number of bits programmed on the word line reaches the target number of bits programmed, and the pulse voltage of the current programming on the target word line is smaller than the pulse voltage of the previous programming.
9. A tamper-resistant programming device, the device comprising:
one or more processors;
storage means for storing one or more programs; when executed by the one or more processors, cause the one or more processors to implement the tamper resistant programming method of any of claims 1-4.
10. A storage medium containing computer executable instructions for performing the tamper resistant programming method of any one of claims 1-4 when executed by a computer processor.
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