CN110554842A - Method for simulating EEPROM (electrically erasable programmable read-Only memory) by using flash memory - Google Patents
Method for simulating EEPROM (electrically erasable programmable read-Only memory) by using flash memory Download PDFInfo
- Publication number
- CN110554842A CN110554842A CN201910841421.XA CN201910841421A CN110554842A CN 110554842 A CN110554842 A CN 110554842A CN 201910841421 A CN201910841421 A CN 201910841421A CN 110554842 A CN110554842 A CN 110554842A
- Authority
- CN
- China
- Prior art keywords
- page
- valid
- byte
- bytes
- working
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000013500 data storage Methods 0.000 description 13
- 238000013507 mapping Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The invention relates to a method for simulating an EEPROM (electrically erasable programmable read-Only memory) by using a flash memory, which comprises the following steps of: providing one or more pages of a flash memory as a first page; providing one or more pages of the flash memory as a second page; determining the first page as a working page, wherein the working page comprises a functional area, wherein the valid state of each byte of at least one part of the working page is stored in the functional area; writing one or more bytes of a working page; reading one or more valid bytes of a working page, wherein the valid status of the valid bytes is valid; formatting the second page after the working page is full; and determining the second page as a work page. The invention also relates to a storage system. The invention can obviously improve the ratio of the effective data to the used flash memory, thereby improving the utilization rate of the flash memory.
Description
Technical Field
The invention relates to the field of embedded software, in particular to a method for simulating an EEPROM (electrically erasable programmable read-Only memory) by using a flash memory. The invention further relates to a storage system.
background
In embedded development, EEPROMs are used in many product scenarios to store non-volatile data that needs to be saved in an application. However, at present, a mainstream microprocessor such as an MCU has a large flash memory (flash) space without an EEPROM because the cost of the product is significantly increased if an EEPROM device is additionally added. Therefore, many applications use embedded software to simulate EEPROM using flash memory to meet product requirements.
However, one of the limitations of the current flash simulation scheme is that the storage of valid data accounts for a low percentage of the total flash used, about 50%, resulting in a low flash utilization.
Disclosure of Invention
The object of the invention is to provide a method for simulating an EEPROM using a flash memory and a storage system, by means of which method and/or system the ratio of useful data to the amount of flash memory used can be significantly increased, and thus the utilization of the flash memory can be increased.
In a first aspect of the invention, this task is solved by a method for emulating an EEPROM using a flash memory, comprising the steps of:
Providing one or more pages of a flash memory as a first page;
providing one or more pages of the flash memory as a second page;
Determining the first page as a working page, wherein the working page comprises a functional area in which a valid status of each byte of at least a portion (e.g., a data storage area) of the working page is stored;
writing one or more bytes of a working page and updating a valid status of the one or more bytes to valid in the functional area after the successful writing of the one or more bytes;
reading one or more valid bytes of a working page, wherein the valid status of the valid bytes is valid;
Formatting the second page after the working page is full; and
The second page is determined to be a work page.
In a preferred embodiment of the invention, it is provided that the formatting of the second page after the working page is full comprises the following steps:
determining the effective state of the last byte of the working page in the functional area; and
If the valid state is valid, the second page is formatted.
with this preferred approach, it can be determined that the read content is successfully written content, i.e., valid bytes. For this purpose, the functional areas are all, for example, "1" at initialization, and after a byte of the memory area has been successfully written, the functional area corresponding to said byte is overwritten with, for example, "0", wherein here "1" indicates that the byte is invalid and "0" indicates that the byte is valid, or vice versa.
In one embodiment of the invention, the size of the page is 2 n bytes, n being a natural number.
in a further embodiment of the invention, it is provided that the lowest bit of the functional area represents the valid state of the first byte of the working page. The size of the functional area is determined according to the size of the data storage area. With this embodiment, it is possible to know whether the work page is full by checking the last byte or the last bit of the functional area, thereby saving processing time.
In a further embodiment of the invention, it is provided that the method further comprises the following steps:
A flag is maintained in the first page and the second page indicating that the page is a working page. For example, a flag bit of "0" may be set to indicate a working page and "1" to indicate a non-working page. Or the opposite is also conceivable.
In one embodiment of the invention, it is provided that the method further comprises the steps of: a single valid byte is looked up.
in a preferred embodiment of the invention, it is provided that the search for a single valid byte comprises the following steps:
Searching the byte where the single effective byte is located in the functional area through a dichotomy; and
The single byte is looked up in this byte by the dichotomy.
With this preferred approach, the time to find a particular valid byte can be significantly saved.
in one embodiment of the invention, it is provided that the method further comprises the following steps:
Multiple EEPROMs are combined into a larger EEPROM.
In a second aspect of the invention, the aforementioned task is solved by a storage system comprising:
A flash memory configured to provide one or more pages of the flash memory as a first page and to provide one or more pages of the flash memory as a second page; and
A controller configured to perform the following acts:
providing one or more pages of a flash memory as a first page;
providing one or more pages of the flash memory as a second page;
Determining the first page as a working page, wherein the working page comprises a functional area, and the effective state of each byte of the working page is stored in the functional area;
Writing one or more bytes of a working page and updating a valid status of the one or more bytes to valid in the functional area after the successful writing of the one or more bytes;
Reading one or more valid bytes of a working page, wherein the valid status of the valid bytes is valid;
Formatting the second page after the working page is full; and
the second page is determined to be a work page.
In one embodiment of the invention, it is provided that the memory system is used for a microcontroller unit MCU.
the invention has at least the following beneficial effects: in the invention, the effective state of each byte of the data storage area (or the whole page) is maintained by using the functional area, so that better address mapping is realized under the condition of omitting the configuration of a virtual address for each byte, the effective data utilization rate of the flash memory is improved, the erasing times of all data units are reduced, the storage life is prolonged, the average access time is shortened, and the poor expandability is improved; meanwhile, by maintaining the valid state of each byte of the data storage area, only the successfully written byte (namely the valid byte) can be better ensured to be read, thereby avoiding system failure caused by reading illegal data.
drawings
the invention is further elucidated with reference to the drawings in conjunction with the detailed description.
FIG. 1 is a schematic diagram showing the data structure of an EEPROM simulated in accordance with the present invention; and
Fig. 2 shows a flow of the method according to the invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, "disposed on …", "disposed over …" and "disposed over …" do not exclude the presence of an intermediate therebetween, unless otherwise specified. Further, "disposed on or above …" merely indicates the relative positional relationship between two components, and may also be converted to "disposed below or below …" and vice versa in certain cases, such as after reversing the product direction.
in the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
in the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal". By analogy, in the present invention, the terms "perpendicular", "parallel" and the like in the directions of the tables also cover the meanings of "substantially perpendicular", "substantially parallel".
The numbering of the steps of the methods of the present invention does not limit the order of execution of the steps of the methods. Unless specifically stated, the method steps may be performed in a different order.
Although the minimum memory location is represented by bytes (Byte) in the present invention, the present invention is not limited thereto, and in other embodiments, minimum memory locations of other sizes, such as bits (bit), words (word), or double words (dword), etc., may be used.
The present invention is based on the following insight of the inventors: most of the existing flash memory analog EEPROMs adopt a plurality of flash memory pages to alternate, 1-byte virtual addresses are configured for each byte of data, and the reading and writing of the data adopt a mode of polling writing and inquiring reading in sequence to realize a basic EEPROM data access function. However, the method has the following defects in practical application: 1. the storage of effective data only occupies 50% of the storage capacity of the actual flash memory at most, and the utilization rate is low; 2. the lower storage efficiency also reduces the times that the same flash memories simulate the EEPROMs with the same size (even if the EEPROM with one byte is not used, the single byte erasing life is not flashed at most 512 times); 3. when data is written, because the data is written in sequence, the writing time of the data is longer and longer in the process of storing the analog EEPROM data; similarly, the data reading adopts reverse reading, so that the initial data reading time is longer when the actual data is read; in practical application, the access time is inconsistent every time, and uncertainty is brought to application with higher time requirement; 4. in a general analog EEPROM application algorithm, a small number of stored bytes are relatively fixed, and portability and expandability due to different application requirements are poor. In the invention, the effective state of each byte of the data storage area is maintained by using the functional area, so that better address mapping is realized under the condition of omitting the configuration of a virtual address for each byte, the effective data utilization rate of the flash memory is improved, the erasing times of all data units are reduced, the storage life is short, the data storage time is stabilized, the average access time is shortened, and the poor expandability is improved.
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
Fig. 1 shows a schematic diagram of a data structure of an EEPROM 100 simulated according to the present invention.
as shown in FIG. 1, an EEPROM 100 simulated in accordance with the present invention includes a first page 101 and a second page 102, where the first and second pages 102 are each 512bytes (Byte) in size, although other sizes of pages are contemplated in other embodiments. Where the first page 101 is set as a work page. Here, the simulation method is: the storage of the analog EEPROM is realized by using a flash memory with at least 2 pages (a first page and a second page, 2x512Bytes), wherein the first page can be written after being erased, the second page is used for recovering effective data in the first page after the first page is fully written, the second page can be used for writing data at the moment, and the first page is used for recovering data in the second page after the second page is fully written, so that the storage of the analog EEPROM is realized in a reciprocating cycle. In addition, a space (e.g., a flag bit) for a fixed address is reserved in each page to store and indicate the current state of each page. In this example, the minimum unit of data that emulates an EEPROM to hold data in flash memory is one byte (8 bits). In order to save storage space, the invention does not relate the address to the physical address of the flash memory by adopting a virtual address mapping mode as in the prior art, namely when the EEPROM is stored, the address of each byte is expressed by 1byte size and is from 0x00 to (EEPROM size-1). In contrast, the present invention employs a bit address mapping scheme, i.e., 1bit is used to indicate the valid status of each byte of at least a portion of the page (e.g., data storage area), for example, when the bit is 0, the byte is valid, and when the bit is 1, the byte is invalid. Here, the lowest bit of the functional area represents the valid state of the first byte of the work page. The size of the functional area is determined according to the size of the data storage area. The flag toggle required to effect a two page state switch of the flash memory may be stored, for example, in the last 1byte of each page.
EEPROM 100, which is emulated in accordance with the present invention, also includes data storage area 104, here 448 bytes, which is used to store valid data. The first and second pages 102 will be written sequentially to store data. When one page is full, another page is formatted for writing data, and so on.
the EEPROM 100 emulated according to the present invention further comprises a functional area 103, in which functional area 103 the status of each byte of the first page 101 is stored. Here, the size of the functional area 103 is 64 bytes. Here, for example, the first 54 bytes in the functional area 103 are used for mapping of the data storage area (i.e., address mapping area), and the remaining 8 bytes are redundant bytes used for other functions, such as flag bits, and status flags indicating whether the page is fully written. For example, the last byte is used to indicate whether the page is full. The basic background of the design is that the erasing life of the EEPROM is realized at least 10W times under the maximum configuration according to the erasing life of the mainstream FLASH being 1W times and the data storage occupying 1K Bytes of FLASH storage.
The invention has at least the following characteristics:
1. the address mapping adopts a single-bit mode, namely 1bit (bit) mapping 1Byte (Byte) data according to the characteristics of the memory, and the mode can improve the storage utilization rate of effective data to be stable 87.5%;
2. the single-byte erasing life can also reach 448x2 times or 896 times of that of FLASH, and the maximum configuration of 64 bytes can also realize that the single-byte life of EEPROM reaches 14 times of that of FLASH (namely 14W times);
3. The design method establishes a fixed mapping relation between an address flag bit and a storage data address, so that a 'double dichotomy' is adopted according to the characteristics of the design method and a memory when effective data access is carried out, the searching time complexity is O (log2n), namely log2n +1 times is needed in the worst case, in the embodiment, nested application of the dichotomy is used, namely firstly, the 'dichotomy' is used for searching a byte where a target address is located in an address mapping area (63 bytes), and then the 'dichotomy' is used for searching a bit corresponding to the target address in the byte (8 bits), so that the maximum searching times of an EEPROM simulating 1byte is 7+ 4-11 times in the worst case, and the average searching times is about 5-6 times. The maximum number of searches required in the conventional method is about 256 (i.e., the number of accesses to the most valid data) and reaches 128 times on average. Therefore, the method greatly shortens the access time of the analog EEPROM.
4. the design designs flexibly configurable simulated EEPROMs with several sizes according to 80% application conditions of the market, developers can configure parameters according to actual requirements and use the configured parameters, in addition, the simulated EEPROMs are provided for users in a driving library mode, the users do not need to modify internal codes, the realization method does not need to be concerned, and the users only need to configure the values of the parameters at software interfaces.
5. in addition, the analog EEPROM can also be regarded as a single-chip EEPROM, and if a larger EEPROM storage space is required in practical special applications, multiple pieces of analog EEPROMs can be expanded to use, for example: two 64-byte analog EEPROMs are used to implement a 128-byte analog EEPROM, but this application also requires twice as much FLASH space to store valid data.
fig. 2 shows a flow of a method 200 according to the invention.
at step 202, one or more pages of flash memory are provided as a first page.
At step 204, one or more pages of the flash memory are provided as a second page.
in step 206, the first page is determined to be a work page, wherein the work page comprises a functional area in which a valid status of each byte of at least a portion of the work page is stored.
at step 208, one or more bytes of the working page are written and the valid status of the one or more bytes is updated to valid in the functional area after the successful writing of the one or more bytes.
At step 210, one or more valid bytes of a work page are read, wherein the valid status of the valid bytes is valid.
at step 212, the second page is formatted after the working page is full.
At step 214, the second page is determined to be a work page.
The invention has at least the following beneficial effects: in the invention, the effective state of each byte of the data storage area (or the whole page) is maintained by using the functional area, so that better address mapping is realized under the condition of omitting the configuration of a virtual address for each byte, the effective data utilization rate of the flash memory is improved, the erasing times of all data units are reduced, the storage life is prolonged, the average access time is shortened, and the poor expandability is improved; meanwhile, by maintaining the valid state of each byte of the data storage area, only the successfully written byte (namely the valid byte) can be better ensured to be read, thereby avoiding system failure caused by reading illegal data.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.
Claims (10)
1. A method of emulating an EEPROM using a flash memory, comprising the steps of:
providing one or more pages of a flash memory as a first page;
Providing one or more pages of the flash memory as a second page;
determining the first page as a working page, wherein the working page comprises a functional area, wherein the valid state of each byte of at least one part of the working page is stored in the functional area;
Writing one or more bytes of a working page and updating a valid status of the one or more bytes to valid in the functional area after the successful writing of the one or more bytes;
reading one or more valid bytes of a working page, wherein the valid status of the valid bytes is valid;
Formatting the second page after the working page is full; and
the second page is determined to be a work page.
2. The method of claim 1, formatting the second page after the working page is full comprises the steps of:
determining the effective state of the last byte of the working page in the functional area; and
if the valid state is valid, the second page is formatted.
3. the method of claim 1, wherein the size of the page is 2 n bytes, n being a natural number.
4. The method of claim 1, wherein the lowest order bit of the functional area represents a valid state representing a first byte of the work page.
5. the method of claim 1, further comprising the steps of:
A flag is maintained in the first page and the second page indicating that the page is a working page.
6. The method of claim 1, further comprising the step of: a single valid byte is looked up.
7. The method of claim 1, wherein finding a single valid byte comprises the steps of:
Searching the byte where the single effective byte is located in the functional area through a dichotomy; and
the single byte is looked up in this byte by the dichotomy.
8. the method of claim 1, further comprising the steps of:
multiple EEPROMs are combined into a larger EEPROM.
9. a storage system, comprising:
a flash memory configured to provide one or more pages of the flash memory as a first page and to provide one or more pages of the flash memory as a second page; and
A controller configured to perform the following acts:
Providing one or more pages of a flash memory as a first page;
Providing one or more pages of the flash memory as a second page;
Determining the first page as a working page, wherein the working page comprises a functional area, and the effective state of each byte of the working page is stored in the functional area;
writing one or more bytes of a working page and updating a valid status of the one or more bytes to valid in the functional area after the successful writing of the one or more bytes;
reading one or more valid bytes of a working page, wherein the valid status of the valid bytes is valid;
Formatting the second page after the working page is full; and
The second page is determined to be a work page.
10. the memory system according to claim 9, wherein the memory system is used for a micro control unit MCU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910841421.XA CN110554842A (en) | 2019-09-06 | 2019-09-06 | Method for simulating EEPROM (electrically erasable programmable read-Only memory) by using flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910841421.XA CN110554842A (en) | 2019-09-06 | 2019-09-06 | Method for simulating EEPROM (electrically erasable programmable read-Only memory) by using flash memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110554842A true CN110554842A (en) | 2019-12-10 |
Family
ID=68739330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910841421.XA Pending CN110554842A (en) | 2019-09-06 | 2019-09-06 | Method for simulating EEPROM (electrically erasable programmable read-Only memory) by using flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110554842A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111708487A (en) * | 2020-05-26 | 2020-09-25 | 杭州涂鸦信息技术有限公司 | Data storage method and device and computer storage medium |
| TWI719829B (en) * | 2020-01-14 | 2021-02-21 | 瑞昱半導體股份有限公司 | Data programming method, data reading method, and memory device |
| CN118012355A (en) * | 2024-04-10 | 2024-05-10 | 上海朔集半导体科技有限公司 | Analog EEPROM, analog controller, storage medium, and method of controlling analog EEPROM |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632765A (en) * | 2004-12-31 | 2005-06-29 | 大唐微电子技术有限公司 | A flash memory file system management method |
| CN101488153A (en) * | 2009-02-12 | 2009-07-22 | 浙江大学 | Method for implementing high-capacity flash memory file system in embedded type Linux |
| US20100070686A1 (en) * | 2006-12-07 | 2010-03-18 | Nxp, B.V. | Method and device for reconfiguration of reliability data in flash eeprom storage pages |
| CN102004698A (en) * | 2010-11-23 | 2011-04-06 | 深圳市江波龙电子有限公司 | Flash memory management method and system |
| CN110045927A (en) * | 2019-04-16 | 2019-07-23 | 华大半导体有限公司 | A method of there is the EEPROM of atomic operation characteristic using flash memory simulation |
-
2019
- 2019-09-06 CN CN201910841421.XA patent/CN110554842A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632765A (en) * | 2004-12-31 | 2005-06-29 | 大唐微电子技术有限公司 | A flash memory file system management method |
| US20100070686A1 (en) * | 2006-12-07 | 2010-03-18 | Nxp, B.V. | Method and device for reconfiguration of reliability data in flash eeprom storage pages |
| CN101488153A (en) * | 2009-02-12 | 2009-07-22 | 浙江大学 | Method for implementing high-capacity flash memory file system in embedded type Linux |
| CN102004698A (en) * | 2010-11-23 | 2011-04-06 | 深圳市江波龙电子有限公司 | Flash memory management method and system |
| CN110045927A (en) * | 2019-04-16 | 2019-07-23 | 华大半导体有限公司 | A method of there is the EEPROM of atomic operation characteristic using flash memory simulation |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI719829B (en) * | 2020-01-14 | 2021-02-21 | 瑞昱半導體股份有限公司 | Data programming method, data reading method, and memory device |
| CN113126885A (en) * | 2020-01-14 | 2021-07-16 | 瑞昱半导体股份有限公司 | Data writing method, data reading method and storage device |
| CN111708487A (en) * | 2020-05-26 | 2020-09-25 | 杭州涂鸦信息技术有限公司 | Data storage method and device and computer storage medium |
| CN118012355A (en) * | 2024-04-10 | 2024-05-10 | 上海朔集半导体科技有限公司 | Analog EEPROM, analog controller, storage medium, and method of controlling analog EEPROM |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112433956B (en) | Sequential write based partitioning in a logical-to-physical table cache | |
| US8041884B2 (en) | Controller for non-volatile memories and methods of operating the memory controller | |
| CN102792284B (en) | Memory devices loss equalization technology | |
| US20080077728A1 (en) | Mapping information managing apparatus and method for non-volatile memory supporting different cell types | |
| US20070016719A1 (en) | Memory device including nonvolatile memory and memory controller | |
| US7925821B2 (en) | Nonvolatile semiconductor storage device and method of managing the same | |
| JP2005242897A (en) | Flash disk drive | |
| US9921954B1 (en) | Method and system for split flash memory management between host and storage controller | |
| CN112534415B (en) | Data validity tracking in non-volatile memory | |
| US20140372710A1 (en) | System and method for recovering from an unexpected shutdown in a write-back caching environment | |
| CN107045423B (en) | Memory device and data access method thereof | |
| US20130013885A1 (en) | Memory storage device, memory controller, and method for identifying valid data | |
| CN110554842A (en) | Method for simulating EEPROM (electrically erasable programmable read-Only memory) by using flash memory | |
| CN106528441B (en) | Data processing method and device for simulating EEPROM (electrically erasable programmable read-Only memory) and electronic equipment | |
| CN103136111A (en) | Data writing method, memorizer controller and memorizer storage device | |
| JP2000011677A (en) | Flash memory system | |
| CN112882649A (en) | Data storage device and non-volatile memory control method | |
| CN116301601A (en) | Data storage method and device for embedded system built-in Flash simulation EEPROM | |
| CN113885808A (en) | Mapping information recording method, memory control circuit unit and memory device | |
| CN111026325A (en) | Flash memory controller, control method of flash memory controller and related electronic device | |
| CN105653478B (en) | Serial flash controller, serial flash control method and serial flash control system | |
| JP2000285001A (en) | Semiconductor flash memory device and its control method | |
| CN112466371B (en) | Method for circularly utilizing analog byte erasing function of flash memory | |
| CN111258498B (en) | FLASH memory management method | |
| JP3826115B2 (en) | Storage device, memory management method, and program |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20220719 Address after: 201210 floor 10, block a, building 1, No. 1867, Zhongke Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Applicant after: Xiaohua Semiconductor Co.,Ltd. Address before: Room 305, block Y1, 112 liangxiu Road, Pudong New Area, Shanghai 201203 Applicant before: HUADA SEMICONDUCTOR Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191210 |
|
| RJ01 | Rejection of invention patent application after publication |