CN110554240A - Impedance detection circuit and method for charging interface and terminal equipment - Google Patents
Impedance detection circuit and method for charging interface and terminal equipment Download PDFInfo
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- CN110554240A CN110554240A CN201910849015.8A CN201910849015A CN110554240A CN 110554240 A CN110554240 A CN 110554240A CN 201910849015 A CN201910849015 A CN 201910849015A CN 110554240 A CN110554240 A CN 110554240A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits
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Abstract
the application is suitable for the technical field of terminals, and provides an impedance detection circuit and method of a charging interface and terminal equipment. The embodiment of the application provides the impedance detection circuit of the charging interface only comprising the excitation module and the sampling calculation module, so that the excitation module is electrically connected with the processor and the pin channel to be detected, and when the charging interface is not connected with an external signal, the processor is controlled to output an excitation signal to the pin channel to be detected; the sampling calculation module is electrically connected with the pin channel to be detected, when the excitation module outputs an excitation signal, the electric signal in the pin channel to be detected is synchronously sampled and processed to obtain the equivalent impedance value of the pin to be detected, the impedance of the pin to be detected can be directly detected when the charging interface is in an idle state, the accuracy is high, the external equipment does not need to be relied on, the charging interface does not need to have external power supply capacity, and the structure is simple.
Description
Technical Field
The application belongs to the technical field of terminals, and particularly relates to an impedance detection circuit and method for a charging interface and terminal equipment.
Background
With the continuous development of terminal technologies, various terminal devices having charging interfaces, such as mobile phones, tablet computers, personal digital assistants, smart bands, AI (Artificial Intelligence) robots, AR (Augmented Reality) glasses, and the like, are developed. The impedance of the charging interface can change under the conditions of moisture, liquid inlet, impurity mixing, damage, short circuit and the like. By detecting the impedance of the charging interface of the terminal equipment, the problems of charging abnormity or burning of the charging interface and the like caused by the impedance abnormity of the charging interface can be effectively prevented.
Content of application
In view of this, embodiments of the present application provide an impedance detection circuit and method for a charging interface, and a terminal device, which can directly detect an impedance of a pin to be detected when the charging interface is in an idle state, and have high accuracy, and do not need to rely on an external device and the charging interface does not need to have an external power supply capability.
A first aspect of an embodiment of the present application provides an impedance detection circuit for a charging interface, including;
the excitation module is used for being electrically connected with the processor and the pin channel to be detected, and when the external signal is not accessed to the charging interface, the excitation module is controlled by the processor to output an excitation signal to the pin channel to be detected, and the pin channel to be detected is electrically connected with the pin to be detected of the charging interface;
And the sampling calculation module is used for being electrically connected with the pin channel to be detected, and synchronously sampling the electric signal in the pin channel to be detected and processing the electric signal to obtain the equivalent impedance value of the pin to be detected when the excitation module outputs an excitation signal.
In one embodiment, the excitation module is configured to periodically output an excitation signal to the pin channel to be tested at a preset frequency under the control of the processor when the external signal is not accessed to the charging interface.
In one embodiment, the excitation module comprises:
the controllable excitation source is electrically connected with the processor and is controlled by the processor to output an excitation signal when the external signal is not accessed to the charging interface;
And the resistance network is electrically connected with the controllable excitation source, the to-be-tested pin channel and the sampling calculation module and is used for carrying out current sampling or voltage sampling on the excitation signal.
in one embodiment, the excitation module further includes a backflow prevention unit electrically connected between the controllable excitation source and the resistor network, and configured to isolate interference, caused by an external signal accessed by the charging interface, to the controllable excitation source.
in one embodiment, the backflow prevention unit includes any one of a diode, a transistor, a field effect transistor, a relay, a thyristor, and a semiconductor switch integrated circuit.
in one embodiment, the controllable stimulus source comprises any one of a voltage source, a current source, and a stimulus signal output port of a programmable logic device, a logic element, an operational amplifier, and a comparator;
The resistance network comprises at least two sampling resistors connected in series, parallel or series-parallel.
in one embodiment, the sample computation module comprises:
the sampling unit is used for being electrically connected with the pin channel to be tested, and synchronously sampling the electric signal in the pin channel to be tested and converting the electric signal into a digital signal when the excitation module outputs an excitation signal;
And the calculating unit is electrically connected with the sampling unit and used for calculating the equivalent impedance value of the pin to be detected according to the digital signal.
In one embodiment, the pin to be tested is a power pin, and the pin channel to be tested is a power line.
A second aspect of the embodiments of the present application provides an impedance detection method for a charging interface, including;
Detecting whether the charging interface is connected with an external signal or not;
When the external signal is not accessed to the charging interface, outputting an excitation signal to a pin channel to be tested, which is electrically connected with a pin to be tested of the charging interface;
And synchronously sampling the electric signals in the channel of the pin to be detected and processing the electric signals to obtain the equivalent impedance value of the pin to be detected.
A third aspect of the embodiments of the present application provides a terminal device, including a processor, a charging interface, a pin channel to be tested, a memory, an impedance detection circuit according to the first aspect of the embodiments of the present application, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the impedance detection method according to the second aspect of the embodiments of the present application when executing the computer program.
a fourth aspect of the embodiments of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps of the impedance detection method according to the second aspect of the embodiments of the present application.
In a first aspect of the embodiments of the present application, an impedance detection circuit is provided that includes only a charging interface of an excitation module and a sampling calculation module, so that the excitation module is electrically connected to a processor and a pin channel to be tested, and when the charging interface is not connected to an external signal, the processor controls the output of an excitation signal to the pin channel to be tested; the sampling calculation module is electrically connected with the pin channel to be detected, when the excitation module outputs an excitation signal, the electric signal in the pin channel to be detected is synchronously sampled and processed to obtain the equivalent impedance value of the pin to be detected, the impedance of the pin to be detected can be directly detected when the charging interface is in an idle state, the accuracy is high, the external equipment does not need to be relied on, the charging interface does not need to have external power supply capacity, and the structure is simple.
according to the second aspect of the embodiment of the application, whether the external signal is accessed through detecting the charging interface or not can be guaranteed to output the excitation signal to the pin channel to be detected which is electrically connected with the pin to be detected of the charging interface when the charging interface is not accessed with the external signal and is in an idle state, synchronous sampling is carried out on the electric signal in the pin channel to be detected and processed to obtain the equivalent impedance value of the pin to be detected, the impedance of the pin to be detected can be directly detected, the accuracy is high, and the external power supply capability does not need to be provided by relying on external equipment and the charging interface.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a first structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 2 is a schematic diagram of a second structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 3 is a schematic structural diagram of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 4 is a schematic diagram of a fourth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a fifth impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 6 is a schematic diagram illustrating a sixth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
fig. 7 is a schematic diagram illustrating a seventh structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
fig. 8 is an eighth structural schematic diagram of an impedance detection circuit of a charging interface according to an embodiment of the present application;
fig. 9 is a schematic diagram of a ninth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 10 is a schematic diagram of a tenth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
fig. 11 is a schematic diagram of an eleventh structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
fig. 12 is a schematic diagram of a twelfth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 13 is a schematic diagram of a thirteenth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 14 is a schematic diagram illustrating a fourteenth structure of an impedance detection circuit of a charging interface according to an embodiment of the present application;
Fig. 15 is a schematic flowchart of an impedance detection method of a charging interface according to an embodiment of the present application;
Fig. 16 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
in order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the drawings described above, are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
As shown in fig. 1, an embodiment of the present application provides an impedance detection circuit 1 of a charging interface, including:
The excitation module 10 is used for being electrically connected with the processor 2 and the pin channel 3 to be detected, when the external signal is not accessed to the charging interface, the excitation module is controlled by the processor 2 to output an excitation signal to the pin channel 3 to be detected, and the pin channel 3 to be detected is electrically connected with the pin 4 to be detected of the charging interface;
And the sampling calculation module 20 is used for being electrically connected with the pin channel 3 to be tested, and synchronously sampling the electric signal in the pin channel 3 to be tested and processing the electric signal to obtain the equivalent impedance value of the pin 4 to be tested when the excitation module 10 outputs the excitation signal.
Fig. 1 shows an exemplary equivalent impedance 41 of the pin 4 to be tested, which equivalent impedance 41 is schematically illustrated as a resistor.
in application, the charging interface may be a charging interface of various terminal devices such as a mobile phone, a tablet computer, a personal digital assistant, an intelligent bracelet, an AI robot, and AR glasses. The charging interface may be a USB interface based on any Type of USB communication protocol, for example, a Mini USB interface, a Micro USB interface, a standard USB interface, and the charging interface may also be a Dock interface, a Lightning interface, a Type C interface, or the like.
in Application, the Processor is an existing Processor in the terminal device, and may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), other general purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The processor may be specifically a power management chip or a charging interface controller. For example, when the charging interface is a USB interface, the processor may be a USB controller; when the interface that charges is Type C interface, the treater can be Type C controller.
in application, the pin to be tested is the existing pin of the charging interface. The pin channel to be tested is an existing signal wire which is led out to the processor from the pin to be tested of the charging interface. When the pin to be tested is a power pin, the pin channel to be tested is a power line. For example, when the charging interface is a USB interface, the power pin may be a +5V pin or a VCC pin; when the interface that charges is Type C interface, the power pin can be the VBUS pin.
in application, the processor is used for detecting whether the charging interface is connected with an external signal. The charging interface is accessed with an external signal, namely the charging interface is connected to the external device, and the non-accessed external signal indicates that the charging interface is not connected to the external device or connected to the external device but has no signal transmission. The external equipment can be any equipment which can be connected with a charging interface through a data line, such as a power adapter, a charger baby, a computer host, a notebook computer, a sound box, an earphone and the like. The external signal may be a power signal or a data signal, and the power signal may be a voltage signal or a current signal.
in an application, the excitation module comprises a controllable excitation source for outputting an excitation signal, and the excitation signal with a preset size can be output under the control of the processor. The excitation signal may be a voltage signal or a current signal.
in one embodiment, the excitation module is configured to periodically output an excitation signal to the pin channel to be tested at a preset frequency under the control of the processor when the external signal is not accessed to the charging interface.
in application, the preset frequency can be set according to actual needs, and the high preset frequency increases the detection times in unit time, so that the accuracy of the detection result can be improved; the preset frequency is low, so that the detection times in unit time are few, the long-time electrification of the pin to be detected can be avoided, and the corrosive influence on the pin to be detected can be effectively reduced.
In application, the sampling calculation module has data sampling and calculation functions, and a data sampling device with preset sampling precision can be selected according to actual needs to realize the data sampling function, for example, an analog-to-digital converter. And when the excitation module outputs the excitation signal, the sampling calculation module synchronously samples the electric signal in the channel of the pin to be detected, converts the electric signal into a digital signal, and calculates to obtain the equivalent impedance value of the pin to be detected. The sampling calculation module can be a processor of the terminal equipment, and can also be a device which has data sampling and calculation functions and exists independently. The electrical signal may be a voltage signal or a current signal.
As shown in fig. 2, in one embodiment of the present application, the excitation module 10 includes:
the controllable excitation source 11 is electrically connected with the processor 2, and is controlled by the processor 2 to output an excitation signal when the external signal is not accessed to the charging interface;
And the resistance network 12 is electrically connected with the controllable excitation source 11, the pin channel 3 to be tested and the sampling calculation module 20, and is used for performing current sampling or voltage sampling on the excitation signal.
in one embodiment, the controllable stimulus source comprises any one of a voltage source, a current source, and a stimulus signal output port of a programmable logic device, a logic element, an operational amplifier, and a comparator;
The resistance network comprises at least two sampling resistors connected in series, parallel or series-parallel.
in an application, the controllable excitation source may be provided by a processor of the terminal device, and the excitation signal may be output through an input-output (IO) port of the processor. The programmable logic device may be a central processing unit, a graphics processor, or other general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array, a complex programmable logic device, a microprocessor, or the like. The logic elements may be AND gates, OR gates, NOT gates, NAND gates, NOR gates, and the like.
In application, the number of the sampling resistors included in the resistor network and the connection mode among the sampling resistors can be set according to actual needs, as long as the current sampling or voltage sampling requirements of the sampling calculation module can be met.
as shown in fig. 2, in the present embodiment, the sample calculation module 20 includes:
The sampling unit 21 is used for being electrically connected with the pin channel 3 to be tested, and synchronously sampling the electric signal in the pin channel 3 to be tested and converting the electric signal into a digital signal when the excitation module 10 outputs an excitation signal;
and the calculating unit 22 is electrically connected with the sampling unit 21 and is used for calculating the equivalent impedance value of the pin 4 to be measured according to the digital signal.
in application, the sampling unit may be an analog-to-digital converter with a preset sampling precision, and the computing unit may be a central processing unit, a graphics processor, or other general processors, a digital signal processor, an application specific integrated circuit, a field programmable gate array, a complex programmable logic device or other programmable logic devices, a discrete gate or transistor logic device, a discrete hardware component, or the like. A general purpose processor may be a microprocessor. The calculation unit may be a processor of the terminal device. The sampling unit and the calculating unit may be logic function units in the processor, i.e. a built-in analog-to-digital converter of the processor.
As shown in fig. 3, in an embodiment, the excitation module 10 further includes a backflow prevention unit 13 electrically connected between the controllable excitation source 11 and the resistor network 12, for isolating interference of an external signal accessed by the charging interface to the controllable excitation source 11.
In one embodiment, the backflow prevention unit includes any one of a diode, a transistor, a field effect transistor, a relay, a thyristor, and a semiconductor switch integrated circuit.
in application, the backflow prevention unit is used for preventing external signals from being reversely transmitted to the controllable excitation source, so that excitation signals output by the controllable excitation source are transmitted in a single direction sequentially through the backflow prevention unit and the resistance network, and devices with corresponding functions can be selected according to actual needs to realize the unidirectional transmission. The field effect transistor may be a P-type or N-type semiconductor field effect transistor or a junction field effect transistor.
as shown in fig. 4, the controllable excitation source 11 is exemplarily shown as an input/output port of a programmable logic device, the backflow prevention unit 13 is a diode, and the resistor network 12 includes three sampling resistors connected in series, parallel and series.
As shown in fig. 5, the controllable excitation source 11 is exemplarily shown as a current source, the backflow preventing unit 13 is a diode, and the resistor network 12 includes three sampling resistors connected in series, parallel and series.
As shown in fig. 6, the controllable excitation source 11 is exemplarily shown as a voltage source, the backflow prevention unit 13 is a diode, and the resistor network 12 includes two sampling resistors connected in series.
As shown in fig. 7, the controllable excitation source 11 is exemplarily shown as an and gate, the backflow preventing unit 13 is a diode, and the resistor network 12 includes three sampling resistors connected in series, parallel and series.
As shown in fig. 8, the controllable driving source 11 is exemplarily shown to be an operational amplifier or a comparator, the anti-backflow unit 13 is a diode, and the resistor network 12 includes three sampling resistors connected in series, parallel and series.
As shown in fig. 9, the controllable excitation source 11 is exemplarily shown as a voltage source, the backflow prevention unit 13 is a triode, and the resistor network 12 includes two sampling resistors connected in series.
as shown in fig. 10, the controllable excitation source 11 is exemplarily shown as a voltage source, the backflow prevention unit 13 is a mosfet, and the resistor network 12 includes two sampling resistors connected in series.
As shown in fig. 11, the controllable excitation source 11 is exemplarily shown as a voltage source, the back-flow prevention unit 13 is a junction field effect transistor, and the resistor network 12 includes two sampling resistors connected in series.
As shown in fig. 12, the controllable excitation source 11 is exemplarily shown as a voltage source, the backflow prevention unit 13 is a relay, and the resistor network 12 includes two sampling resistors connected in series.
As shown in fig. 13, the controllable excitation source 11 is exemplarily shown as a voltage source, the backflow prevention unit 13 is a thyristor, and the resistor network 12 includes two sampling resistors connected in series.
As shown in fig. 14, the controllable excitation source 11 is exemplarily shown as a voltage source, the backflow prevention unit 13 is a semiconductor switch integrated circuit, and the resistor network 12 includes two sampling resistors connected in series.
It should be understood that the excitation module may be configured in other structures according to different types of devices for implementing the controllable excitation source and the anti-backflow unit, and the number of the sampling resistors and the connection manner of the sampling resistors, and fig. 4 to 14 only show some possible structures by way of example, and the anti-backflow unit may be omitted in the case that the anti-backflow function is not required to be implemented.
As shown in fig. 15, an embodiment of the present application further provides an impedance detection method of a charging interface, which may be implemented based on an impedance detection circuit and executed by a processor of a terminal device, the impedance detection method including;
Step S151, detecting whether the charging interface is accessed to an external signal;
step S152, when the external signal is not accessed to the charging interface, outputting an excitation signal to a to-be-tested pin channel electrically connected with a to-be-tested pin of the charging interface;
And S153, synchronously sampling the electric signals in the channel of the pin to be detected and processing to obtain the equivalent impedance value of the pin to be detected.
In an application, step S151 may be performed by a processor, step S152 may be performed by the processor controlling the excitation module, and step S153 may be performed by the processor or the processor controlling the sampling calculation module.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
As shown in fig. 16, an embodiment of the present application provides a terminal device 100 including: the impedance detection circuit 1, the processor 2, the pin channel under test 3, the charging interface 5, the memory 6, and a computer program 61, such as an impedance detection program, stored in the memory 6 and executable on the processor 2. The processor 2, when executing the computer program 61, implements the steps in the above-described embodiment of the impedance detection method, such as the steps S151 to S153 shown in fig. 15.
illustratively, the computer program 61 may be divided into one or more software program modules, which are stored in the memory 6 and executed by the processor 2 to accomplish the present application. One or more of the software program modules may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 61 in the terminal device 100. For example, the computer program 61 may be divided into a signal detection module, a control module, and a sampling calculation module, and each module has the following specific functions:
The signal detection module is used for detecting whether the charging interface is connected with an external signal or not;
The control module is used for outputting an excitation signal to a pin channel to be detected which is electrically connected with a pin to be detected of the charging interface when the external signal is not accessed to the charging interface;
And the sampling calculation module is used for synchronously sampling the electric signals in the channel of the pin to be detected and processing the electric signals to obtain the equivalent impedance value of the pin to be detected.
The terminal device may include, but is not limited to, an impedance detection circuit 1, a processor 2, a pin channel to be tested 3, a charging interface 5, and a memory 6. Those skilled in the art will appreciate that fig. 16 is merely an example of the terminal device 100 and does not constitute a limitation of the terminal device 100 and may include more or less components than those shown, or combine certain components, or different components, e.g., the terminal device may also include input output devices, network access devices, buses, etc.
The Processor 2 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
the storage 6 may be an internal storage unit of the terminal device 100, such as a hard disk or a memory of the terminal device 100. The memory 6 may also be an external storage device of the terminal device 100, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like provided on the terminal device 100. Further, the memory 6 may also include both an internal storage unit of the terminal device 100 and an external storage device. The memory 6 is used for storing computer programs and other programs and data required by the terminal device. The memory 6 may also be used to temporarily store data that has been output or is to be output.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely illustrated, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules or modules to perform all or part of the above described functions. Each functional module in the embodiments may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module, and the integrated module may be implemented in a form of hardware, or in a form of software functional module. In addition, specific names of the functional modules are only used for distinguishing one functional module from another, and are not used for limiting the protection scope of the application. The specific working process of the modules in the system may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described apparatus/terminal device embodiments are merely illustrative, and for example, a module or a division of modules is merely a logical division, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
in addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated software program modules may be stored in a computer-readable storage medium if they are implemented as software functional modules and sold or used as separate products. Based on such understanding, all or part of the flow in the method according to the embodiments described above may be implemented by a computer program, which is stored in a computer readable storage medium and used by a processor to implement the steps of the embodiments of the methods described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. An impedance detection circuit of a charging interface is characterized by comprising;
The excitation module is used for being electrically connected with the processor and the pin channel to be detected, and when the external signal is not accessed to the charging interface, the excitation module is controlled by the processor to output an excitation signal to the pin channel to be detected, and the pin channel to be detected is electrically connected with the pin to be detected of the charging interface;
And the sampling calculation module is used for being electrically connected with the pin channel to be detected, and synchronously sampling the electric signal in the pin channel to be detected and processing the electric signal to obtain the equivalent impedance value of the pin to be detected when the excitation module outputs an excitation signal.
2. the impedance detection circuit of claim 1, wherein the excitation module is configured to periodically output an excitation signal to the pin channel to be tested at a predetermined frequency under the control of the processor when no external signal is received at the charging interface.
3. The impedance detection circuit of a charging interface of claim 1, wherein the excitation module comprises:
the controllable excitation source is electrically connected with the processor and is controlled by the processor to output an excitation signal when the external signal is not accessed to the charging interface;
And the resistance network is electrically connected with the controllable excitation source, the to-be-tested pin channel and the sampling calculation module and is used for carrying out current sampling or voltage sampling on the excitation signal.
4. The impedance detection circuit of claim 3, wherein the excitation module further comprises a backflow prevention unit electrically connected between the controllable excitation source and the resistor network, and configured to isolate interference of an external signal accessed by the charging interface with the controllable excitation source.
5. The impedance detection circuit of a charging interface of claim 4, wherein the anti-backflow unit comprises any one of a diode, a triode, a field effect transistor, a relay, a thyristor and a semiconductor switch integrated circuit.
6. The impedance detection circuit of a charging interface of any one of claims 3 to 5, wherein the controllable excitation source comprises any one of a voltage source, a current source and an excitation signal output port of a programmable logic device, a logic element, an operational amplifier and a comparator;
The resistance network comprises at least two sampling resistors connected in series, parallel or series-parallel.
7. The impedance detection circuit of a charging interface of any one of claims 1 to 5, wherein the sampling calculation module comprises:
The sampling unit is used for being electrically connected with the pin channel to be tested, and synchronously sampling the electric signal in the pin channel to be tested and converting the electric signal into a digital signal when the excitation module outputs an excitation signal;
and the calculating unit is electrically connected with the sampling unit and used for calculating the equivalent impedance value of the pin to be detected according to the digital signal.
8. A charging interface impedance detection circuit as claimed in any one of claims 1 to 5, wherein the pin to be tested is a power pin, and the pin channel to be tested is a power line.
9. The impedance detection method of the charging interface is characterized by comprising the following steps of;
Detecting whether the charging interface is connected with an external signal or not;
When the external signal is not accessed to the charging interface, outputting an excitation signal to a pin channel to be tested, which is electrically connected with a pin to be tested of the charging interface;
and synchronously sampling the electric signals in the channel of the pin to be detected and processing the electric signals to obtain the equivalent impedance value of the pin to be detected.
10. A terminal device comprising a processor, a charging interface, a pin channel to be tested, a memory, an impedance detection circuit according to any one of claims 1 to 8, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the impedance detection method according to claim 9 when executing the computer program.
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Application publication date: 20191210 |