CN110542849B - Full MOS voltage and temperature monitoring method and circuit - Google Patents
Full MOS voltage and temperature monitoring method and circuit Download PDFInfo
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Abstract
The invention provides a full MOS voltage and temperature monitoring method and a monitoring circuit, which comprise two ring oscillators RO1 and RO2, two time/digital converters TDC1 and TDC2, a temperature mapping module, a voltage mapping module, a reference clock frequency divider module and two compensation modules. Wherein the reference clock is provided by a crystal oscillator, the ring oscillator RO1 is powered by the CORE domain supply voltage VDD _ CORE, and the ring oscillator RO2 is powered by the battery voltage VBAT. The reference clock is respectively connected to the TDC1 and the TDC2 after passing through the frequency divider, and the output ends of the TDC1 and the TDC2 are respectively connected to the temperature mapping module and the voltage mapping module. The invention can realize real full MOS, does not need to increase extra mask, effectively calibrates PVT and improves the monitoring precision; the invention also has the advantages of simple structure, small area and no static power consumption.
Description
Technical Field
The invention relates to the field of chip design, in particular to a method and a circuit for monitoring full MOS voltage and temperature in a chip.
Background
In integrated circuits, monitoring of the supply voltage and temperature of the chip is particularly important. On one hand, due to the limitation of process withstand voltage, the working life of the chip can be reduced by an excessively high power supply voltage, and even the chip device can be permanently damaged; on the other hand, too low a supply voltage may affect the functionality of the chip, resulting in erroneous operation of the system. In addition, due to the sensitivity of semiconductor devices to temperature, the normal operation of the chip may be affected when the temperature is outside a certain range. Therefore, it is necessary to monitor the temperature of the chip and perform the necessary temperature compensation on the chip as required to ensure that the chip has a sufficiently wide temperature operating range.
In the conventional technology, a chip converts a power supply voltage or an output voltage of a temperature sensor (off-chip or on-chip) into a corresponding digital signal by integrating an auxiliary ADC (analog-to-digital converter), so as to monitor the power supply and the temperature of the chip. This scheme requires a large number of analog devices, such as operational amplifiers, comparators, etc., resulting in large power consumption and chip area. With the continuous evolution of the CMOS technology, the power supply voltage of the chip is continuously reduced, and the limitation of the analog implementation method is increasingly obvious.
In recent years, Analog-Time-Digital (ATD) conversion techniques with better Digital process compatibility have become more popular. The ATD Conversion process may be divided into two stages, namely, Analog-to-Time Conversion (ATC) and Time-to-Digital (TDC), in which an Analog voltage signal is converted into a clock domain signal, and then the clock domain signal is digitally quantized to obtain a Digital signal corresponding to the Analog voltage signal.
The scheme of the traditional ADC is not only high in cost and large in power consumption, but also not suitable for realizing a digital process. The existing monitoring method based on the ATC technology well solves the defects of the traditional simulation scheme, but has various defects. These deficiencies are concentrated on the contradiction between "fully compatible digital processes" and "compensation of PVT (Process, Voltage, Temperature: Process, Voltage and Temperature, PVT for short)" such as:
an ADC proposed in a paper published in "integrated circuits in china" 2009,18(3) "full digital ADC design and simulation [ J ]" (author: sandinon, livinstone) adopts analog passive components such as resistors, capacitors and the like to form a ring oscillator, and can be realized only by adding an additional mask in a digital process, so that real full digital realization cannot be realized, and the influence of temperature drift and process variation is not considered, so that the practicability is not strong.
In chinese patent application publication No. CN105071801A, a transistor and an external precision resistor are used to generate a PTAT (proportional to absolute temperature) current for compensating PVT variations. The cost is high, and the method is not suitable for realizing the digital process.
In the chinese patent application publication No. CN101751062A, the temperature drift of the ring oscillator is compensated by using the low-noise reference voltage generating circuit and the linear regulator, but the circuit has a complicated structure, uses a trimming resistor, and has a complicated manufacturing process and high cost.
In chinese patent application publication No. CN103684354A, two inverters with positive and negative temperature coefficients are used to form a ring oscillator, which solves the problem of temperature drift, but does not consider the dispersion caused by the process, and thus the practicability is poor.
As can be seen from the above examples, the design implemented in the all-digital process often lacks the overall compensation for PVT, resulting in poor practicability; however, the design of PVT compensation is considered, and additional analog devices are mostly adopted, so that the digital signals cannot be truly realized.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a full MOS voltage and temperature monitoring method and a monitoring circuit. The specific scheme is as follows:
full MOS voltage and temperature monitoring circuit is applied to digital chip, its characterized in that: the device comprises a reference clock frequency divider, a first ring oscillator, a second ring oscillator, a first time/digital converter, a second time/digital converter, a temperature mapping module and a voltage mapping module;
the input end of the first ring oscillator is connected with the core domain voltage of the digital chip, and the output end of the first ring oscillator is connected with the first input end of the first time/digital converter; the input end of the second ring oscillator is connected with the power supply voltage of the digital chip, and the output end of the second ring oscillator is connected with the first input end of the second time/digital converter;
the input end of the reference clock frequency divider is connected with a reference clock signal and respectively outputs the reference clock signal to the second input end of the first time/digital converter and the second input end of the second time/digital converter after frequency division;
the output end of the first time/digital converter is connected with the temperature mapping module; the output end of the second time/digital converter is connected with the voltage mapping module.
Preferably, the full MOS voltage and temperature monitoring circuit further includes a first compensation module and a second compensation module, wherein the first compensation module is connected between the first time/digital converter and the temperature mapping module, and is configured to compensate a digital value output by the first time/digital converter; the second compensation module is connected between the second time/digital converter and the voltage mapping module and is used for compensating the digital value output by the second time/digital converter.
Preferably, the first compensation module and the second compensation module are linear compensation modules or nonlinear compensation modules.
Preferably, the first ring oscillator and the second ring oscillator are digital circuits composed of inverters or schmitt triggers.
Preferably, the first ring oscillator and the second ring oscillator are both composed of N inverters, and N is an odd number greater than or equal to 3; the output ends and the input ends of the N inverters are connected end to end, and the output end of the last inverter is connected with the input end of the first inverter; the power ends of the N phase inverters are connected with each other to serve as the input end of the ring oscillator, and the output end of the Nth phase inverter serves as the output end of the ring oscillator.
Preferably, the first ring oscillator and the second ring oscillator are the same ring oscillator or different ring oscillators.
The full MOS voltage and temperature monitoring method comprises the following steps:
step 1: under the condition that the input voltage is VBAT1 and the temperature is T1, output pulses of the first ring oscillator and the second ring oscillator are counted in K reference clock cycles respectively, and a count value X1(1) and a count value X2(1) under the condition are obtained respectively; k is an integer greater than or equal to 1;
step 2: under the conditions that the input voltage is VBAT2 and the temperature is T2, output pulses of the first ring oscillator and the second ring oscillator are counted in K reference clock cycles respectively, and a count value X1(2) and a count value X2(2) are obtained;
and step 3: calculating the difference between X1(2) and X1 (1): x1(2) -X1(1) ═ TC (T2-T1), where TC is the temperature coefficient; t2 ═ T1+ [ X1(2) -X1(1) ]/TC can be deduced, so that the average temperature T2 of the chip in the period of time can be obtained by mapping the difference of the count values through the temperature mapping module;
and 4, step 4: the difference between X2(2) and X2(1) was determined:
x2(2) -X2(1) ═ Kvco (VBAT2-VBAT1) + TC (T2-T1), where Kvco is the voltage coefficient;
substituting the (T2-T1) obtained in the step 3 to obtain
X2(2)-X2(1)＝Kvco*(VBAT2-VBAT1)+[X1(2)-X1(1)]；
The size of VBAT2 thus obtained is
VBAT2＝VBAT1+{[X2(2)-X2(1)]-[X1(2)-X1(1)]}/Kvco。
Preferably, the step 3 of mapping the difference between the count values by the temperature mapping module is obtained by a lookup table or an operation.
Preferably, in the linear compensation, in the step 3, the temperature coefficient TC is multiplied by a coefficient a to compensate the temperature coefficient variation caused by the process deviation; in said step 4, the variation of the voltage coefficient is compensated by multiplying the voltage coefficient Kvco by a corresponding coefficient B, a and B being values larger than 0. During nonlinear compensation, scanning the digital chip at full temperature and full voltage, testing corresponding count values at different temperatures and voltages, fitting an expression of actual data, and then performing nonlinear compensation on the expression to obtain a linear expression.
Preferably, the reference clock period K can be changed by changing the division ratio of the basic clock divider, thereby compensating for variations in process variations.
The invention has the beneficial effects that:
1. the invention can realize real full MOS, and does not need to add extra mask in the standard digital CMOS process;
2. the invention effectively calibrates PVT, and improves the monitoring precision;
3. the invention effectively calibrates the nonlinearity of the ring oscillator, and improves the monitoring range and precision; 4. the invention also has the advantages of simple structure, small area and no static power consumption.
Drawings
FIG. 1 is a schematic diagram of two large power supply areas in an integrated digital circuit;
FIG. 2 is a block diagram of an all-MOS voltage and temperature monitoring circuit according to a first embodiment of the present invention;
FIG. 3 is a block diagram of an all-MOS voltage and temperature monitoring circuit according to a second embodiment of the present invention;
FIG. 4 is a circuit schematic of a ring oscillator of the present invention;
FIG. 5 is a flow chart of a method for monitoring supply voltage and temperature in accordance with the present invention;
FIG. 6 is a schematic diagram of the temperature coefficient linear compensation of the present invention;
FIG. 7 is a schematic diagram of voltage coefficient linearity compensation according to the present invention;
FIG. 8 is a schematic diagram of a non-linearity compensation module according to the present invention.
Detailed Description
The present invention will be further explained with reference to the drawings and the embodiments, it should be understood that the embodiments described herein are only for explaining and explaining the present invention and are not to be construed as limiting the present invention.
In a digital integrated circuit, the power domain division can be generally divided into two major areas, i.e., an input/output (IO) power domain and a core (core) power domain. The IO domain is an interface between the digital chip and other chips, and usually has a higher supply voltage or is directly powered by a battery, which is called VBAT. To reduce overall power consumption and increase operating speed, the CORE domain is usually powered by a lower voltage, referred to as VDD _ CORE. As shown in fig. 1, the supply voltage of the CORE domain is VBAT, and a relatively low supply voltage is generated by the BUCK converter or the LDO module, and both the BUCK converter and the LDO use a bandgap reference voltage as a reference, and a stable output voltage is obtained by closed loop negative feedback, so VDD _ CORE has very good temperature insensitivity and Power Supply Rejection Ratio (PSRR), which is usually about 60dB, that is, when the supply voltage changes by 1V, the supply voltage change in the CORE domain is only 1 mV.
First embodiment
Based on the above power supply system, the schematic diagram of the present invention is shown in fig. 2, and includes two ring oscillators RO1 and RO2, two time/digital converters TDC1 and TDC2, a temperature mapping module, a voltage mapping module, and a reference clock divider module. Where the reference clock may be a system reference clock provided by a crystal oscillator, the ring oscillator RO1 is powered by the CORE domain supply voltage VDD _ CORE, and the ring oscillator RO2 is powered by the battery voltage VBAT. The reference clock is respectively connected to the TDC1 and the TDC2 after passing through the reference clock frequency divider, and the output ends of the TDC1 and the TDC2 are respectively connected to the temperature mapping module and the voltage mapping module.
Due to the carrier mobility mu of the MOS tubenSaturated drain-source voltage VdsatAnd a threshold voltage VthThe parameters vary with Process (Process), Voltage (Voltage) and Temperature (Temperature) (PVT variation for short), and therefore the frequency of the ring oscillator varies with PVT variation. For a finished chip, the process variation parameters are already determined, so that only two influencing factors, namely voltage and temperature, are involved. Thus, the oscillation frequency of the ring oscillator can be written as:
f＝f0+Kvco*Vc+TC*T
where f0 is the initial oscillation frequency of the ring oscillator, i.e. the oscillation frequency at temperature T0 and voltage V0, Kvco and Vc are the voltage coefficient and control voltage of the ring oscillator, respectively, and TC and T are the temperature coefficient and temperature, respectively.
As described above, since the supply voltage VDD _ CORE of RO1 varies little with VBAT, the oscillation frequency of RO1 can be approximated as being temperature dependent only, i.e.:
fro1＝f01+Kvco1*0+TC1*T＝f01+TC1*T
fro1 the corresponding digital value X1 after the time/digital converter can reflect the chip temperature value, i.e. the chip temperature value
X1＝f(T) (1)
It can be seen that X1 is a function of temperature T.
For RO2, since its supply voltage (i.e., measured voltage) VBAT is varied, its oscillation frequency is affected not only by temperature but also by VBAT. The oscillation frequency of RO2 can be written as:
fro2＝f02+Kvco2*VBAT+TC2*T
therefore, after fro2 passes through the TDC2 of the time/digital converter, the corresponding digital value X2 reflects both the voltage value of VBAT and the chip temperature value, i.e. the chip temperature value
X2＝f(VBAT，T) (2)
It can be seen that X2 is a function of both temperature T and VBAT.
Since the relational expression between X2 and VBAT can be obtained by obtaining T from expression (1) and substituting it into expression (2) to eliminate T in expression (2), the VBAT voltage value corresponding to this time can be obtained.
The temperature mapping module and the voltage mapping module are used to map the digital values of X1 and X2 to actual temperature and voltage values.
To be compatible with digital processes, the ring oscillator of the present invention is made up of inverters or schmitt triggers or other forms of digital circuitry. In this embodiment, a ring oscillator formed by inverters, such as the one shown in fig. 3 and including N (N is an odd number of > -3) inverters, is selected as an example, and the oscillation frequency can be expressed as:
for the sake of analysis convenience, assuming that RO1 and RO2 are two identical ring oscillators, they have equal initial oscillation frequency (i.e., f01 ═ f02 ═ f0), equal temperature coefficient (i.e., TC1 ═ TC2 ═ TC), and equal voltage coefficient (i.e., Kvco1 ═ Kvco2 ═ Kvco), assuming that the frequency of the reference clock is fref, the count value obtained for the output pulse of RO1 in the period of K reference clocks (K is an integer greater than or equal to 1) is:
X1＝K*fro1/fref＝K*(f0+TC*T)/fref，
the count value of RO2 is X2 ═ K ═ (f0+ Kvco ═ VBAT + TC ×/fref,
X2-X1＝K*(Kvco1*VBAT)/fref，
so that the corresponding VBAT voltage value at this time can be obtained.
The ring oscillator is only used for illustrating the function of the ring oscillator in the present invention, the ring oscillator of the present invention is not limited to be composed of inverters, and ring oscillators composed of other components are also within the protection scope of the present invention.
The specific temperature and power supply voltage monitoring method comprises the following steps:
step 1: under the set known conditions (VBAT1 and T1), counting the output pulses of the RO1 and the RO2 in the period of K reference clocks by a counter respectively to obtain count values X1(1) and X2(1) under the conditions; k is an integer greater than or equal to 1;
step 2: under condition 2(VBAT2 and T2), the output pulses of RO1 and RO2 are counted by the counter 1 and the counter 2 in K reference clock cycles, respectively, to obtain count values X1(2) and X2 (2).
And step 3: calculating the difference between X1(2) and X1 (1): since X1(2) -X1(1) ═ TC (T2-T1), T2 ═ T1+ [ X1(2) -X1(1) ]/TC can be inferred, the average temperature T2 of the chip in this period can be obtained by mapping the difference between the count values.
And 4, step 4: the difference between X2(2) and X2(1) was determined:
X2(2)-X2(1)＝Kvco*(VBAT2-VBAT1)+TC*(T2-T1)
substituting the (T2-T1) obtained in the step 3 to obtain
X2(2)-X2(1)＝Kvco*(VBAT2-VBAT1)+[X1(2)-X1(1)]
The size of VBAT2 thus obtained is
VBAT2＝VBAT1+{[X2(2)-X2(1)]-[X1(2)-X1(1)]}/Kvco。
Second embodiment
The first embodiment is described based on the condition that the process parameters of chip production do not deviate, and if the process parameters deviate, the compensation module is required to compensate the temperature and the voltage. Therefore, the second embodiment of the present invention adds the temperature compensation module 1 and the voltage compensation module 2, and the compensation module 1 and the compensation module 2 are respectively used to compensate the digital values X1 and X2 corresponding to the temperature and the voltage, so as to obtain accurate temperature and voltage values. Another embodiment of the present invention is shown in fig. 3. In addition, the compensation module also has a function of compensating temperature nonlinearity and voltage nonlinearity.
Calibration for process bias: since process variations cause variations in f0, Kvco, and TC, the count value obtained by counting varies. As in step 3 of the first embodiment, a temperature compensation module may be added to compensate for the change in temperature coefficient caused by process variation by multiplying TC by a coefficient a to obtain TC a, as shown in fig. 6; similarly, in step 4, a voltage compensation module may be added, and Kvco may be multiplied by a corresponding coefficient B to compensate for the change of Kvco, as shown in fig. 7. A and B are numbers greater than 0.
Other parts of this embodiment are the same as those of the first embodiment, and are not described herein again.
In the embodiment, for the convenience of analysis, it is assumed that the ring oscillators 1 and 2 are the same oscillator, but in practical application, different ring oscillators may be used to achieve the same effect when a more complicated compensation method is used to compensate the process deviation.
Third embodiment
In the second embodiment, in order to compensate for the variation of the process deviation, we multiply the difference of the count values by a compensation factor. As can be seen from the equation, another compensation method is to change the counting period K to obtain the same effect. By changing the division ratio of the programmable divider, the number of counted periods K can be changed to compensate for variations in process variations.
Fourth embodiment
In the specific temperature and power supply voltage monitoring method of the above embodiment, the difference between the count values is mapped and obtained by a table lookup method or other operations.
Fifth embodiment
In the above embodiments, the compensation module is linearly compensated. For the nonlinearity of the ring oscillator, the invention tests the corresponding count value X under different temperatures and voltages by scanning the full temperature and the full voltage of the digital chip, and fits a polynomial expression of actual data: a is1*Xn+a2*Xn-1+......+an*X+(an+1) Then, non-linear compensation is carried out on the Y formula to obtain a linear expression Y ═ an*X+an+1. As shown in fig. 8. The above is only one way of non-linear compensation, and other ways of non-linear compensation may be used in the present invention.
The above description is for the purpose of illustrating embodiments of the invention and is not intended to limit the invention, and it will be understood by those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (9)
1. Full MOS voltage and temperature monitoring circuit is applied to digital chip, its characterized in that: the device comprises a reference clock frequency divider, a first ring oscillator, a second ring oscillator, a first time/digital converter, a second time/digital converter, a temperature mapping module and a voltage mapping module;
the input end of the first ring oscillator is connected with the core domain voltage of the digital chip, and the output end of the first ring oscillator is connected with the first input end of the first time/digital converter; the input end of the second ring oscillator is connected with the power supply voltage of the digital chip, and the output end of the second ring oscillator is connected with the first input end of the second time/digital converter;
the input end of the reference clock frequency divider is connected with a reference clock signal and respectively outputs the reference clock signal to the second input end of the first time/digital converter and the second input end of the second time/digital converter after frequency division;
the output end of the first time/digital converter is connected with the temperature mapping module; the output end of the second time/digital converter is connected with the voltage mapping module;
the full-MOS voltage and temperature monitoring circuit further comprises a first compensation module and a second compensation module, wherein the first compensation module is connected between the first time/digital converter and the temperature mapping module and is used for compensating a digital value output by the first time/digital converter; the second compensation module is connected between the second time/digital converter and the voltage mapping module and is used for compensating the digital value output by the second time/digital converter.
2. The all-MOS voltage and temperature monitoring circuit of claim 1, wherein: the first compensation module and the second compensation module are linear compensation modules or nonlinear compensation modules.
3. The all-MOS voltage and temperature monitoring circuit of any of claims 1-2, wherein: the first ring oscillator and the second ring oscillator are digital circuits composed of inverters or Schmitt triggers.
4. The all-MOS voltage and temperature monitoring circuit of claim 3, wherein: the first ring oscillator and the second ring oscillator are composed of N inverters, and N is an odd number which is more than or equal to 3; the output ends and the input ends of the N inverters are connected end to end, and the output end of the last inverter is connected with the input end of the first inverter; the power ends of the N phase inverters are connected with each other to serve as the input end of the ring oscillator, and the output end of the Nth phase inverter serves as the output end of the ring oscillator.
5. The all-MOS voltage and temperature monitoring circuit of claim 3, wherein: the first ring oscillator and the second ring oscillator are the same ring oscillator or different ring oscillators.
6. An all-MOS voltage and temperature monitoring method implemented by the monitoring circuit of any one of claims 1 to 5, comprising the steps of:
step 1: under the condition that the input voltage is VBAT1 and the temperature is T1, output pulses of the first ring oscillator and the second ring oscillator are counted in K reference clock cycles respectively, and a count value X1(1) and a count value X2(1) under the condition are obtained respectively; k is an integer greater than or equal to 1;
step 2: under the conditions that the input voltage is VBAT2 and the temperature is T2, output pulses of the first ring oscillator and the second ring oscillator are counted in K reference clock cycles respectively, and a count value X1(2) and a count value X2(2) are obtained;
and step 3: calculating the difference between X1(2) and X1 (1): x1(2) -X1(1) ═ TC (T2-T1), where TC is the temperature coefficient; t2 ═ T1+ [ X1(2) -X1(1) ]/TC can be deduced, so that the average temperature T2 of the chip in the period of time can be obtained by mapping the difference of the count values through the temperature mapping module;
and 4, step 4: the difference between X2(2) and X2(1) was determined:
x2(2) -X2(1) ═ Kvco (VBAT2-VBAT1) + TC (T2-T1), where Kvco is the voltage coefficient;
substituting the (T2-T1) obtained in step 3 to obtain:
X2(2)-X2(1)＝Kvco*(VBAT2-VBAT1)+[X1(2)-X1(1)]；
the size of VBAT2 thus obtained is
VBAT2＝VBAT1+{[X2(2)-X2(1)]-[X1(2)-X1(1)]}/Kvco。
7. The all-MOS voltage and temperature monitoring method of claim 6, wherein: in the step 3, the difference between the count values is mapped by the temperature mapping module, and can be obtained by a lookup table or an operation mode.
8. The all-MOS voltage and temperature monitoring method of claim 7, wherein: in the linear compensation, in the step 3, the temperature coefficient TC is multiplied by a coefficient A to compensate the temperature coefficient variation caused by the process deviation; in step 4, the voltage coefficient Kvco is multiplied by a corresponding coefficient B to compensate for the variation of the voltage coefficient, a and B being values greater than 0;
during nonlinear compensation, scanning the digital chip at full temperature and full voltage, testing corresponding count values at different temperatures and voltages, fitting an expression of actual data, and then performing nonlinear compensation on the expression to obtain a linear expression.
9. The all-MOS voltage and temperature monitoring method of claim 8, wherein: by changing the division ratio of the basic clock divider, the reference clock period K can be changed to compensate for variations in process variations.
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| US7742887B2 (en) * | 2003-11-24 | 2010-06-22 | Qualcomm Incorporated | Identifying process and temperature of silicon chips |
| US8154353B2 (en) * | 2009-11-03 | 2012-04-10 | Arm Limited | Operating parameter monitor for an integrated circuit |
| CN104184469A (en) * | 2014-08-25 | 2014-12-03 | 长沙瑞达星微电子有限公司 | Ring oscillator with low power consumption and low temperature coefficient |
| US9325323B2 (en) * | 2014-08-30 | 2016-04-26 | Stmicroelectronics International N.V. | CMOS oscillator having stable frequency with process, temperature, and voltage variation |
| JP6415285B2 (en) * | 2014-12-08 | 2018-10-31 | セイコーＮｐｃ株式会社 | Temperature voltage sensor |
| CN105823971B (en) * | 2015-01-09 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | Chip operating state monitoring system and monitoring method |
| US10527503B2 (en) * | 2016-01-08 | 2020-01-07 | Apple Inc. | Reference circuit for metrology system |
| CN105811926B (en) * | 2016-04-06 | 2019-02-05 | 江苏星宇芯联电子科技有限公司 | A kind of ring oscillator circuit of included temperature and process corner calibration |
| CN205566248U (en) * | 2016-04-06 | 2016-09-07 | 江苏星宇芯联电子科技有限公司 | From ring oscillator circuit of taking calibration of temperature and technology angle |
| US10288496B1 (en) * | 2016-08-15 | 2019-05-14 | Xilinx, Inc. | Ring oscillator for temperature or voltage sensing |
| CN106209025B (en) * | 2016-08-26 | 2023-05-23 | 哈尔滨工业大学（威海） | Ring oscillator with process and temperature compensation |
| US10458857B2 (en) * | 2018-02-22 | 2019-10-29 | Advanced Micro Devices, Inc. | Accurate on-chip temperature sensing using thermal oscillator |
| CN108489625B (en) * | 2018-03-21 | 2019-10-11 | 西安交通大学 | A kind of fully integrated nearly zero-power temperature sensor of CMOS |
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