CN110536090A - A kind of HDMI Source test equipment and method based on FPGA - Google Patents
A kind of HDMI Source test equipment and method based on FPGA Download PDFInfo
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- CN110536090A CN110536090A CN201910809591.XA CN201910809591A CN110536090A CN 110536090 A CN110536090 A CN 110536090A CN 201910809591 A CN201910809591 A CN 201910809591A CN 110536090 A CN110536090 A CN 110536090A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
Abstract
The present invention provides a kind of HDMI Source test equipment and method based on FPGA, is directly correspondingly connected with FPGA and HDMI Source by pin；The FPGA directly receives the signal from HDMI Source, and vision signal and audio signal are parsed according to HDMI agreement, and obtains test result it is judged that whether HDMI signal is correct according to time sequence parameter sum number predetermined.The present invention eliminates HDMI conversion chip, directly with FPGA according to HDMI agreement come analytic signal, it more directly can test and observe in this way HDMI signal, therefrom find the problem, and configuration register is not needed, it only needs to set time sequence parameter predetermined and data, FPGA can judge always whether HDMI signal is correct.
Description
Technical field
The present invention relates to the test equipment and method of a kind of digitized video/audio interface, in particular to digitized video/
The test equipment and method of high-definition multimedia interface in audio interface.
Background technique
HDMI is the abbreviation of (High Definition Multimedia Interface), means the more matchmakers of fine definition
Body interface is a kind of digitized video/audio interface, can simultaneous transmission audio and video frequency signal.
HDMI carries out audio video transmission, TMDS (Transition Minimized using TMDS signal transmission technology
Differential Signaling) differential signal transmission is also referred to as minimized, refer to through logics such as exclusive or and exclusive or non-exclusive
Original signal data is converted into 10 by algorithm, and preceding 8 are obtained after operation for data by original signal, and the 9th indicates operation
Mode, the 10th for corresponding to DC balance, (DC-balanced just refers to and guarantees direct current offset in channel in an encoding process
It is zero, level translation realizes the matching between Different Logic interface), the data after conversion are with the transmission of the difference kind of drive.This calculation
Method reduces the upper punching for being transmitted signal transition process and undershoot, and the data of transmission tend to DC balance, make signal to transmission
The electromagnetic interference of line is reduced, and improves the speed and reliability of signal transmission.
Current SOC (System On Chip) processor nearly all has HDMI as display interface, so at SOC
HDMI interface test before reason device factory just seems particularly significant, because display directly affects user experience.
Existing test mode is by HDMI signal by a conversion chip, and conversion chip exports the audio of I2S interface,
The video data line of 24bit and 4 row field signals, are connected to FPGA (Field- for the audio-video signal after conversion
Programmable Gate Array, i.e. field programmable gate array) judge audio, video data whether with it is preset consistent, such as
Fruit is consistent, and specification interface is normal, inconsistent, then specification interface is abnormal.
Such test method not only needs conversion chip, but also needs configuration register, low efficiency, and prolongs
The testing time is grown.For test equipment, the introducing of conversion chip is also possible to bring new problem, this unfavorable problem
Analysis.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of HDMI Source test equipment based on FPGA and side
Method directly receives the signal from HDMI Source using FPGA, eliminates HDMI conversion chip, in this way can more directly
Test and observation HDMI signal, therefrom find the problem.
On the one hand, test equipment of the present invention is achieved in that a kind of HDMI Source test equipment based on FPGA,
It including FPGA but does not include HDMI conversion chip, and the FPGA and HDMI Source is correspondingly connected with by pin；
The FPGA directly receives the signal from HDMI Source, parses vision signal and sound according to HDMI agreement
Frequency signal, and test result is obtained it is judged that whether HDMI signal is correct according to time sequence parameter sum number predetermined.
Further, the FPGA includes CEC test module, string turns and module, TMDS decoder module, phase alignment mould
Block, audio-video separation module, video measurement module and audio-frequency test module；
The CEC test module is correspondingly connected with the HDMI Source by pin hdmi_cec, pre- by receiving a string
Whether the data defined are correct come the hdmi_cec signal for judging the HDMI Source；
The string turns and module, the TMDS decoder module, the phase alignment module, the audio-video separation module
It is sequentially connected, and the phase alignment module is also connected with the string and turns simultaneously module, the string turns and module passes through pin respectively
Hdmi_clk_p, hdmi_clk_n, hdmi_data_p and hdmi_data_n are correspondingly connected with the HDMI Source, the sound
Video separation module is separately connected the video measurement module and the audio-frequency test module；
The string turns and module uses the clock of HDMI source as reference clock source, and the signal of 1bit is converted into
10bit signal, and adjust the sequence and delay of 10bit signal；
The TMDS decoder module lists all TMDS characters, is just solved if it is effective TMDS character
Code, notes that the phase alignment module is adjusted if it is idle character；
The phase alignment module is by judging whether effective TMDS character, and to adjust, the string turns and the signal of module is arranged
Sequence and delay to search out effective TMDS character, and are decided；
The audio-video separation module isolates audio signal according to the Data Island period, and according to video cycle point
Separate out vision signal；
The audio-frequency test module handles audio signal again, obtains the parameter and audio data of restored audio clock
Stream, by parameter compared with predefined audio data, obtains the test result values of audio data；
The video measurement module counts the row field signal recovered, while receiving effective video data, and two
Person compared with data, obtains the test result values of video data with predefined timing.
Further, the FPGA further includes EDID module, and the EDID module passes through pin hdmi_scl and hdmi_
Sda is correspondingly connected with the HDMI Source；And the EDID module has 256 to be used to select the resolution ratio to be exported
Determine the byte of data.
Further, the FPGA further includes HPD module, and the HPD module is correspondingly connected with institute by pin hdmi_hpd
HDMI Source is stated, when the HDMI test inside the FPGA is enabled, the HPD module can draw high hdmi_hpd signal
Level, to prompt HDMI Source to recognize external equipment access.
On the other hand, test method of the present invention is achieved in that a kind of test side HDMI Source based on FPGA
Method does not use HDMI conversion chip, but FPGA and HDMI Source is correspondingly connected with by pin；It is straight by the FPGA
The signal from HDMI Source is received, vision signal and audio signal are parsed according to HDMI agreement, and according to fixed in advance
The time sequence parameter sum number of justice obtains test result it is judged that whether HDMI signal is correct.
Further, the test process of the FPGA is:
In a first aspect, receiving a string of data predefined by a CEC test module to judge the HDMI Source
Hdmi_cec signal it is whether correct；
Second aspect, by a string turns and module uses the clock of HDMI source as reference clock source, by 1bit's
Signal is converted into 10bit signal, and adjusts the sequence and delay of 10bit signal；
As soon as listing all TMDS characters by TMDS decoder module, solved if it is effective TMDS character
Code, notes that a phase alignment module is adjusted if it is idle character；
The phase alignment module is by judging whether effective TMDS character, and to adjust, the string turns and the signal of module is arranged
Sequence and delay to search out effective TMDS character, and are decided；
Then audio signal is isolated according to the Data Island period by an audio-video separation module and gives audio survey
Die trial block, and vision signal is isolated according to video cycle and gives a video measurement module；
The audio-frequency test module handles audio signal again, obtains the parameter and audio data of restored audio clock
Stream, by parameter compared with predefined audio data, obtains the test result values of audio data；
The video measurement module counts the row field signal recovered, while receiving effective video data, and two
Person compared with data, obtains the test result values of video data with predefined timing.
Further, in the test process of the FPGA, also realize that selection HDMI Source is wanted by an EDID module
The resolution ratio of output.
Further, in the test process of the FPGA, when the HDMI test inside the FPGA is enabled, pass through one
HPD module can draw high the level of hdmi_hpd signal, to prompt HDMI Source to recognize external equipment access.
The present invention has the advantage that the present invention directly receives the signal from HDMI Source using FPGA, eliminate
HDMI conversion chip, with FPGA according to HDMI agreement come analytic signal, more directly can test and observe in this way HDMI letter
Number, it therefrom finds the problem, and do not need configuration register, it is only necessary to which time sequence parameter predetermined and data are arranged
Good, FPGA can judge always whether HDMI signal is correct.The present invention directly receives HDMI signal, keeps hardware design simpler
Single, software setting is simple, has saved the testing time.In addition, function of the FPGA with a similar logic analyser, can grab
All signals inside FPGA are wanted observation signal using adding, can be directly displayed on graphical interfaces, are conducive to analysis and ask
Topic.
Detailed description of the invention
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the overall structure connection schematic diagram of test equipment of the present invention.
Fig. 2 is the specific structure connection schematic diagram of test equipment of the present invention.
Specific embodiment
Embodiment one
For the embodiment of the HDMI Source test equipment of the invention based on FPGA, refering to Figure 1, it includes
FPGA but do not include HDMI conversion chip, and the FPGA and HDMI Source is correspondingly connected with by pin；
The FPGA directly receives the signal from HDMI Source, parses vision signal and sound according to HDMI agreement
Frequency signal, and test result is obtained it is judged that whether HDMI signal is correct according to time sequence parameter sum number predetermined.
Again as shown in Fig. 2, the FPGA further comprise CEC test module, string turn and module, TMDS decoder module,
Phase alignment module, audio-video separation module, video measurement module and audio-frequency test module；It further include EDID module and HPD mould
Block.Wherein, the CEC test module is correspondingly connected with the HDMI Source by pin hdmi_cec；The string turns and mould
Block, the TMDS decoder module, the phase alignment module, the audio-video separation module are sequentially connected, and the phase
Alignment module be also connected with it is described string turn and module, it is described string turn and module pass through respectively pin hdmi_clk_p, hdmi_clk_n,
Hdmi_data_p and hdmi_data_n is correspondingly connected with the HDMI Source, and the audio-video separation module is separately connected institute
State video measurement module and the audio-frequency test module；The EDID module connects by the way that pin hdmi_scl and hdmi_sda are corresponding
Meet the HDMI Source；The HPD module is correspondingly connected with the HDMI Source by pin hdmi_hpd.
It is specific:
The CEC test module is an independent test module, is judged by receiving a string of data predefined
Whether the hdmi_cec signal of the HDMI Source is correct；
The string turns and module uses the clock of HDMI source as reference clock source, and the signal of 1bit is converted into
10bit signal, and adjust the sequence and delay of 10bit signal；
The TMDS decoder module lists all TMDS characters, is just solved if it is effective TMDS character
Code, notes that the phase alignment module is adjusted if it is idle character；TMDS character is according to inside HDMI agreement
Rule calculates, and the character of DMI is 10bit, then just have 1024 kinds of characters, wherein effective character may account for 50%, if
The 10bit character received is not inside effective character, then being exactly idle character；
The phase alignment module is by judging whether effective TMDS character, and to adjust, the string turns and the signal of module is arranged
Sequence and delay to search out effective TMDS character, and are decided；Next circulation of the sequence 10 of signal, if select
It is the A7 Series FPGA of xilinx, then delay value 0-31 mono- circulation, 10 signals of every sequence, delay value add 1, in this way
Mechanism searches out effective TMDS character, and decides；
According to the Data Island period, (HDMI agreement defines HDMI signal and is divided into the audio-video separation module
Control period, data island and tri- kinds of video period) audio signal is isolated, and according to video cycle point
Separate out vision signal (vision signal belongs to row field signal)；
The audio-frequency test module handles audio signal again, obtains the parameter and audio data of restored audio clock
Stream, by parameter compared with predefined audio data, obtains the audio data test result values of a 8bit.
The video measurement module counts the row field signal recovered, while receiving effective video data, and two
Person compared with data, obtains one 8 video data test result values with predefined timing.
The EDID module has 256 bytes for having had determined data, HDMI Source can according to these data come
Select the resolution ratio to be exported.
The HPD module, when the HDMI test inside the FPGA is enabled, the HPD module can draw high hdmi_hpd
The level of signal, to prompt HDMI Source to recognize external equipment access.
Embodiment two
As shown in connection with fig. 1, which is the embodiment of the HDMI Source test method the present invention is based on FPGA,
Without using HDMI conversion chip, but FPGA and HDMI Source is correspondingly connected with by pin；It is directly connect by the FPGA
The signal from HDMI Source is received, according to HDMI agreement come analytic signal, and according to time sequence parameter predetermined and data
Judge whether HDMI signal is correct.
Wherein, as shown in connection with fig. 2, the test process of the FPGA is:
When HDMI test inside the FPGA is enabled, the level of hdmi_hpd signal can be drawn high by a HPD module,
To prompt HDMI Source to recognize external equipment access.
Then in a first aspect, receiving a string of data predefined by a CEC test module to judge the HDMI
Whether the hdmi_cec signal of Source is correct；
Second aspect, by a string turns and module uses the clock of HDMI source as reference clock source, by 1bit's
Signal is converted into 10bit signal, and adjusts the sequence and delay of 10bit signal；
As soon as listing all TMDS characters by TMDS decoder module, solved if it is effective TMDS character
Code, notes that a phase alignment module is adjusted if it is idle character；
The phase alignment module is by judging whether effective TMDS character, and to adjust, the string turns and the signal of module is arranged
Sequence and delay to search out effective TMDS character, and are decided；
Then audio signal is isolated according to the Data Island period by an audio-video separation module and gives audio survey
Die trial block, and vision signal is isolated according to video cycle and gives a video measurement module；
The audio-frequency test module handles audio signal again, obtains the parameter and audio data of restored audio clock
Stream, by parameter compared with predefined audio data, obtains the test result values of the audio data of a 8bit；
The video measurement module counts the row field signal recovered, while receiving effective video data, and two
Person compared with data, obtains the test result values of the video data of a 8bit with predefined timing.
In the test process of the FPGA, selection HDMI Source point to be exported also is realized by an EDID module
Resolution.
The present invention directly receives the signal from HDMI Source using FPGA, eliminates HDMI conversion chip, uses FPGA
According to HDMI agreement come analytic signal, HDMI signal more directly can be tested and be observed in this way, is therefrom found the problem,
And configuration register is not needed, it is only necessary to set time sequence parameter predetermined and data, FPGA can sentence always
Whether disconnected HDMI signal is correct.
Although specific embodiments of the present invention have been described above, those familiar with the art should be managed
Solution, we are merely exemplary described specific embodiment, rather than for the restriction to the scope of the present invention, it is familiar with this
The technical staff in field should be covered of the invention according to modification and variation equivalent made by spirit of the invention
In scope of the claimed protection.
Claims (8)
1. a kind of HDMI Source test equipment based on FPGA, it is characterised in that: including FPGA but do not include HDMI conversion core
Piece, and the FPGA and HDMI Source is correspondingly connected with by pin；
The FPGA directly receives the signal from HDMI Source, and vision signal and audio letter are parsed according to HDMI agreement
Number, and test result is obtained it is judged that whether HDMI signal is correct according to time sequence parameter sum number predetermined.
2. a kind of HDMI Source test equipment based on FPGA according to claim 1, it is characterised in that: described
FPGA includes CEC test module, string turns and module, TMDS decoder module, phase alignment module, audio-video separation module, view
Frequency test module and audio-frequency test module；
The CEC test module is correspondingly connected with the HDMI Source by pin hdmi_cec, predefined by receiving a string
Whether good data are correct come the hdmi_cec signal for judging the HDMI Source；
It is described string turn and module, the TMDS decoder module, the phase alignment module, the audio-video separation module successively
Connection, and the phase alignment module is also connected with the string and turns simultaneously module, the string turns and module passes through pin hdmi_ respectively
Clk_p, hdmi_clk_n, hdmi_data_p and hdmi_data_n are correspondingly connected with the HDMI Source, the audio-video point
The video measurement module and the audio-frequency test module are separately connected from module；
The string turns and module uses the clock of HDMI source as reference clock source, and the signal of 1bit is converted into 10bit
Signal, and adjust the sequence and delay of 10bit signal；
The TMDS decoder module lists all TMDS characters, is just decoded if it is effective TMDS character, such as
Fruit is that idle character notes that the phase alignment module is adjusted；
The phase alignment module by judging whether effective TMDS character, come adjust it is described string turn and module signal sequence and
Delay, to search out effective TMDS character, and is decided；
The audio-video separation module isolates audio signal according to the DataIsland period, and isolates view according to video cycle
Frequency signal；
The audio-frequency test module handles audio signal again, obtains the parameter and voice data stream of restored audio clock, will
Parameter obtains the test result values of audio data compared with predefined audio data；
The video measurement module counts the row field signal recovered, while receiving effective video data, the two with
Predefined timing obtains the test result values of video data compared with data.
3. a kind of HDMI Source test equipment based on FPGA according to claim 2, it is characterised in that: described
FPGA further includes EDID module, and the EDID module is correspondingly connected with the HDMI by pin hdmi_scl and hdmi_sda
Source；And the EDID module has 256 bytes for having had determined data for being used to select the resolution ratio to be exported.
4. a kind of HDMI Source test equipment based on FPGA according to claim 2, it is characterised in that: described
FPGA further includes HPD module, and the HPD module is correspondingly connected with the HDMI Source by pin hdmi_hpd, when described
When HDMI test inside FPGA is enabled, the HPD module can draw high the level of hdmi_hpd signal, to prompt HDMI
Source has recognized external equipment access.
5. a kind of HDMI Source test method based on FPGA, it is characterised in that: HDMI conversion chip is not used, but will
FPGA and HDMI Source is correspondingly connected with by pin；The signal from HDMI Source is directly received by the FPGA,
Vision signal and audio signal are parsed according to HDMI agreement, and according to time sequence parameter sum number predetermined it is judged that HDMI believes
It is number whether correct, obtain test result.
6. a kind of HDMI Source test method based on FPGA according to claim 5, it is characterised in that: described
The test process of FPGA is:
In a first aspect, receiving a string of data predefined by a CEC test module to judge the HDMI Source's
Whether hdmi_cec signal is correct；
Second aspect, by a string turns and module uses the clock of HDMI source as reference clock source, by the signal of 1bit
It is converted into 10bit signal, and adjusts the sequence and delay of 10bit signal；
As soon as listing all TMDS characters by TMDS decoder module, it is decoded if it is effective TMDS character,
Note that a phase alignment module is adjusted if it is idle character；
The phase alignment module by judging whether effective TMDS character, come adjust it is described string turn and module signal sequence and
Delay, to search out effective TMDS character, and is decided；
Then audio signal is isolated according to the Data Island period by an audio-video separation module and gives an audio-frequency test mould
Block, and vision signal is isolated according to video cycle and gives a video measurement module；
The audio-frequency test module handles audio signal again, obtains the parameter and voice data stream of restored audio clock, will
Parameter obtains the test result values of audio data compared with predefined audio data；
The video measurement module counts the row field signal recovered, while receiving effective video data, the two with
Predefined timing obtains the test result values of video data compared with data.
7. a kind of HDMI Source test equipment based on FPGA according to claim 6, it is characterised in that: described
In the test process of FPGA, the selection HDMI Source resolution ratio to be exported also is realized by an EDID module.
8. a kind of HDMI Source test equipment based on FPGA according to claim 6, it is characterised in that: described
In the test process of FPGA, when the HDMI test inside the FPGA is enabled, hdmi_hpd letter can be drawn high by a HPD module
Number level, to prompt HDMI Source to recognize external equipment access.
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Application publication date: 20191203 |