CN110534517A

CN110534517A - Integrated circuit memory and forming method thereof, semiconductor device

Info

Publication number: CN110534517A
Application number: CN201810517310.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-05-25
Filing date: 2018-05-25
Publication date: 2019-12-03

Abstract

The present invention provides a kind of integrated circuit memories and forming method thereof, semiconductor device.By placing the peripheral partition wall of setting in the outer of set of bit lines, to which the bit line for being conducive to alleviate in set of bit lines positioned at marginal position leads to the problem of figure deformation, and it can also make corresponding edge position and the corresponding circuit configuration concentration in middle position in set of bit lines close or even identical, so that it is guaranteed that being formed by the pattern uniformity of each bit line of its in set of bit lines.

Description

Integrated circuit memory and forming method thereof, semiconductor device

Technical field

The present invention relates to semiconductor integrated circuit technology field, in particular to a kind of integrated circuit memory and its formation side Method, semiconductor device.

Background technique

Integrated circuit memory usually has memory cell array, includes multiple in the memory cell array in array The storage unit of arrangement.And the integrated circuit memory also has a plurality of wordline and a multiple bit lines, each wordline and each Bit line is electrically connected with corresponding storage unit respectively, to realize the store function of each storage unit.

Fig. 1 is a kind of existing structural schematic diagram of integrated circuit memory, as shown in Figure 1, integrated circuit memory packet It includes:

Multiple active areas 10, multiple active areas 10 are arranged in array, and multiple active areas are used to form multiple Storage unit；

One word line group 20, the word line group 20 include the wordline 21 that a plurality of (X-direction) along a first direction successively arranges, often One wordline 21 extends in second direction (Y-direction) and intersects with the corresponding active area 10；And

One set of bit lines 30, the set of bit lines 30 include a plurality of bit line 31/ successively arranged along second direction (Y-direction) 31 ', each bit line 31 extends in the first direction (x-direction) and intersects with the corresponding active area 10.

When forming integrated circuit memory shown in FIG. 1, preparation process is usual are as follows: firstly, a substrate is provided, and Multiple active areas are defined in the substrate；Then, word line group is formed in the substrate；Then, set of bit lines is formed described On substrate.Wherein, the forming method of the set of bit lines is for example are as follows: deposits a bit line material layer first on substrate；Then, it is formed For one mask layer on the bit line material layer, the mask layer defines the figure of multiple bit lines in set of bit lines；Then, with exposure mask Layer is bit line material layer described in mask etching, to form the set of bit lines.

However, when forming integrated circuit memory as described above, being formed by bit line shown in continuing to refer to figure 1 The bit line 31 ' on marginal position is corresponded in group 30, figure pattern easily deforms, to can cause to the performance of bit line Adverse effect, causes its stability of the integrated circuit memory being ultimately formed poor.

Summary of the invention

The purpose of the present invention is to provide a kind of integrated circuit memories, to solve its position of existing integrated circuit memory Usually there is the problem of figure deformation in the bit line being located on marginal position in line group.

In order to solve the above technical problems, the present invention provides a kind of integrated circuit memory, comprising:

One substrate, with multiple active areas in array arrangement in the substrate；

One word line group is formed in the substrate, and the word line group includes a plurality of word successively arranged along a first direction Line, each wordline extend in a second direction and connect with the corresponding active area；

One set of bit lines is formed over the substrate, and the set of bit lines includes a plurality of position successively arranged along second direction Line, each bit line extend in a first direction and connect with the corresponding active area；And

One peripheral partition wall forms over the substrate and is arranged in the periphery of the set of bit lines, and the peripheral partition wall It is located in same structure layer with the set of bit lines.

Optionally, there is first size of space, the periphery partition wall and immediate bit line between the adjacent bit line Between there is second size of space, the absolute difference of second size of space and first size of space is less than or equal to described The width value of bit line.

Optionally, the bit line partition wall includes the first partition wall portion, and first partition wall portion extends along the first direction, And the bit line of corresponding edge position is set far from the outside at set of bit lines center.

Optionally, the peripheral partition wall further includes the second partition wall portion, and second partition wall portion prolongs along the second direction It stretches, and the set of bit lines is set close to the outside of each bit line end.

Optionally, the end in first partition wall portion and second partition wall portion is connected with each other, so that the periphery constituted Partition wall is configured to ring structure, and is looped around on the outside of the set of bit lines.

Optionally, the width dimensions of the peripheral partition wall are greater than the width dimensions of the bit line.

Optionally, the length dimension of the peripheral partition wall is greater than the length dimension of the bit line.

Optionally, the integrated circuit memory further include: multiple bit line contact pads are formed over the substrate, one Institute's bitline contact pad is connect with the end of a bit line.

Optionally, the bit line extends along direction tool there are two opposite first end and the second end, and adjacent two In bit line described in item, corresponding two bit line contact pads are respectively formed on the first end and the second end of two bit lines.

Optionally, definition has a device region and a peripheral region in the substrate, and the peripheral region is located at the device region Periphery, multiple active areas, the word line group, the set of bit lines and the peripheral partition wall are arranged at the described of the substrate In device region；Wherein, in this second direction, most marginal active area between the boundary of the device region have a bit line Side is left white area, and the bit line side is left white the width dimensions of area in this second direction greater than the width between the adjacent bit line Size is spent, the periphery wall part fills the bit line side and is left white area.

Optionally, the integrated circuit memory further include: multiple peripheral circuits are formed in the periphery of the substrate Qu Zhong, and the peripheral circuit has a gate structure, and the gate structure and institute's bitline contact pad are in same structure layer In.

Another object of the present invention is to provide a kind of forming methods of integrated circuit memory, comprising:

One substrate is provided, there is an active area array in the substrate, the active area array includes multiple in array The active area of arrangement；

Form a word line group in the substrate, the word line group includes that a plurality of (X-direction) along a first direction is successively arranged The wordline of cloth, each wordline extend in a second direction and connect with the corresponding active area；And

Form a set of bit lines and a peripheral partition wall over the substrate, the set of bit lines include it is a plurality of along second direction according to The bit line of secondary arrangement, each bit line extend in a first direction and connect with the corresponding active area, the outer enclosure Wall is formed in the periphery of the set of bit lines and is located in same structure layer with the set of bit lines.

Optionally, the integrated circuit memory further includes multiple formation bit line contact pads over the substrate, and one Institute's bitline contact pad is connect with the end of a bit line.

Optionally, definition has a device region and a peripheral region in the substrate, and the peripheral region is located at the device region Periphery, multiple active areas, the word line group, the set of bit lines and the peripheral partition wall are both formed in the described of the substrate In device region；And in this second direction, most marginal active area between the boundary of the device region have a bit line Side is left white area.

Optionally, it is also formed with multiple peripheral circuits, the periphery electricity over the substrate and in the corresponding peripheral region Road has a gate structure, and the gate structure and institute's bitline contact pad are formed in same processing step.

Optionally, using same conductive material layer formed the set of bit lines, the peripheral partition wall, institute's bitline contact pad and The peripheral circuit, preparation method include:

Form the conductive material layer over the substrate, the conductive material layer covers the device region and the periphery Area；

The first mask layer is formed in the conductive material layer, first mask layer defines multiple peripheral circuit figures Figure is padded with multiple bit line contacts, and first mask layer covers in the conductive material layer and corresponds to the active area array Part, and further extend to cover in the conductive material layer and correspond to the part that the bit line side is left white area；

Using first mask layer as conductive material layer described in mask etching, to form the peripheral circuit and the bit line Engagement pad corresponds to the active area array in the conductive material layer, and in the conductive material layer and the bit line side is stayed The part in white area is retained；

The second mask layer is formed in the conductive material layer, second mask layer defines multiple bit lines figure in institute It states on active area array, and defines peripheral partition wall figure and be left white in area in the bit line side, and second mask layer Cover the peripheral circuit and institute's bitline contact pad；And

Using second mask layer as conductive material layer described in mask etching, to form a plurality of bit line described active On area's array, and forms the peripheral partition wall and be left white in area in the bit line side.

The second mask layer is formed in the conductive material layer, second mask layer defines multiple bit lines figure in institute It states on active area array, and defines peripheral partition wall figure and be left white in area in the bit line side, and second mask layer The part for corresponding to the peripheral region in the conductive material layer is covered, and further extends to cover in the conductive material layer and correspond to The part of active area array side；

Using second mask layer as conductive material layer described in mask etching, to form a plurality of bit line described active On area's array, and forms the peripheral partition wall and be left white in area in the bit line side, and correspond to institute in the conductive material layer The part of the part and corresponding active area array side of stating peripheral region is retained；

The first mask layer is formed in the conductive material layer, first mask layer defines multiple peripheral circuit figures In the peripheral region, and multiple bit line contact pad figures are defined on the side of the active area array, and described First mask layer covers the set of bit lines and the peripheral partition wall；And

Using first mask layer as conductive material layer described in mask etching, to form the peripheral circuit and the bit line Engagement pad.

Another object of the present invention is to provide a kind of semiconductor device, comprising:

One call wire group is formed over the substrate, and the call wire group includes a plurality of successively arranging along second direction Call wire, each call wire extends in a first direction and connects with the corresponding active area；And

One peripheral partition wall, forms over the substrate and is arranged in the periphery of the call wire group, and the outer enclosure Wall and the call wire group are located in same structure layer.

In integrated circuit memory provided by the invention, by the same structure layer of set of bit lines and positioned at set of bit lines Peripheral region in the peripheral partition wall that is arranged, have preferably so as to make to be formed by the bit line in set of bit lines positioned at marginal position Pattern, without etch notch or deformation the defects of.Specifically, in the preparation process of memory provided by the invention In, due to that need to form peripheral partition wall and the periphery of set of bit lines is arranged in, to can avoid being located on marginal position in set of bit lines The problem of bit line is attacked by biggish etching.Also, also intermediate region and corresponding edge region can be corresponded in equalized bitline group Circuit configuration concentration, improve and be formed by pattern uniformity in set of bit lines between each bit line.

Detailed description of the invention

Fig. 1 is a kind of existing schematic diagram of the structure of integrated circuit memory；

Fig. 2 is the structural schematic diagram of the integrated circuit memory in the embodiment of the present invention one；

Fig. 3 is the structural schematic diagram of integrated circuit memory its set of bit lines and word line group in the embodiment of the present invention one；

Fig. 4 is the structural schematic diagram of the integrated circuit memory in the embodiment of the present invention two；

Fig. 5 is the flow diagram of the forming method of the integrated circuit memory in the embodiment of the present invention three；

Fig. 6 a~Figure 10 a is the forming method of the integrated circuit memory in the embodiment of the present invention three in its preparation process Top view；

Fig. 6 b~Figure 10 b is respectively the integrated circuit memory in the embodiment of the present invention three shown in Fig. 6 a~Figure 10 a Forming method is in its preparation process along aa ' and bb ' diagrammatic cross-section in direction；

Figure 11~Figure 13 is in the forming method of integrated circuit memory its preparation process in the embodiment of the present invention four Top view；

Figure 14~Figure 16 is in the forming method of integrated circuit memory its preparation process in the embodiment of the present invention five Top view.

Wherein, appended drawing reference is as follows:

10- active area；

20- word line group；21- wordline；

30- set of bit lines；31- bit line；

The bit line on marginal position is corresponded in 31 '-set of bit lines；

32- bit line contact pad；

100- substrate；

110- active area；120- isolation structure；

200- word line group；

210- wordline；220- separation layer；

300- set of bit lines；

310- bit line；320- bit line contact pad；

The periphery 400- partition wall；

The first partition wall of 410- portion；The second partition wall of 420- portion

500- peripheral circuit；

600- conductive material layer

610- work function adjustment layer；620- conductive material layer；

630- insulation material layer；640- side wall；

650- insulation fill stratum；

710/710 '-the first mask layer；

711/711 '-peripheral circuit figure；712- bit line contact pads figure；

720/720 '-the second mask layer；

721/721 '-bit line figure；The periphery 722- partition wall figure；

722 '-the first partition wall portion figures；723 '-the second partition wall portion figures

AA- device region；The peripheral region BB-；

CC-1- first is left white area；CC-2- second is left white area；

First size of space of D1-；Second size of space of D2-.

Specific embodiment

As stated in the background art, the structure based on existing integrated circuit memory is formed by its set of bit lines of memory In be located at bit line the problem of being easy to appear deformation on marginal position, thus the performance of integrated circuit memory can be caused it is unfavorable It influences.

The present inventor has found after study, and the bit line being located on marginal position in set of bit lines is caused to occur deforming Main reason is that when forming the set of bit lines, since the edge of set of bit lines is left white region there are biggish, so as to cause position It is easier the attack by biggish etching agent in the bit line on marginal position, and then occurs the bit line on marginal position easily The problem of its figure deformation.

Based on this, the present invention provides a kind of integrated circuit memories, including

In integrated circuit memory provided by the invention, since outer place in set of bit lines is provided with peripheral partition wall, and Peripheral partition wall and set of bit lines balance in set of bit lines in same structure layer, therefore when preparing set of bit lines using peripheral partition wall The circuit configuration concentration of corresponding intermediate region and corresponding edge region, makes to be formed by each bit line and is uniformly etched Intensity, to be formed, pattern is close and uniform bit line.

Integrated circuit memory proposed by the present invention and integrated circuit are stored below in conjunction with the drawings and specific embodiments The forming method of device, semiconductor device are described in further detail.According to following explanation, advantages of the present invention and spy Sign will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to side Just, the purpose of the embodiment of the present invention is lucidly aided in illustrating.

Fig. 2 is the structural schematic diagram of the integrated circuit memory in the embodiment of the present invention one, and Fig. 3 is the embodiment of the present invention one In integrated circuit memory its set of bit lines and word line group structural schematic diagram.In conjunction with shown in Fig. 2 and Fig. 3, the integrated circuit Memory includes:

One substrate 100, with multiple active areas 110 in array arrangement, the active area 110 in the substrate 100 For constituting storage unit；

One word line group 200 is formed in the substrate 100, and the word line group 200 includes a plurality of (side X along a first direction To) wordline 210 successively arranged, each wordline 210 extend in second direction (Y-direction) and with it is corresponding described active Area 110 connects；

One set of bit lines 300 is formed on the substrate 100, and the set of bit lines 300 includes a plurality of along the second direction (side Y To) bit line 310 successively arranged, each bit line 310 extend in the first direction (x-direction) and with it is corresponding described active Area 110 connects；

One peripheral partition wall 400 forms over the substrate and is arranged in the periphery of the set of bit lines 300, and described outer Enclosure wall 400 and the set of bit lines 300 are located in same structure layer.

By the way that peripheral partition wall 400 is arranged to surround set of bit lines 300, to avoid being located on marginal position in set of bit lines 300 Bit line 310 be exposed to spacious be left white in region.In this way, especially be made when forming the integrated circuit memory During standby set of bit lines, it can be effectively improved and correspond to the problem of the bit line on marginal position is attacked by biggish etching, And then ensures to be formed by the bit line being located on marginal position in set of bit lines and have biggish pattern.Alternatively, it is also understood that By the way that peripheral partition wall 400 is arranged, to increase the arrangement concentration for corresponding to the bit line on marginal position in set of bit lines 300, make It is located at its circuit configuration concentration of the bit line of marginal position in set of bit lines 300, it can be close to being located at middle area in set of bit lines The circuit configuration concentration of the bit line in domain.Since circuit configuration concentration is uniform, it is equal that subsequent etching can be improved accordingly Even property, so can make to be formed by set of bit lines positioned at the bit line of marginal position and positioned at its pattern of the bit line of intermediate region and It is of uniform size.

Emphasis is refering to what is shown in Fig. 3, have the first size of space D1, the periphery partition wall between the adjacent bit line 310 There is the second size of space D2, second size of space D2 and first interval ruler between 400 and immediate bit line 310 The absolute difference of very little D1 is less than or equal to the width value of the bit line.That is, being located at the bit line on marginal position in the set of bit lines 300 The second size of space D2 between peripheral partition wall 400, the first size of space D1 between adjacent bit lines in the set of bit lines It is close or even equal, so as to keep circuit configuration corresponding to the bit line being located on marginal position in the set of bit lines 300 intensive Degree and in set of bit lines be located at intermediate region on bit line corresponding to circuit configuration concentration it is close or identical, be conducive to for The pattern uniformity between each bit line is further increased when subsequent preparation set of bit lines.

With continued reference to shown in Fig. 2, definition has a device region AA and a peripheral region BB, the periphery in the substrate 100 Area BB is located at the periphery of the device region AA.Wherein, multiple active areas 110, the word line group 200, the set of bit lines 300 It is arranged in the device region AA of the substrate with peripheral partition wall 400.It is to be understood that the device region AA is to be used for Form the region of storage unit.

Further, the active area array being made of multiple active areas 110 can be with the center device region AA weight It closes, and the area of the device region AA is greater than the area of the active area array, to keep the active area array complete It is all contained in the device region AA.That is, the periphery tool in the regional scope of device region AA and positioned at the active area array There is a bit line side to be left white area.

With specific reference to shown in Fig. 2, in the first direction (x-direction), from most marginal active area 110 to the device region AA Boundary between have bit line side be left white area (that is, first is left white area CC-1) it is believed that described first be left white area CC-1 extension On side of the active area array in first direction；And in second direction (Y-direction), from most marginal active area 110 are left white area (that is, second is left white area CC-2) it is believed that described to also having bit line side between the boundary of the device region AA Second, which is left white area CC-2, extends in the active area array on the side in second direction.Wherein, described first it is left white area CC- 1 and described second is left white area CC-2 and all has biggish width dimensions, such as described first is left white area CC-1 in a first direction Width dimensions be greater than the width dimensions between adjacent bit lines and described second be left white the width of area CC-2 in a second direction Size is greater than the width dimensions between adjacent bit lines.

It should be noted that being only to schematically illustrate the structural schematic diagram in part of devices area in Fig. 2, should recognize It arrives, device region can also further extend toward the right direction in face of drawing along the X direction and device region can also be along Y Further extend upwards toward in face of drawing in direction.

In optional scheme, its wordline 210 extends along second direction (Y-direction) in the word line group 200, and can be into one Step extends to the boundary of the device region AA.That is, the wordline 120 is connected with corresponding active area 110, and cross described active Area's array is to further extend in the second white space CC-2 of active area array periphery.And in the set of bit lines 300 Bit line 310 extends and connects with corresponding active area 110 along a first direction (X-direction).As described above, in active area array Periphery have extend in a second direction second be left white area CC-2, be typically left white in area CC-2 and be not present described second Active area, and then bit line will not be additionally set.Based on this, the bit line 310 in the set of bit lines 300 on marginal position is Described second is exposed to be left white in area CC-2.

As stated in the background art and as shown in connection with fig. 1, in traditional integrated circuit memory, set of bit lines 30 it is peripheral not It is provided with peripheral partition wall, so that the 31 one side of bit line being located on marginal position in set of bit lines 30 be made to be directly exposed to spaciousness Be left white in region, and further result in set of bit lines 30 positioned at marginal position bit line corresponding to the intensive journey of circuit configuration Degree has larger difference with circuit configuration concentration corresponding to the bit line in set of bit lines positioned at intermediate region, therefore is making During standby set of bit lines, easily lead to the irregular problem of its figure of bit line being located on marginal position in set of bit lines.

However, peripheral partition wall 400 is provided in outer place of set of bit lines 300, in the present embodiment to avoid set of bit lines 300 In be located at the bit line 310 on marginal position and be directly exposed to spacious second and be left white in area CC-2.Wherein, the peripheral partition wall 400 can be understood as being partially filled with described second and be left white area CC-2, with increase by second be left white area CC-2 circuit configuration it is intensive Degree, the difference for the circuit configuration concentration for avoiding the circuit configuration concentration of corresponding set of bit lines from being left white area with corresponding second It is excessive.

Wherein, the width dimensions of the peripheral partition wall 400 can be adjusted according to actual state.For example, the present embodiment In second be left white the width dimensions of area CC-2 much larger than the first size of space D1 between adjacent bit lines, can increase accordingly at this time outer The width dimensions of enclosure wall 400, so that the second size of space D2 between most marginal bit line 310 and peripheral partition wall 400 can Close to first size of space D1.In the present embodiment, the width dimensions of the periphery partition wall 400 are greater than the bit line 310 Width dimensions.And the length dimension of the peripheral partition wall 400 can also further be greater than the length dimension of bit line 310, and can make Two ends that two ends of the periphery partition wall 400 in their extension direction are respectively relative to the bit line further extend Out, so as to make the set of bit lines 300, face has the peripheral partition wall 400 on facing the second side for being left white area CC-2.

Further, the peripheral partition wall 400 includes the first partition wall portion, and first partition wall portion is along the first direction (X-direction) extends, and the bit line of corresponding edge position is arranged in far from the outside at set of bit lines center (that is, the of peripheral partition wall 400 The two sides of the set of bit lines 120 along the X direction are arranged in one partition wall portion).In the present embodiment, the periphery partition wall 400 only includes First partition wall portion, therefore the peripheral partition wall 400 can be strip structure and be parallel to the bit line 310.And it is based on Each bit line is successively sequentially arranged in the present embodiment, and the periphery partition wall 400 can be further disposed at top bit line and most bottom The outside of bit line, and comply with the distributing order of each bit line.

With continued reference to shown in Fig. 2 and Fig. 3, the integrated circuit memory further include: multiple bit line contact pads 320 are formed On the substrate 100, institute's bitline contact pad 320 is connect with the end of a bit line 310, for realizing each The extraction of bit line 310.It should be noted that institute's bitline contact pad 320 can be set in device region AA, also can be set In the BB of peripheral region, as long as bit line contact pad 320 can be connected with corresponding bit line 310, in the present embodiment, the bit line is connect Touch pad 320 is arranged in device region AA.

Wherein, the bit line 310 extends along opposite first end and the second end there are two the tools of direction.Preferred side Case, in two adjacent bit lines 310, corresponding two bit line contact pads 320 are respectively formed at the first of two bit lines On end and the second end.That is, wherein the bit line contact pad 320 of a bit line is formed in the first end of corresponding bit line On, the bit line contact pad 320 of another bit line is formed on the second end of corresponding bit line, so that two adjacent positions Two bit line contact pads 320 on line mutually stagger.In this way, which the area of each bit line engagement pad 320 can be increased.Especially It is, with the continuous promotion of the arrangement concentration of the continuous reduction and integrated circuit of dimensions of semiconductor devices, to utilize Photoetching process directly defines the bit line contact pad of microsize, and difficulty is also bigger.Also, by limit lithographic process window Limitation, also easily lead to occur between adjacent bit lines engagement pad the risk of short circuit.

Specifically, the multiple bit lines 310 in integrated circuit memory in its set of bit lines 300 are for example using pitch-multiplied work Skill (Pitch Doubling) formation, in this way, can make to be formed by multiple bit lines 310, the spacing between adjacent bit lines 310 Size is significantly smaller than photolithography limitation spacing dimension and the width dimensions of bit line 310 are also smaller than photolithography limitation width dimensions, into And be advantageously implemented integrated circuit memory its size reduction and the storage unit in integrated circuit memory arrangement it is close Collection degree.

Refering to what is shown in Fig. 1, its bit line contact pad 32 is normally located at each bit line in traditional integrated circuit memory On 31 same end.As it can be seen that for the set of bit lines 30 formed using pitch multiplication process, due to the width of each bit line Lesser spacing dimension is only reserved between the reduction and adjacent bit lines of size, therefore, is being defined by photoetching process and position When the bit line contact pad that line is correspondingly connected with, it need to need to ensure that the size of each bit line engagement pad 32 is sufficiently small, and need to avoid phase Adjacent 32 short circuit of bit line contact pad, however this will cause greatly to challenge to existing photoetching process.

It is each so as to increase however refering to what is shown in Fig. 2, multiple bit line contact pads 320 are staggered in the present embodiment The area of bit line contact pad 320, and the spacing between immediate two bit line contact pads 320 can be increased, therefore making When standby bit line contact pad 320, lithographic process window can be increased, to reduce the preparation difficulty of bit line contact pad 320, be effectively improved The problem of short circuit is easy to happen between adjacent bit lines engagement pad 320.As it can be seen that for the bit line formed using pitch multiplication process For group 300, staggered bit line contact pad 320 provided in the present embodiment, advantage is become apparent, and improvement is more For protrusion.

In addition, the integrated circuit memory further includes multiple peripheral circuits 500 with continued reference to shown in Fig. 2, it is multiple described Peripheral circuit 500 is formed in the peripheral region BB of the substrate.Wherein, the peripheral circuit 500 is for example including transistor, And further there is a gate structure.In preferred scheme, the gate structure and institute's bitline contact pad 320 are in same structure In layer and the gate structure and institute's bitline contact pad 320 can be formed simultaneously in same processing procedure, further, The peripheral circuit 500 and institute's bitline contact pad 320 can be formed using same conductive material layer.

Embodiment two

Difference with embodiment one is that the peripheral partition wall in the present embodiment includes the first partition wall portion and the second partition wall portion, To surround the outside of the set of bit lines using first partition wall portion and second partition wall portion.

Fig. 4 is the structural schematic diagram of the integrated circuit memory in the embodiment of the present invention two, as described in Figure 4, the periphery Partition wall includes the first partition wall portion 410 and the second partition wall portion 420.Wherein, first partition wall portion 410 is along the first direction (X Direction) extend, and the bit line 310 of corresponding edge position is set far from the outside at set of bit lines center；Second partition wall portion 420 Extend along the second direction (Y-direction), and the set of bit lines 300 is set close to the outside of each bit line end.That is, this In embodiment, the setting of the first partition wall portion 410 is left white in area CC-2 second, and the second partition wall portion 420, which is arranged, is left white area CC- first In 1.

Wherein, the end in first partition wall portion 410 and second partition wall portion 420 can be also further connected with each other, from And the peripheral partition wall being made of the first isolation part 410 and the second partition wall portion 420 is enable to surround along the outside of set of bit lines 300 The set of bit lines 300.Since the surrounding in set of bit lines 300 is surrounded with the peripheral partition wall, so as to utilize the outer enclosure Wall is protected can not only be avoided the bit line 310 in set of bit lines 300 positioned at marginal position from occurring largely by circular set of bit lines 300 Notch and lead to the problem of that figure is irregular, and the end of each bit line in set of bit lines 300 can also be avoided also to have preferably Pattern.

Further, in the present embodiment, the bit line contact pad (not shown) being connect with the end of each bit line 310, It can be arranged on the same end of bit line (that is, each bit line contact pad corresponding to each bit line can be arranged at bit line First end on, or be arranged on the second end of bit line).Certainly, institute's bitline contact pad can also such as embodiment one Shown in, on the staggered first end and the second end that corresponding bit line is set.

In the present embodiment, since the first partition wall portion 410 of peripheral partition wall and the second partition wall portion 420 are connected with each other, to make The peripheral partition wall constituted is configured to ring structure, and can be looped around on the outside of the set of bit lines 300.Further, institute Peripheral partition wall is stated also further around institute's bitline contact pad in the inside of its ring structure.

With continued reference to shown in Fig. 4, the memory further includes multiple peripheral circuits 500.In the present embodiment, the periphery electricity Road 500 is formed on the outside of the ring structure of the peripheral partition wall and the peripheral circuit 500, institute's bitline contact Pad 320, the peripheral partition wall and the bit line 310 are arranged in same structure layer.

Embodiment three

Based on integrated circuit memory as described above, the present invention also provides a kind of formation sides of integrated circuit memory Method.Fig. 5 is the flow diagram of the forming method of the integrated circuit memory in the embodiment of the present invention three, as described in Figure 5, institute The forming method for stating integrated circuit memory includes:

Step S100 provides a substrate, has multiple active areas in array arrangement in the substrate；

Step S200 forms a word line group in the substrate, the word line group include it is a plurality of along a first direction successively The wordline of arrangement, each wordline extend in a second direction and connect with the corresponding active area；

Step S300 forms a set of bit lines and a peripheral partition wall over the substrate, the set of bit lines include it is a plurality of along The bit line that second direction is successively arranged, each bit line connect with the corresponding active area and extend in a first direction, The periphery partition wall is formed in the periphery of the set of bit lines and is located in same structure layer with the set of bit lines.

Fig. 6 a~Figure 10 a is the forming method of the integrated circuit memory in the embodiment of the present invention three in its preparation process Top view, Fig. 6 b~Figure 10 b is respectively the integrated circuit memory in the embodiment of the present invention three shown in Fig. 6 a~Figure 10 a Forming method is in its preparation process along aa ' and bb ' diagrammatic cross-section in direction.Below in conjunction with attached drawing in the present embodiment Its each step of forming method is described in detail.

In the step s 100, with specific reference to a substrate 100 shown in Fig. 6 a and Fig. 6 b, is provided, have in the substrate 100 more A active area 110 in array arrangement, multiple active areas 110 constitute active area array.

As shown in Figure 6 a, defining in the substrate 100 has a device region AA and a peripheral region BB, and described peripheral region BB In the periphery of the device region AA, multiple active areas 110 are formed in the device region AA of the substrate 100.With And in the first direction (x-direction), from most marginal active area 110 between the boundary of the device region AA have bit line side It is left white area (that is, first is left white area CC-1)；In second direction (Y-direction), from most marginal active area 110 to the device region Also there is bit line side to be left white area (that is, second is left white area CC-2) between the boundary of AA.

Continuing with shown in Fig. 6 a and Fig. 6 b, isolation structure 120, the isolation junction are also formed in the substrate 100 Structure 120 is for being isolated adjacent active area 110 and isolating device area AA and peripheral region BB etc..

In step s 200, with continued reference to shown in Fig. 6 a and Fig. 6 b, one word line group of formation is described in the substrate 100 Word line group includes the wordline 210 that a plurality of (X-direction) along a first direction successively arranges, and each wordline 210 is in second direction Extend in (Y-direction) and is connected with the corresponding active area 110.In the present embodiment, the wordline 210 in the word line group is to cover Wordline is buried, is buried in the substrate 100.

It further, further include forming a separation layer 220 in the wordline 210 after forming the wordline 210, The wordline 210 to be isolated, the bitline short circuits for avoiding the problem that and being subsequently formed.In the present embodiment, the separation layer The 220 coverings wordline 210 and the surface for further covering the substrate 100.

It should be noted that the structural schematic diagram after forming wordline is only schematically illustrated in Fig. 6 a, it is attached in order to make Figure can be relatively sharp reflect the structure of word line group, wherein separation layer described above is omitted.

In step S300, with specific reference to shown in Fig. 7 a~Figure 10 a and Fig. 7 b~10b, a set of bit lines and a periphery are formed For partition wall 400 on the substrate 100, the set of bit lines includes a plurality of bit line successively arranged along second direction (Y-direction) 310, each bit line 310 connects with the corresponding active area 110 and extends in the first direction (x-direction), described outer Enclosure wall 400 is formed in the periphery of the set of bit lines and is located in same structure layer with the set of bit lines.

In the present embodiment, the periphery partition wall 400 and the bit line 310 of the set of bit lines are located in same structure layer, and The two can be formed in same processing step.Specifically, the figure of set of bit lines is defined simultaneously using same mask layer Figure with peripheral partition wall is in same conductive material layer, and by performing etching to same conductive material layer, with using same The conductive material layer is formed simultaneously bit line 310 and peripheral partition wall 400.I.e., it is possible to be interpreted as, by utilizing peripheral partition wall 400 Simulation bit line is constituted, to balance the intensive journey of circuit configuration of the bit line in corresponding edge region and corresponding intermediate region in set of bit lines Degree, to can alleviate etching agent when etching same conductive material layer in compact area and to the etching difference for dredging region, mention Height keeps the pattern of each bit line 310 in the set of bit lines being ultimately formed complete the etching homogeneity of conductive material layer.

Referring next to shown in Figure 10 a, the forming method of integrated circuit memory further include: form multiple bit line contact pads 320 on the substrate 100, and institute's bitline contact pad 320 is connect with the end of a bit line 310, for drawing The bit line 310 out.In addition, the integrated circuit memory being ultimately formed further includes multiple peripheral circuits 500, the periphery electricity Road 500 is formed on the substrate 100, and is located in the peripheral region BB.Wherein, the peripheral circuit 500 is, for example, crystal It manages and there is a gate structure.

In preferred scheme, the gate structure of the peripheral circuit 500 can be located at institute bitline contact pad 320 In same structure layer, and it can be formed in same processing step.For example, defining the periphery simultaneously using same mask layer The figure of circuit and the figure of institute's bitline contact pad execute etching technics and etch the film on same film material plies Material layer, to be formed simultaneously the peripheral circuit 500 and institute's bitline contact pad 320.

In the present embodiment, the set of bit lines, the peripheral partition wall 400, institute's bitline contact pad 320 and the peripheral circuit 500, same conductive material layer can be used and formed.That is, forming the set of bit lines, the peripheral partition wall using same conductive material layer 400, institute's bitline contact pad 320 and the peripheral circuit 500, so as to make the set of bit lines, the peripheral partition wall 400, institute Bitline contact pad 320 and the peripheral circuit 500 are located in same structure layer.Below in conjunction with attached drawing in the present embodiment, institute The forming method for stating set of bit lines, the peripheral partition wall 400, institute's bitline contact pad and the peripheral circuit is described in detail.

First step, with specific reference to shown in Fig. 7 b, one conductive material layer 600 of deposition is on the substrate 100, the conduction Material layer 600 covers the device region AA and the peripheral region BB.In the present embodiment, be also formed on the substrate 100 every Absciss layer 220, therefore the conductive material layer 600 is formed in accordingly on the separation layer 220.

Wherein, the conductive material layer 600 can further comprise a work function adjustment layer 610, conductive material layer 620 and absolutely Edge material layer 630.The work function adjustment layer 610, conductive material layer 620 and insulation material layer 630 are sequentially formed at the lining On bottom 100, and it is located on the separation layer 220.

Second step, with continued reference to shown in Fig. 7 a and Fig. 7 b, the first mask layer 710 of formation is in the conductive material layer 600 On, first mask layer 710 defines multiple peripheral circuit figures 711 and multiple bit line contacts pad figure 712, and described First mask layer 710 covers the part that the active area array is corresponded in the conductive material layer, and further extends and cover institute It states second and is left white area CC-2.

That is, in this step, defining the subsequent peripheral circuit that need to be formed simultaneously using the first mask layer 710 and bit line connecing The figure of touch pad, and active area array is covered simultaneously, to can ensure that the conductive material layer 600 on active area array can be protected It stays, for forming the bit line in set of bit lines in subsequent processing step.In addition, the subsequent bit line contact pad that is formed by is with after It is continuous to be formed by bit line connection, therefore, hidden in the bit line contact pad figure 712 and the first mask layer 710 in the first mask layer 710 The part for being stamped source region array is connected with each other.And second is also further set to be left white in area CC-2 using the first mask layer 710 Conductive material layer is retained, for forming peripheral partition wall in subsequent technique.

It should be noted that can clearly to illustrate that the first mask layer 710 is left white area with active area array and second The structure of separation layer and conductive material layer is omitted in Fig. 7 a for covering situation between CC-2.It should be appreciated, however, that in reality Preparation process in, be formed with out conductive material layer 600 below the first mask layer 710.

Third step is to conduct described in mask etching with first mask layer 710 with specific reference to shown in Fig. 8 a and Fig. 8 b Material layer 600, to form the peripheral circuit 500 and institute's bitline contact pad 320 in the conductive material layer 600, and Corresponded in the conductive material layer 600 the active area array and described second be left white area CC-2 part be retained.

It is connect that is, being formed by bit line contact pad 320 at this time with retained conductive material layer 600, so as to be subsequently formed Bit line can be correspondingly connected with bit line contact pad 320.

Optionally, it after performing etching the conductive material layer 600, still further comprises to form a side wall 640 and exist On the side wall of conductive material layer 600 after etching, to avoid the side wall of the conductive material layer 620 in the conductive material layer 600 It exposes.

Four steps, with specific reference to shown in Fig. 9 a and Fig. 9 b, the second mask layer 720 of formation is in the conductive material layer 600 On, second mask layer 720 defines multiple bit lines figure 721 on the active area array, and defines outer enclosure Wall figure 722 is left white in area CC-2 described second, also, second mask layer 720 covers the peripheral circuit 500 and institute Bitline contact pad 320.

In preferred scheme, before forming the second mask layer 720, further includes: form an insulation fill stratum 650 and etching In the conductive material layer 600 afterwards.

Specifically, after etching the conductive material layer 600 to form peripheral circuit 500 and bit line contact pad 320, It pads the conductive material layer 600 on 320 outsides positioned at the peripheral circuit 500 and bit line contact to be then removed accordingly, therefore It is to be understood that in peripheral circuit 500, bit line contact pad 320 and remaining conductive material layer 600 (for example, being located at active area battle array The conductive material layer being retained in column) between, that is, multiple grooves are defined, to make the surface exhibits of entire substrat structure not Even curface.

In the present embodiment, in a groove by the filling of insulation fill stratum 650, to make the surface exhibits of entire substrat structure Flat surface.In this way, being conducive to improve the preparation precision of subsequent technique.For example, forming patterned second mask layer When 720, the precision of bit line figure 721 formed in the second mask layer 720 and peripheral partition wall figure 722 can be improved.

With continued reference to shown in Fig. 9 a, the bit line figure 721 of the second mask layer 720 (side X along a first direction To) extend, and institute's bitline contact pad 320 is extended to, to enable to be formed by bit line and corresponding bit line contact pad 320 Connection.

It in the present embodiment, is formed in the conductive material layer 600 of bit line contact pad 320, multiple bit line contact pads 320 connect It is connected in the conductive material layer of corresponding active area array, i.e., adjacent bit line contact pad 320 is at this time still through conductive material layer It is connected with each other.Based on this, in the preferred scheme, the bit line figure 721 also further extends to institute's bitline contact pad 320 Interior zone in, thus enable between adjacent bit line contact pad 320 and the conductive material layer of non-corresponding bit line by Expose (that is, enable between adjacent bit lines engagement pad 320 conductive material layer interconnected by adjacent bit line figure it Between gap expose), and then by subsequent etching technics, can ensure between each bit line contact pad 320 mutually every It is disconnected.

It is to be understood that the length dimension of the bit line figure 721 of second mask layer 720, which is greater than, to be had in the present embodiment The length dimension on corresponding direction of source region array, so that bit line figure 721 be enable to extend to bit line from active area array In the interior zone of engagement pad 320.It should be appreciated that having biggish length based on 720 neutrality line figure 721 of the second mask layer Size (correspondingly, the gap between adjacent bit lines figure also has longer length dimension), thus utilizing photoetching process shape When at patterned second mask layer 720, even if still being able to guarantee adjacent bit line contact pad 320 there are lithography alignment deviation Between be connected with each other conductive material layer can be exposed from the gap of adjacent bit lines figure 721.

It is of course also possible to be interpreted as, when defining bit line contact pad 320, make to be formed by bit line contact pad 320 and extend to Active area array.That is: firstly, defining larger size and extending to the bit line contact pad 320 on active area array；Then, lead to Cross the portion extension that the second mask layer 720 exposes bit line contact pad 320, with ensure between adjacent bit lines engagement pad mutually every It is disconnected.

5th step is to pass described in mask etching with second mask layer 720 with specific reference to shown in Figure 10 a and Figure 10 b Material layer is led, to form the set of bit lines on the active area array, and forms the peripheral partition wall 400 described second It is left white in area CC-2.The set of bit lines includes multiple bit lines 310.

Since not only definition has multiple bit lines figure 721 in the second mask layer 720, and in the multiple bit lines figure 721 outside there is also defined peripheral partition wall figure 722, thus in making corresponding edge region in multiple bit lines figure 721 and corresponding to Between region bit line figure circuit configuration concentration it is identical or close to identical.At this point, when executing etching technics, it can Active balance conductive material layer corresponds to the quarter of the bit line figure of intermediate region and the bit line figure in corresponding edge region in correspondence Uniformity is lost, the part of the bit line figure of corresponding edge position in conductive material layer is avoided to be attacked by bigger etching, thus It can make the bit line 310 for being located at marginal position in the set of bit lines being ultimately formed, pattern is completely without etching notch etc. Problem.

In the present embodiment, multiple bit lines 310, bit line contact pad 320, peripheral partition wall 400 and the periphery electricity of the set of bit lines Road 500 is all made of same conductive material layer and is formed, to make four to be respectively positioned in same structure layer.

Example IV

The forming method for present embodiments providing another integrated circuit memory, the difference with embodiment three be, this Priority definition goes out set of bit lines and peripheral partition wall in embodiment, then re-defines out peripheral circuit and bit line contact pad.

Figure 11~Figure 13 is in the forming method of integrated circuit memory its preparation process in the embodiment of the present invention four Top view.With specific reference to shown in Figure 11~Figure 13, the set of bit lines, the peripheral partition wall, institute's bitline contact pad and the week The forming method of side circuit includes the following steps.

As step 1, with embodiment three classes, it may be assumed that one conductive material layer of deposition is on the substrate 100, the conduction material The bed of material covers the device region AA and peripheral region BB.

Step 2, with specific reference to shown in Figure 11, the second mask layer 720 of formation is in the conductive material layer, and described second Mask layer 720 defines multiple bit lines figure 721 on the active area array, and defines peripheral partition wall figure 722 and exist Described second is left white in area CC-2, and second mask layer 720 covers and corresponds to the peripheral region in the conductive material layer The part of BB, and further extend the part for covering and corresponding to active area array side in the conductive material layer.

That is, the corresponding subsequent bit line that need to be formed of the bit line figure 721 of second mask layer 720, peripheral partition wall figure 722 The corresponding subsequent peripheral partition wall that need to be formed.And it is covered using the second mask layer 720 and corresponds to the week in the conductive material layer The part of border area BB, so that peripheral region BB can be retained when subsequent etching conductive material layer is to form bit line and peripheral partition wall In conductive material layer, to be used to form peripheral circuit.Similar, the part of active area array side wall is located in conductive material layer It is used to form bit line contact pad.

Step 3 is conductive material layer described in mask etching with second mask layer 720 with specific reference to shown in Figure 12 600, to form a plurality of bit line 310 on the active area array, and the peripheral partition wall 400 is formed described second It is left white in area CC-2, and corresponds to the part of the peripheral region BB in the conductive material layer 600 and correspond to the active area battle array The part for arranging side is retained.

As embodiment three classes, after etching the conductive material layer to form bit line 310 and peripheral partition wall 400, It can also further comprise being formed in the conductive material layer of an insulation fill stratum after etching, be removed with filling in conductive material layer Part subsequent be formed by the first mask layer in favor of improving thus the surface for keeping the surface of entire substrat structure flat Pattern precision in 710.

Step 4 forms the first mask layer 710 in the conductive material layer 600 with specific reference to shown in Figure 13, and described the One mask layer 710 defines multiple peripheral circuit figures 711 in the peripheral region BB, and defines multiple bit line contact pads Figure 712 is on the side of the active area array, and first mask layer 710 covers the bit line in the set of bit lines 310 and the peripheral partition wall 400.

As shown in figure 13,710 covering part of the first mask layer second is left white area CC-2, and further outside part overlaid Enclosure wall 400.It is to be understood that after defining peripheral partition wall by the second mask layer, can further be utilized in the present embodiment First mask layer 710 adjusts the width dimensions of peripheral partition wall.For example, in the present embodiment, the first mask layer 710 is from peripheral partition wall Extend in width direction and cover peripheral partition wall, exposes part periphery partition wall, therefore can in subsequent etching process Reduce the width dimensions of peripheral partition wall, to adjust the size of the peripheral partition wall.

Step 5 is conductive material layer described in mask etching with first mask layer 710, to form the peripheral circuit With institute's bitline contact pad.It can refer to shown in Figure 10 a, so far can form integrated circuit memory as described above, and can Set of bit lines, bit line contact pad 320, peripheral partition wall 400 and peripheral circuit 500 are formed using same layer conductive material layer.

Embodiment five

It is formed by integrated circuit memory according to the forming method in the present embodiment, peripheral partition wall includes the first partition wall Portion and the second partition wall portion, to surround the outside of the set of bit lines using first partition wall portion and second partition wall portion.

Figure 14~Figure 16 is in the forming method of integrated circuit memory its preparation process in the embodiment of the present invention five Top view.Specifically, with peripheral partition wall, set of bit lines, the bit line contact in the first partition wall portion and the second partition wall portion in the present embodiment The forming method of pad and peripheral circuit includes the following steps.

First step deposits a conductive material layer on the substrate 100, and the conductive material layer covers the device region The AA and peripheral region BB.

Second step forms the first mask layer 710 ' in the conductive material layer with specific reference to shown in Figure 14, and described the One mask layer 710 ' defines multiple peripheral circuit figures 711 ' and multiple bit line contacts pad figure (not shown), and institute It states the first mask layer 710 ' and covers the part for corresponding to the active area array in the conductive material layer, and further extend and cover Described first, which is left white area CC-1 and second, is left white area CC-2.

First mask layer 710 ' covers active area array, can be protected with the conductive material layer ensured on active area array It stays, for forming the bit line in set of bit lines in subsequent processing step.And first mask layer 710 ' also further make first It is left white the conductive material layer that area CC-1 and second is left white in area CC-2 to be retained, to be used in subsequent technique respectively first It is left white in area CC-1 to form the first isolation part and be left white in area CC-2 second and forms the second isolation part, to constitute peripheral partition wall.

Third step is conductive material described in mask etching with first mask layer 710 ' with specific reference to shown in Figure 15 Layer 600, to form the peripheral circuit 500 and institute's bitline contact pad (not shown) in the conductive material layer 600, And the active area array is corresponded in the conductive material layer 600, first area CC-1 and second is left white and is left white the portion of area CC-2 Divide and is retained.

Four steps, with specific reference to shown in Figure 16, the second mask layer 720 ' of formation is in the conductive material layer 600, institute It states the second mask layer 720 ' and defines multiple bit lines figure 721 ' on the active area array, and define the first partition wall portion Figure 722 ' is left white in area CC-2 described second, and the second partition wall portion figure 723 ' is left white in area CC-1 described first, and Second mask layer 720 ' covers the peripheral circuit 500 and institute's bitline contact pad.

It should be noted that having defined the first partition wall portion and second based on the first mask layer 710 ' in the present embodiment Boundary of the partition wall portion far from set of bit lines, therefore the second mask layer 720 ' is in the first partition wall portion that defines and when the second partition wall portion, it can base Boundary setting first partition wall portion figure 722 ' of the conductive material layer retained after etching and the second partition wall portion figure Shape 723 ' is for example, in the present embodiment, and first partition wall portion figure 722 ' is for defining the first partition wall portion close to set of bit lines Boundary, the second partition wall portion figure 723 ' is for defining the second partition wall portion close to the boundary of set of bit lines.In this way, first can be passed through Mask layer 710 ' and the collaboration of the second mask layer 720 ' define first partition wall portion and the second partition wall portion.

5th step is conductive material layer 600 described in mask etching, the rheme to be formed with second mask layer 720 ' Line group on the active area array, and formed the first partition wall portion be left white in area CC-2 described second, and formed second every Wall portion is left white in area CC-1 described first.The set of bit lines includes multiple bit lines 310.

So far, i.e., set of bit lines in same structure layer, peripheral partition wall, periphery are formd using same conductive material layer Circuit and bit line contact pad.

Another object of the present invention is to provide a kind of semiconductor device, the semiconductor device Include:

One substrate, with multiple active areas in array arrangement in the substrate；And

One call wire group is formed over the substrate, and the call wire group includes a plurality of successively arranging along second direction Call wire, each call wire extends in a first direction and connects with the corresponding active area.

It is similar with integrated circuit memory as described above, when the periphery of call wire group is directly exposed to the big of its periphery When in dimensional space region, it is formed by marginal position then can frequently result in during preparing call wire group The problem of call wire deforms.

For this purpose, semiconductor device provided by the invention further include: a peripheral partition wall is formed over the substrate And the periphery of the call wire group is set, and the peripheral partition wall and the call wire group are located in same structure layer.From And it is uniform so that each call wire in semiconductor device its call wire group in the present invention is had preferable pattern Property, avoid the problem that the call wire being located on marginal position deforms.

In conclusion in integrated circuit memory provided by the invention, since the periphery of set of bit lines is provided with peripheral partition wall, The periphery partition wall can be protected during forming set of bit lines is located at the set of bit lines, avoids being located at margin location in set of bit lines The bit line set is attacked by biggish etching, so that the bit line in set of bit lines positioned at marginal position be avoided asking for figure deformation occur Topic.Also, by the way that peripheral partition wall is arranged, the circuit that intermediate region and corresponding edge region are corresponded in set of bit lines is balanced accordingly Arrangement concentration, to can make the etching even intensity that each bit line is subject in set of bit lines when forming set of bit lines, be conducive to Form set of bit lines of uniform morphology.

Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other The difference of embodiment, the same or similar parts in each embodiment may refer to each other.

Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.

Claims

1. a kind of integrated circuit memory characterized by comprising

One word line group is formed in the substrate, and the word line group includes a plurality of wordline successively arranged along a first direction, often One wordline extends in a second direction and connects with the corresponding active area；

One set of bit lines is formed over the substrate, and the set of bit lines includes a plurality of bit line successively arranged along second direction, often One bit line extends in a first direction and connects with the corresponding active area；And

One peripheral partition wall forms over the substrate and is arranged in the periphery of the set of bit lines, and the peripheral partition wall and institute Set of bit lines is stated to be located in same structure layer.

2. integrated circuit memory as described in claim 1, which is characterized in that have between first between the adjacent bit line Every size, the periphery partition wall is with parallel to having second size of space, second size of space between immediate bit line It is less than or equal to the width value of the bit line with the absolute difference of first size of space.

3. integrated circuit memory as described in claim 1, which is characterized in that the bit line partition wall includes the first partition wall portion, First partition wall portion extends along the first direction, and the bit line of corresponding edge position is arranged in far from set of bit lines center Outside.

4. integrated circuit memory as claimed in claim 3, which is characterized in that the periphery partition wall further includes the second partition wall Portion, second partition wall portion extend along the second direction, and the set of bit lines is arranged in close to the outer of each bit line end Side.

5. integrated circuit memory as claimed in claim 4, which is characterized in that first partition wall portion and second partition wall The end in portion is connected with each other, so that the peripheral partition wall constituted is configured to ring structure, and is looped around the periphery of the set of bit lines It places.

6. integrated circuit memory as described in claim 1, which is characterized in that the width dimensions of the periphery partition wall are greater than institute The width dimensions of rheme line.

7. integrated circuit memory as described in claim 1, which is characterized in that the length dimension of the periphery partition wall is greater than institute The length dimension of rheme line.

8. integrated circuit memory as described in claim 1, which is characterized in that further include:

Multiple bit line contact pads are formed over the substrate, and the end of institute's bitline contact pad and a bit line connects It connects.

9. integrated circuit memory as claimed in claim 8, which is characterized in that the bit line extends along there are two the tools of direction Opposite first end and the second end, in two adjacent bit lines, corresponding two bit line contact pads are respectively formed at On the first end and the second end of two bit lines.

10. integrated circuit memory as claimed in claim 8, which is characterized in that in the substrate definition have a device region and One peripheral region, the peripheral region are located at the periphery of the device region, multiple active areas, the word line group, the set of bit lines It is arranged in the device region of the substrate with the peripheral partition wall；

Wherein, in this second direction, most marginal active area between the boundary of the device region there is a bit line side to stay White area, the bit line side are left white the width dimensions of area in this second direction greater than the broad-ruler between the adjacent bit line Very little, the periphery partition wall is formed in the bit line side and is left white in area.

11. integrated circuit memory as claimed in claim 10, which is characterized in that further include:

Multiple peripheral circuits are formed in the peripheral region of the substrate, and the peripheral circuit has a gate structure, The gate structure and institute's bitline contact pad are in same structure layer.

12. a kind of forming method of integrated circuit memory characterized by comprising

One substrate is provided, there is an active area array in the substrate, the active area array includes multiple in array arrangement Active area；

Form a word line group in the substrate, the word line group includes a plurality of wordline successively arranged along a first direction, often One wordline extends in a second direction and connects with the corresponding active area 110；And

Form a set of bit lines and a peripheral partition wall over the substrate, the set of bit lines includes a plurality of successively arranging along second direction The bit line of cloth, each bit line extend in a first direction and connect with the corresponding active area, the periphery partition wall shape It is located in same structure layer in the periphery of the set of bit lines and with the set of bit lines.

13. the forming method of integrated circuit memory as claimed in claim 12, which is characterized in that the adjacent bit line it Between have first size of space, it is described periphery partition wall with it is parallel between immediate bit line have second size of space, it is described The absolute difference of second size of space and first size of space is less than or equal to the width value of the bit line.

14. the forming method of integrated circuit memory as claimed in claim 12, which is characterized in that the integrated circuit storage Device further includes the bit line contact pad of multiple formation over the substrate, the end of institute a bitline contact pad and a bit line Portion's connection.

15. the forming method of integrated circuit memory as claimed in claim 14, which is characterized in that there is definition in the substrate One device region and a peripheral region, the peripheral region are located at the periphery of the device region, multiple active areas, the word line group, The set of bit lines and the peripheral partition wall are both formed in the device region of the substrate；And in this second direction, Most marginal active area between the boundary of the device region there is a bit line side to be left white area.

16. the forming method of integrated circuit memory as claimed in claim 15, which is characterized in that over the substrate and right Answer and be also formed with multiple peripheral circuits in the peripheral region, the peripheral circuit have a gate structure, the gate structure and Institute's bitline contact pad is formed in same processing step.

17. the forming method of integrated circuit memory as claimed in claim 16, which is characterized in that use same conductive material Layer forms the set of bit lines, the peripheral partition wall, institute's bitline contact pad and the peripheral circuit, preparation method

Form the conductive material layer over the substrate, the conductive material layer covers the device region and the peripheral region；

The first mask layer is formed in the conductive material layer, first mask layer defines multiple peripheral circuit figures and more A bit line contact pads figure, and first mask layer covers the portion that the active area array is corresponded in the conductive material layer Point, and further extend to cover in the conductive material layer and correspond to the part that the bit line side is left white area；

Using first mask layer as conductive material layer described in mask etching, to form the peripheral circuit and institute's bitline contact Pad, and correspond to the active area array in the conductive material layer and the bit line side be left white area part it is retained；

The second mask layer is formed in the conductive material layer, second mask layer defines multiple bit lines figure to be had described It on source region array, and defines peripheral partition wall figure and is left white in area in the bit line side, and second mask layer covers The peripheral circuit and institute's bitline contact pad；And

Using second mask layer as conductive material layer described in mask etching, to form a plurality of bit line in the active area battle array On column, and forms the peripheral partition wall and be left white in area in the bit line side.

18. the forming method of integrated circuit memory as claimed in claim 16, which is characterized in that use same conductive material Layer forms the set of bit lines, the peripheral partition wall, institute's bitline contact pad and the peripheral circuit, preparation method

The second mask layer is formed in the conductive material layer, second mask layer defines multiple bit lines figure to be had described It on source region array, and defines peripheral partition wall figure and is left white in area in the bit line side, and second mask layer covers The part of the peripheral region is corresponded in the conductive material layer, and is further extended and covered in the conductive material layer described in correspondence The part of active area array side；

Using second mask layer as conductive material layer described in mask etching, to form a plurality of bit line in the active area battle array On column, and forms the peripheral partition wall and be left white in area in the bit line side, and correspond to the week in the conductive material layer The part of the part in border area and corresponding active area array side is retained；

The first mask layer is formed in the conductive material layer, first mask layer defines multiple peripheral circuit figures in institute It states in peripheral region, and defines multiple bit line contact pad figures on the side of the active area array, and described first Mask layer covers the set of bit lines and the peripheral partition wall；And

Using first mask layer as conductive material layer described in mask etching, to form the peripheral circuit and institute's bitline contact Pad.

19. a kind of semiconductor device characterized by comprising

One call wire group is formed over the substrate, and the call wire group includes a plurality of biography successively arranged along second direction Conducting wire, each call wire extend in a first direction and connect with the corresponding active area；And

One peripheral partition wall, forms over the substrate and is arranged in the periphery of the call wire group, and the peripheral partition wall and The call wire group is located in same structure layer.