CN110534512A - A kind of anti-latch domain structure - Google Patents
A kind of anti-latch domain structure Download PDFInfo
- Publication number
- CN110534512A CN110534512A CN201910844970.2A CN201910844970A CN110534512A CN 110534512 A CN110534512 A CN 110534512A CN 201910844970 A CN201910844970 A CN 201910844970A CN 110534512 A CN110534512 A CN 110534512A
- Authority
- CN
- China
- Prior art keywords
- contact zone
- metal
- contact
- area
- zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000036039 immunity Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention provides a kind of domain structure of anti-latch, including the area NWELL, the area PWELL, first contact zone P+, 2nd contact zone P+, first contact zone N+, 2nd contact zone N+, first active area, second active area, first polycrystalline grid, second polycrystalline grid, third polycrystalline grid, contact hole, first metal, second metal, third metal, 4th metal, the present invention breaks through existing standard CMOS cell domain structure, from the angle for reducing parasitic transistor base resistance, anti- latch domain structure is provided with the design of substrate contact and source contact proximity, the robustness of CMOS is improved from layout design angle.
Description
Technical field
The invention belongs to semiconductor power device technology fields, are related to a kind of anti-latch domain structure.
Background technique
Latch up, that is, latch-up, often occurs in CMOS integrated circuit.When extraneous triggering is so that cmos circuit
Internal parasitic transistor emitter positively biased simultaneously generates sufficiently large electric current, so that positively biased also occurs for another parasitic transistor simultaneously
Also forward conduction, when the product of the common-emitter current gain β of two parasitic transistors is greater than 1, circuit will generate low-resistance
Channel makes the current multiplication after triggering.If power supply is capable of providing the electric current after maintaining triggering at this time, device maintains latch
State can not turn off, and chip will be burnt.
The means of most direct anti-latch are exactly so that the current amplification factor of parasitic transistor is sufficiently small；In layout design
In, it can all increase metal-oxide-semiconductor source-drain area is at a distance from trap boundary or reasonable distribution substrate is with trap potential contact generally with as far as possible
Reduce the equivalent resistance RS and RW of substrate and trap.Under technology today, as shown in Fig. 2, can be by substrate contact in engineering design rule
There are larger spacing between source contact, from the angle of anti-latch, exist very between substrate contact and source contact
Big well resistance undoubtedly makes latch-up be easier to occur.In order to solve this problem, the present invention breaks through engineering common sense, from disappearing
Except the angle of well region and the big resistance of substrate zone, anti-latch is provided with the design of substrate contact and source contact proximity, from
The robustness of layout design angle raising cmos device.
Summary of the invention
The problem to be solved in the present invention is: in the case where not changing CMOS working performance, changing domain structure, is promoted
The latch-up immunity of cmos circuit.
For achieving the above object, technical solution of the present invention is as follows:
A kind of anti-latch domain structure, including part A: the area NWELL 100, the first P+ inside the area NWELL 100 connect
Touch area 201, positioned at 201 left end of the first contact zone P+ the 2nd contact zone N+ 102, be located at the first contact zone P+ 201 and the 2nd N+
The first active area 401 inside contact zone 102 further includes the first polycrystalline grid 001, the first metal 301, is located at the first active area
401 contact hole 501, wherein the first contact zone P+ 201 and 102 adjacent contact of the 2nd contact zone N+, the first polycrystalline grid 001
First contact zone P+ 201 in left side is connected by the first metal 301 with VDD with the 2nd contact zone N+ 102；
Further include part B: being connect with the area PWELL 200 of 100 adjacent contact of the area NWELL, the N+ inside the area PWELL 200
Touch area 101, positioned at 101 left end of the first contact zone N+ the 2nd contact zone P+ 202, be located at the first contact zone N+ 101 and the 2nd P+
The second active area 402 inside contact zone 202 further includes the second polycrystalline grid 002, the 4th metal 304, is located at the second active area
402 contact hole 501, wherein the first contact zone N+ 101 and 202 adjacent contact of the 2nd contact zone P+, and pass through the second metal
302 connect with GND；First contact zone N+ 101 and the 2nd contact zone P+ 202 in 002 left side of the second polycrystalline grid pass through the second gold medal
Belong to 302 to connect, the first polycrystalline grid 001 is connected with the second polycrystalline grid 002 by third polycrystalline grid 003, third metal 303
Connected with the 4th metal 304 by fifth metal 305.
It is preferred that the 2nd contact zone N+ 102 is adjacent with the first contact zone P+ 201 on width y and the direction length x
Contact；2nd contact zone P+ 202 on width y and the direction length x with 101 adjacent contact of the first contact zone N+.Fig. 4
It is preferred that including C portion: inside the area NWELL 100 be equipped with the 3rd contact zone N+ 103, the 3rd contact zone N+
103 surround the part A, the first P of the 3rd contact zone N+ 103, the 2nd contact zone N+ 102,001 left side of the first polycrystalline grid
201 three of+contact zone passes through the first metal 301, the 6th metal 306 connects with VDD；
Further include the part D: being located inside PWELL200 and be equipped with the 3rd contact zone P+ 203, the 3rd contact zone P+ 203 surrounds
The part B, the 3rd contact zone P+ 203, the 2nd contact zone P+ 202, the left side of the second polycrystalline grid 002 the first contact zone N+
101 threes pass through third metal 303, the 7th metal 307 connects with GND；Third metal 303 and the 4th metal 304, all pass through
Through-hole 502 connects with fifth metal 305.Fig. 5
It is preferred that being equipped with the 4th contact zone N+ 104 and the 4th contact zone P+ 204, the 4th N inside the area PWELL 200
+ contact zone 104 and 204 alternative expression of the 4th contact zone P+ are distributed, and surround the part D；Wherein the 4th contact zone N+ 104 with
4th contact zone P+ 204 is shorted by the 8th metal 308 and floating, and the 7th metal 307 passes through through-hole 502 and the 9th metal 309
Connect, the 9th metal 309 is connected by through-hole 502 with GND.Fig. 6
The invention has the benefit that existing standard CMOS cell laying out pattern scheme is broken through, from reduction parasitic transistor
The angle of base resistance provides anti-latch domain structure scheme with the design of substrate contact and source contact proximity, from version
The robustness of G- Design angle raising CMOS.
Detailed description of the invention
Fig. 1 is the equivalent circuit diagram of conventional CMOS circuit latch；
Fig. 2 is conventional MOS element layout structure；
Fig. 3 is the domain structure of embodiment 1；
Fig. 4 is the domain structure of embodiment 2；
Fig. 5 is the domain structure of embodiment 3；
Fig. 6 is the domain structure of embodiment 4.
001 is the first polycrystalline grid, 002 is the second polycrystalline grid, 003 is third polycrystalline grid, and 100 be the area NWELL,
101 be the first contact zone N+, 102 be the 2nd contact zone N+, 103 be the 3rd contact zone N+, 104 be the 4th contact zone N+, 200 are
The area PWELL, 201 for the first contact zone P+, 202 be the 2nd contact zone P+, 203 be the 3rd contact zone P+, 204 be the 4th P+ contact
Area, 301 be the first metal, 302 be the second metal, 303 be third metal, 304 be the 4th metal, 305 be fifth metal, 306
It is the 7th metal for the 6th metal, 307,308 is the 8th metal, 309 is the 9th metal, 401 is the first active area, 402 be the
Two active areas, 403 be third active area, 404 be the 4th active area, 501 be contact hole, 502 be through-hole.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Embodiment 1
As shown in figure 3, the present embodiment device architecture, including part A: the area NWELL 100, inside the area NWELL 100
First contact zone P+ 201, positioned at 201 left end of the first contact zone P+ the 2nd contact zone N+ 102, be located at the first contact zone P+ 201
And the 2nd the first active area 401 inside the contact zone N+ 102, further include the first polycrystalline grid 001, the first metal 301, be located at the
The contact hole 501 of one active area 401, wherein the first contact zone P+ 201 and 102 adjacent contact of the 2nd contact zone N+, the first polycrystalline
First contact zone P+ 201 in 001 left side of grid is connected by the first metal 301 with VDD with the 2nd contact zone N+ 102；
Further include part B: being connect with the area PWELL 200 of 100 adjacent contact of the area NWELL, the N+ inside the area PWELL 200
Touch area 101, positioned at 101 left end of the first contact zone N+ the 2nd contact zone P+ 202, be located at the first contact zone N+ 101 and the 2nd P+
The second active area 402 inside contact zone 202 further includes the second polycrystalline grid 002, the 4th metal 304, is located at the second active area
402 contact hole 501, wherein the first contact zone N+ 101 and 202 adjacent contact of the 2nd contact zone P+, and pass through the second metal
302 connect with GND；First contact zone N+ 101 and the 2nd contact zone P+ 202 in 002 left side of the second polycrystalline grid pass through the second gold medal
Belong to 302 to connect, the first polycrystalline grid 001 is connected with the second polycrystalline grid 002 by third polycrystalline grid 003, third metal 303
Connected with the 4th metal 304 by fifth metal 305.
The working principle of this example are as follows: design rule can provide the contact zone P+ and the contact zone N+ extremely in existing standard CMOS cell
There is certain spacing less.However if reality metal-oxide-semiconductor is when doing substrate contact, substrate contact and source contact be separated by it is certain between
Away from the well region between substrate contact and source contact has very big resistance, if generating pressure drop on biggish resistance can undoubtedly make
Have potential difference before source region and substrate, this potential difference can as parasitic transistor emitter bias by endophyte transistor
It opens, causes the latch of cmos circuit.In embodiment 1 using source region and substrate it is tangent close to laying out pattern, improve CMOS
Latch-up immunity.
Embodiment 2
As shown in figure 4, the difference of the domain structure and embodiment 1 of the present embodiment is: the 2nd contact zone N+ 102 is in width
On y and the direction length x with 201 adjacent contact of the first contact zone P+；2nd contact zone P+ 202 on width y and the direction length x with
First contact zone N+, 101 adjacent contact.
Embodiment 3
As shown in figure 5, the present embodiment and the main distinction of embodiment 1 are: including C portion: being set inside the area NWELL 100
There is the 3rd contact zone N+ 103, the 3rd contact zone N+ 103 surrounds the part A, the 3rd contact zone N+ 103, the 2nd contact zone N+
102,201 three of the first contact zone P+ in the left side of the first polycrystalline grid 001 all pass through the first metal 301, the 6th metal 306 with
VDD connects；Further include the part D: being located inside PWELL200 and be equipped with the 3rd contact zone P+ 203, the 3rd contact zone P+ 203 surrounds
The part B, the 3rd contact zone P+ 203, the 2nd contact zone P+ 202, the left side of the second polycrystalline grid 002 the first contact zone N+
101 threes pass through third metal 303, the 7th metal 307 connects with GND；Third metal 303 and the 4th metal 304, all pass through
Through-hole 502 connects with fifth metal 305.
Embodiment 4
As shown in fig. 6, the present embodiment and the main distinction of embodiment 3 are: being equipped with the 4th N+ inside the area PWELL 200 and connect
Area 104 and the 4th contact zone P+ 204 are touched, the 4th contact zone N+ 104 and 204 alternative expression of the 4th contact zone P+ are distributed, and are surrounded
The part D；Wherein the 4th contact zone N+ 104 and the 4th contact zone P+ 204 are shorted and floating by the 8th metal 308, and the 7th
Metal 307 is connected by through-hole 502 with the 9th metal 309, and the 9th metal 309 is connected by through-hole 502 with GND.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (4)
1. a kind of anti-latch domain structure, it is characterised in that:
Including part A: the area NWELL (100) are located at the first internal contact zone P+ (201) of the area NWELL (100), are located at the first P+
2nd contact zone N+ (102) of contact zone (201) left end is located in the first contact zone P+ (201) and the 2nd contact zone N+ (102)
First active area (401) in portion further includes the first polycrystalline grid (001), the first metal (301), is located at the first active area (401)
Contact hole (501), wherein the first contact zone P+ (201) and the 2nd contact zone N+ (102) adjacent contact, the first polycrystalline grid
(001) the first contact zone P+ (201) on the left of is connected by the first metal (301) with VDD with the 2nd contact zone N+ (102)；
It further include part B: with the area PWELL (200) of the area NWELL (100) adjacent contact, positioned at the area PWELL (200) internal N+
Contact zone (101), is located at the first contact zone N+ at the 2nd contact zone P+ (202) for being located at the first contact zone N+ (101) left end
It (101) and internal the second active area (402) in the 2nd contact zone P+ (202) further include, the second polycrystalline grid (002), the 4th gold medal
The contact hole (501) for belonging to (304), being located at the second active area (402), wherein the first contact zone N+ (101) and the 2nd contact zone P+
(202) adjacent contact, and connected by the second metal (302) with GND；The first N+ contact on the left of second polycrystalline grid (002)
Area (101) is connected with the 2nd contact zone P+ (202) by the second metal (302), the first polycrystalline grid (001) and the second polysilicon gate
Pole (002) is connected by third polycrystalline grid (003), and third metal (303) and the 4th metal (304) pass through fifth metal
(305) connect.
2. a kind of anti-latch domain structure according to claim 1, it is characterised in that: the 2nd contact zone N+ (102) is in width
Spend on y and the direction length x with the first contact zone P+ (201) adjacent contact；2nd contact zone P+ (202) is in width y and the length side x
Upwards with the first contact zone N+ (101) adjacent contact.
3. a kind of anti-latch domain structure according to claim 1, it is characterised in that: including C portion: the area NWELL (100)
Inside is equipped with the 3rd contact zone N+ (103), and the 3rd contact zone N+ (103) surrounds the part A, the 3rd contact zone N+ (103),
The first contact zone P+ (201) three on the left of 2nd contact zone N+ (102), the first polycrystalline grid (001) passes through the first metal
(301), the 6th metal (306) connects with VDD；
Further include the part D: being located inside PWELL (200) and be equipped with the 3rd contact zone P+ (203), the 3rd contact zone P+ (203) surrounds
Part B is stated in residence, the 3rd contact zone P+ (203), the 2nd contact zone P+ (202), the first N+ on the left of the second polycrystalline grid (002)
Contact zone (101) three passes through third metal (303), the 7th metal (307) connects with GND；Third metal (303) and the 4th
Metal (304) is all connected by through-hole (502) with fifth metal (305).
4. a kind of anti-latch domain structure according to claim 3, it is characterised in that: be equipped with the inside the area PWELL (200)
Four contact zones N+ (104) and the 4th contact zone P+ (204), the 4th contact zone N+ (104) and the 4th contact zone P+ (204) alternative expression
Distribution, and surround the part D；Wherein the 4th contact zone N+ (104) and the 4th contact zone P+ (204) pass through the 8th metal
(308) it is shorted and floating, the 7th metal (307) is connected by through-hole (502) with the 9th metal (309), the 9th metal (309) is logical
Through-hole (502) is crossed to connect with GND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910844970.2A CN110534512B (en) | 2019-09-07 | 2019-09-07 | Anti-latch-up layout structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910844970.2A CN110534512B (en) | 2019-09-07 | 2019-09-07 | Anti-latch-up layout structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110534512A true CN110534512A (en) | 2019-12-03 |
| CN110534512B CN110534512B (en) | 2023-02-07 |
Family
ID=68667612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910844970.2A Active CN110534512B (en) | 2019-09-07 | 2019-09-07 | Anti-latch-up layout structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110534512B (en) |
Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4035826A (en) * | 1976-02-23 | 1977-07-12 | Rca Corporation | Reduction of parasitic bipolar effects in integrated circuits employing insulated gate field effect transistors via the use of low resistance substrate contacts extending through source region |
| DE3414772A1 (en) * | 1983-04-25 | 1984-10-25 | Mitsubishi Denki K.K., Tokio/Tokyo | Complementary field-effect transistor |
| EP0276850A2 (en) * | 1987-01-28 | 1988-08-03 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with latch up preventing structure |
| US4797724A (en) * | 1982-06-30 | 1989-01-10 | Honeywell Inc. | Reducing bipolar parasitic effects in IGFET devices |
| US4922317A (en) * | 1986-08-06 | 1990-05-01 | Nissan Motor Company, Limited | CMOS device having Schottky diode for latch-up prevention |
| CN1164932A (en) * | 1995-04-06 | 1997-11-12 | 工业技术研究院 | N-sided polygonal cell lay-out for multiple cell transistor |
| US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
| US20030007301A1 (en) * | 2001-07-09 | 2003-01-09 | Ming-Dou Ker | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit |
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
| JP2004022877A (en) * | 2002-06-18 | 2004-01-22 | Matsushita Electric Ind Co Ltd | Standard cell for multiple power sources, standard cell library for automatic arrangement and wiring, power supply wiring method, and semiconductor integrated device |
| CN1581354A (en) * | 2003-08-06 | 2005-02-16 | 三洋电机株式会社 | Semiconductor device |
| CN1777997A (en) * | 2002-05-10 | 2006-05-24 | 通用半导体公司 | MOSFET device having geometry that permits frequent body contact |
| KR20090097720A (en) * | 2008-03-12 | 2009-09-16 | 주식회사 하이닉스반도체 | Cmos semiconductor devcie preventing lachup |
| US20110101465A1 (en) * | 2008-10-31 | 2011-05-05 | Freescale Semiconductor, Inc. | Cmos device structures |
| US20140027810A1 (en) * | 2012-07-27 | 2014-01-30 | Freescale Semiconductor, Inc. | Single-event latch-up prevention techniques for a semiconductor device |
| CN103887332A (en) * | 2013-10-15 | 2014-06-25 | 杭州恩能科技有限公司 | Novel power semiconductor device |
| US8841732B2 (en) * | 2011-08-03 | 2014-09-23 | GlobalFoundries, Inc. | Self-adjusting latch-up resistance for CMOS devices |
| US8912014B1 (en) * | 2006-01-18 | 2014-12-16 | Spansion Llc | Controlling the latchup effect |
| CN104319286A (en) * | 2014-11-04 | 2015-01-28 | 北京奥贝克电子股份有限公司 | Device structure applicable to bulk silicon CMOS and capable of restraining parasitic latch-up effect |
| CN105206609A (en) * | 2014-06-30 | 2015-12-30 | 万国半导体股份有限公司 | Compact guard ring structure for cmos integrated circuits |
| CN107833882A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | The electrostatic preventing structure of SOI technology |
-
2019
- 2019-09-07 CN CN201910844970.2A patent/CN110534512B/en active Active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4035826A (en) * | 1976-02-23 | 1977-07-12 | Rca Corporation | Reduction of parasitic bipolar effects in integrated circuits employing insulated gate field effect transistors via the use of low resistance substrate contacts extending through source region |
| US4797724A (en) * | 1982-06-30 | 1989-01-10 | Honeywell Inc. | Reducing bipolar parasitic effects in IGFET devices |
| DE3414772A1 (en) * | 1983-04-25 | 1984-10-25 | Mitsubishi Denki K.K., Tokio/Tokyo | Complementary field-effect transistor |
| US4922317A (en) * | 1986-08-06 | 1990-05-01 | Nissan Motor Company, Limited | CMOS device having Schottky diode for latch-up prevention |
| EP0276850A2 (en) * | 1987-01-28 | 1988-08-03 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with latch up preventing structure |
| CN1164932A (en) * | 1995-04-06 | 1997-11-12 | 工业技术研究院 | N-sided polygonal cell lay-out for multiple cell transistor |
| US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
| US20030007301A1 (en) * | 2001-07-09 | 2003-01-09 | Ming-Dou Ker | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit |
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
| CN1777997A (en) * | 2002-05-10 | 2006-05-24 | 通用半导体公司 | MOSFET device having geometry that permits frequent body contact |
| JP2004022877A (en) * | 2002-06-18 | 2004-01-22 | Matsushita Electric Ind Co Ltd | Standard cell for multiple power sources, standard cell library for automatic arrangement and wiring, power supply wiring method, and semiconductor integrated device |
| CN1581354A (en) * | 2003-08-06 | 2005-02-16 | 三洋电机株式会社 | Semiconductor device |
| US8912014B1 (en) * | 2006-01-18 | 2014-12-16 | Spansion Llc | Controlling the latchup effect |
| KR20090097720A (en) * | 2008-03-12 | 2009-09-16 | 주식회사 하이닉스반도체 | Cmos semiconductor devcie preventing lachup |
| US20110101465A1 (en) * | 2008-10-31 | 2011-05-05 | Freescale Semiconductor, Inc. | Cmos device structures |
| US8841732B2 (en) * | 2011-08-03 | 2014-09-23 | GlobalFoundries, Inc. | Self-adjusting latch-up resistance for CMOS devices |
| US20140027810A1 (en) * | 2012-07-27 | 2014-01-30 | Freescale Semiconductor, Inc. | Single-event latch-up prevention techniques for a semiconductor device |
| CN103887332A (en) * | 2013-10-15 | 2014-06-25 | 杭州恩能科技有限公司 | Novel power semiconductor device |
| CN105206609A (en) * | 2014-06-30 | 2015-12-30 | 万国半导体股份有限公司 | Compact guard ring structure for cmos integrated circuits |
| CN104319286A (en) * | 2014-11-04 | 2015-01-28 | 北京奥贝克电子股份有限公司 | Device structure applicable to bulk silicon CMOS and capable of restraining parasitic latch-up effect |
| CN107833882A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | The electrostatic preventing structure of SOI technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110534512B (en) | 2023-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100642651B1 (en) | Semiconductor controled rectifier for electro-static discharge protecting | |
| TWI409930B (en) | Structures for electrostatic discharge protection | |
| KR100976410B1 (en) | Electrostatic Discharge Device | |
| TWI523197B (en) | Electrostatic discharge protection device | |
| TW200410393A (en) | Electrostatic discharge protection device for mixed voltage interface | |
| CN101630673B (en) | Esd protection structures on soi substrates | |
| KR102254766B1 (en) | Lateral bipolar junction transistor having high current driving capability | |
| JP2012099749A (en) | Semiconductor device | |
| TW201618272A (en) | Electrstatic discharge protection circuit, structure and method of making the same | |
| TWI418010B (en) | Electrostatic discharge protection circuit and device | |
| CN103985710A (en) | ESD protection device of both-way SCR structure | |
| CN107564901B (en) | LDMOS device with ESD protection function and layout thereof | |
| KR100749231B1 (en) | Semiconductor device | |
| CN104253123B (en) | An electrostatic discharge protection structure | |
| TWI784502B (en) | Electrostatic discharge protection circuit | |
| CN110534512A (en) | A kind of anti-latch domain structure | |
| Oberoi et al. | Latch-up characterization and checking of a 55 nm CMOS mixed voltage design | |
| US9153570B2 (en) | ESD tolerant I/O pad circuit including a surrounding well | |
| JP2019511113A (en) | Output driver with power down protection | |
| KR102256043B1 (en) | Electrostatic discharge protection device | |
| CN109478549A (en) | ESD protection circuit applied to integrated circuit | |
| CN108346652A (en) | A kind of electrostatic discharge protection component | |
| Urresti et al. | Lateral punch-through TVS devices for on-chip protection in low-voltage applications | |
| CN102315217A (en) | Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit | |
| CN105405843B (en) | Electrostatic discharge protective circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |