CN110532577B - Digital logic circuit compiling method and device - Google Patents
Digital logic circuit compiling method and device Download PDFInfo
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Abstract
The invention provides a method and a device for compiling a digital logic circuit, which relate to the technical field of circuits, and comprise the following steps: the method comprises the steps of obtaining compiling steps of the digital logic circuit, judging whether time sequence reports corresponding to the compiling steps meet preset time sequence requirements one by adopting a sequence reverse to the compiling sequence of the digital logic circuit, determining the compiling steps corresponding to the time sequence reports which do not meet the preset time sequence requirements as target compiling steps, taking the compiling strategies corresponding to the time sequence reports which meet the preset time sequence requirements as target compiling strategies according to the time sequence reports corresponding to each compiling strategy, and recompiling the digital logic circuit according to the target compiling strategies. Because the data output by the compiling step before the target compiling step can be used in the process of recompiling the digital logic circuit by adopting the target compiling strategy, the time spent by the client for recompiling the digital logic circuit can be reduced, and the efficiency of recompiling the digital logic circuit can be improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of circuits, in particular to a digital logic circuit compiling method and a digital logic circuit compiling device.
Background
With the continuous development of digital logic circuits, the scale of digital logic circuits is also continuously expanding, and users can compile and obtain large-scale digital logic circuits in a software and hardware combined mode in the process of designing the digital logic circuits.
In the related art, a client can obtain a circuit code written by a user and used for generating a digital logic circuit, execute a plurality of compiling steps such as synthesis, conversion, layout, optimization and wiring according to a compiling strategy corresponding to each preset compiling step according to the circuit code, and finally compile to obtain a large-scale digital logic circuit.
However, a user can only know whether the compiled digital logic circuit meets the timing requirement after executing each compiling step, and when the digital logic circuit does not meet the timing requirement, the compiling strategy needs to be reset for compiling, which causes the problems of long time spent on compiling the digital logic circuit and low efficiency.
Disclosure of Invention
Embodiments of the present invention provide a method and an apparatus for compiling a digital logic circuit, so as to solve the problems of long time and low efficiency for recompiling the digital logic circuit when the digital logic circuit does not meet the timing requirement.
In order to solve the technical problem, the invention is realized as follows: a digital logic circuit compilation method, the method comprising:
acquiring compiling steps of the digital logic circuit, wherein each compiling step corresponds to a strategy set, each strategy set comprises at least one compiling strategy, and each compiling strategy has a corresponding time sequence report;
adopting a sequence reverse to the compiling sequence of the digital logic circuit to judge whether the time sequence report corresponding to each compiling step meets the preset time sequence requirement one by one;
when any one time sequence report does not meet the preset time sequence requirement, determining the compiling step corresponding to the time sequence report as a target compiling step;
acquiring a time sequence report corresponding to each compiling strategy in a target strategy set, wherein the target strategy set is a strategy set corresponding to the target compiling step;
according to the time sequence report corresponding to each compiling strategy, taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a target compiling strategy;
recompiling the digital logic circuit according to the target compilation strategy.
Optionally, the taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a target compiling strategy includes:
traversing the time sequence report corresponding to each compiling strategy, and taking the time sequence report meeting the preset time sequence requirement as a target time sequence report;
selecting a compiling strategy corresponding to the target time sequence report from the target strategy set;
and taking the compiling strategy corresponding to the target timing report as the target compiling strategy.
Optionally, after recompiling the digital logic circuit according to the target compilation strategy, the method further includes:
judging whether the recompiled digital logic circuit meets the preset time sequence requirement or not;
when the recompiled digital logic circuit does not meet the preset time sequence requirement, recompiling the digital logic circuit again until the recompiled digital logic circuit meets the preset time sequence requirement.
Optionally, before the compiling step of obtaining the digital logic circuit, the method further includes:
for each compiling step, parallelly operating a plurality of compiling strategies in a corresponding strategy set according to preset circuit codes, wherein the preset circuit codes are used for generating a preset digital logic circuit;
acquiring a time sequence report generated by each compiling strategy according to the preset circuit codes;
and taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a preset compiling strategy.
Optionally, the recompiling the digital logic circuit according to the target compilation strategy includes:
judging whether the target compiling step is the last compiling step of the digital logic circuit or not;
when the target compiling step is the last compiling step of the digital logic circuit, recompiling the digital logic circuit according to the target compiling strategy;
when the target compiling step is not the last compiling step of the digital logic circuit, recompiling the digital logic circuit according to the target compiling strategy and preset compiling strategies corresponding to all compiling steps after the target compiling step.
Optionally, after the compiling strategy corresponding to the timing report meeting the preset timing requirement is taken as a target compiling strategy, the method further includes:
and updating the preset compiling strategy corresponding to the target compiling step according to the target compiling strategy.
Optionally, before the compiling step of obtaining the digital logic circuit, the method further includes:
judging whether the digital logic circuit meets the preset time sequence requirement or not;
the compiling step of obtaining the digital logic circuit includes:
and when the digital logic circuit does not meet the preset time sequence requirement, acquiring a compiling step of the digital logic circuit.
On the other hand, an embodiment of the present invention further provides a digital logic circuit compiling apparatus, where the digital logic circuit compiling apparatus includes:
the first obtaining module is used for obtaining compiling steps of the digital logic circuit, wherein each compiling step corresponds to a strategy set, each strategy set comprises at least one compiling strategy, and each compiling strategy has a corresponding time sequence report;
the first judgment module is used for judging whether the time sequence reports corresponding to the compiling steps meet the preset time sequence requirements one by one in a sequence reverse to the compiling sequence of the digital logic circuit;
a step determining module, configured to determine, when any one of the timing reports does not meet the preset timing requirement, a compiling step corresponding to the timing report as a target compiling step;
a second obtaining module, configured to obtain a timing report corresponding to each compiling policy in a target policy set, where the target policy set is a policy set corresponding to the target compiling step;
the strategy determining module is used for taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a target compiling strategy according to the time sequence report corresponding to each compiling strategy;
and the compiling module is used for recompiling the digital logic circuit according to the target compiling strategy.
Optionally, the policy determining module includes:
the report determining submodule is used for traversing the time sequence report corresponding to each compiling strategy and taking the time sequence report meeting the preset time sequence requirement as a target time sequence report;
the selection submodule is used for selecting a compiling strategy corresponding to the target time sequence report from the target strategy set;
and the strategy determination submodule is used for taking the compiling strategy corresponding to the target timing report as the target compiling strategy.
Optionally, the apparatus further comprises:
the second judging module is used for judging whether the recompiled digital logic circuit meets the preset time sequence requirement or not;
the compiling module is further configured to recompile the digital logic circuit again when the recompiled digital logic circuit does not meet the preset timing requirement until the recompiled digital logic circuit meets the preset timing requirement.
Optionally, the apparatus further comprises:
the strategy operation module is used for operating a plurality of compiling strategies in a corresponding strategy set in parallel according to preset circuit codes for each compiling step, wherein the preset circuit codes are used for generating a preset digital logic circuit;
the third acquisition module is used for acquiring a time sequence report generated by each compiling strategy according to the preset circuit codes;
and the preset strategy determining module is used for taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a preset compiling strategy.
Optionally, the compiling module includes:
a judging submodule for judging whether the target compiling step is the last compiling step of the digital logic circuit;
a first compiling submodule, configured to recompile the digital logic circuit according to the target compiling strategy when the target compiling step is a last compiling step of the digital logic circuit;
and the second compiling submodule is used for recompiling the digital logic circuit according to the target compiling strategy and preset compiling strategies corresponding to all compiling steps after the target compiling step when the target compiling step is not the last compiling step of the digital logic circuit.
Optionally, the apparatus further comprises:
and the updating module is used for updating the preset compiling strategy corresponding to the target compiling step according to the target compiling strategy.
Optionally, the apparatus further comprises:
the third judging module is used for judging whether the digital logic circuit meets the requirement of the preset time sequence;
the first obtaining module comprises:
and the obtaining submodule is used for obtaining the compiling step of the digital logic circuit when the digital logic circuit does not meet the preset time sequence requirement.
In the embodiment of the invention, in the compiling step of the digital logic circuit, checking is carried out according to the reverse sequence opposite to the sequence of the compiling step, whether the time sequence reports corresponding to the compiling steps meet the preset time sequence requirement is detected one by one, so that the compiling step which does not meet the preset time sequence requirement is determined as a target compiling step, each compiling strategy in a target strategy set corresponding to the target compiling step is operated in parallel, the target compiling strategy is determined, and finally the digital logic circuit is recompiled according to the target compiling strategy. Because the data output by the compiling step before the target compiling step can be used in the process of recompiling the digital logic circuit by adopting the target compiling strategy, the time spent by the client for recompiling the digital logic circuit can be reduced, and the efficiency of recompiling the digital logic circuit can be improved.
Drawings
FIG. 1 is a flowchart illustrating steps of a method for compiling digital logic circuits according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating steps of a method for compiling digital logic circuits according to an embodiment of the present invention;
fig. 3 is a block diagram of a digital logic circuit compiling apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a flowchart illustrating steps of a digital logic circuit compiling method according to an embodiment of the present invention is shown, which may specifically include the following steps:
In the process of compiling the digital logic circuit, circuit codes provided by a user can be used as input data, compiling processing is carried out through each compiling step to obtain processed and compiled data, and finally the digital logic circuit corresponding to the circuit codes can be generated according to the compiled data.
Wherein the circuit code is used to generate a digital logic circuit. In addition, the data output by each compilation step may be used as input data for the next compilation step.
Before the digital logic circuit is generated, the digital logic circuit needs to be judged according to compiled data, whether the digital logic circuit generated according to the compiled data meets the preset time sequence requirement or not is determined, and if the digital logic circuit does not meet the preset time sequence requirement, the digital logic circuit needs to be compiled again so that the digital logic circuit can meet the preset time sequence requirement.
In order to reduce the time taken to recompile the digital logic circuit, the client needs to first obtain the compiling step of the digital logic circuit, so that in the subsequent steps, the detection can be performed according to the sequence of the compiling step to determine the compiling step corresponding to the timing report which does not meet the preset timing requirement.
The client side can compile the digital logic circuit through the corresponding compiling strategy, and determine whether the compiling step to which the corresponding compiling strategy belongs meets the preset time sequence requirement according to each time sequence report.
Therefore, if the digital logic circuit needs to be recompiled, each compiling step for compiling the digital logic circuit can be obtained according to the pre-stored data. For example, when it is determined that the digital logic circuit does not satisfy the preset timing requirement, the compiling steps of "synthesizing", "converting", "laying out", "optimizing", and "routing" may be obtained in the order in which the digital logic circuit is compiled.
And 102, judging whether the time sequence reports corresponding to the compiling steps meet the preset time sequence requirement one by adopting a sequence reverse to the compiling sequence of the digital logic circuit.
After the compiling steps for compiling the digital logic circuit are obtained, the checking can be carried out according to a reverse sequence opposite to the compiling sequence, and whether the time sequence report corresponding to the compiling strategy adopted by each compiling step meets the preset time sequence requirement is confirmed from back to front.
Specifically, the client may determine a reverse order opposite to the compiling order according to the compiling steps of compiling the digital logic circuit, and then determine whether the timing report corresponding to each compiling step meets the preset timing requirement one by one according to the reverse order. If the time sequence report corresponding to a certain compiling step meets the preset time sequence requirement, the compiling strategy adopted by the compiling step is the optimal compiling strategy, the compiling strategy of the compiling step does not need to be changed, and the client can continuously judge whether the time sequence report corresponding to the next compiling step meets the preset time sequence requirement or not until the time sequence report corresponding to a certain compiling step is determined not to meet the preset time sequence requirement.
For example, corresponding to the example of step 101, if the digital logic circuit is compiled in the order: "synthesize", "transform", "place", "optimize", and "route", then the reverse order, which is opposite to the compilation order, is: the "wiring", "optimizing", "layout", "converting", and "synthesizing", if the timing report corresponding to the "optimizing" in the compiling step satisfies the preset timing requirement, the client may continue to determine whether the timing report corresponding to the "layout" in the compiling step satisfies the preset timing requirement.
And 103, when any one time sequence report does not meet the preset time sequence requirement, determining the compiling step corresponding to the time sequence report as a target compiling step.
After the judgment is performed according to the reverse sequence, if it is detected that the time sequence report corresponding to any one compiling step does not meet the preset time sequence requirement, it indicates that the compiling strategy adopted by the compiling step may not be the optimal compiling strategy, and the compiling strategy adopted by the compiling step needs to be changed, the client may determine the compiling step as the target compiling step, so as to update the compiling strategy adopted by the target compiling step in the subsequent steps.
And 104, acquiring a time sequence report corresponding to each compiling strategy in the target strategy set.
Wherein, the target strategy set is a strategy set corresponding to the target compiling step.
After the target compiling strategy is determined, the client can obtain a target strategy set corresponding to the target compiling strategy, and run a plurality of compiling strategies in the target strategy set in parallel, so that each compiling strategy can generate a corresponding time sequence report according to a circuit code provided by a user.
Wherein the circuit code is edited by a user to generate a digital logic circuit that meets the user's requirements.
Specifically, the client may select a preset number of compiling strategies from the target strategy set, run the selected preset number of compiling strategies in parallel, obtain a time sequence report corresponding to each compiling strategy after the running is completed, select the preset number of compiling strategies from the target strategy set again, and run the selected compiling strategies in parallel to obtain the time sequence report corresponding to each compiling strategy until the time sequence report of each compiling strategy in the target strategy set is obtained.
And 105, taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a target compiling strategy according to the time sequence report corresponding to each compiling strategy.
After obtaining the timing report corresponding to each compiling strategy in the target strategy set, the client may match each timing report with the preset timing requirement, find the timing report matching with the preset timing requirement, and finally may use the compiling strategy corresponding to the failure report as the target compiling strategy.
It should be noted that, the embodiment of the present invention may also determine the target compiling policy in other ways, which is not limited in the embodiment of the present invention.
For example, in step 104, the client may finish running the preset number of compiling strategies in parallel, and obtain the timing reports corresponding to the compiling strategies, and then match the obtained timing reports with the preset timing requirements, and determine whether the obtained timing reports include the timing report meeting the preset timing requirements. When the obtained multiple timing reports include a timing report meeting a preset timing requirement, determining the compiling strategy corresponding to the timing report as a target compiling strategy, and stopping running the compiling strategy, but if the obtained multiple timing reports do not include the timing report meeting the preset timing requirement, running the multiple compiling strategies in parallel again, and matching according to the obtained multiple timing reports again until a timing report matching the preset timing requirement is obtained, so as to determine the target compiling strategy.
And 106, recompiling the digital logic circuit according to the target compiling strategy.
After the target compiling strategy is determined, the client can compile the circuit code of the user again according to the target compiling strategy in the target compiling step and the preset compiling strategy preset in other steps, so that the digital logic circuit meeting the preset time sequence requirement can be obtained.
Specifically, the client may determine a position where the target compiling step is located according to the compiling step of the digital logic circuit, and determine a compiling step adjacent to the target compiling step and before the target compiling step, and then may obtain data output by the compiling step, and use the data output by the compiling step as input data of the target compiling step, so as to compile the input data again by using a target compiling strategy, and finally obtain a recompiled digital logic circuit.
Further, if there are other compiling steps after the target compiling step, the client may use the data output by the target compiling step as the input data of the compiling step after the target compiling step, and compile by using the preset compiling strategy of the other compiling steps, so as to obtain the digital logic circuit.
However, if there is no other compiling step after the target compiling step, that is, the target compiling step is the last compiling step of the digital logic circuit, the compiled digital logic circuit may be generated according to the data output by the target compiling step.
In summary, in the digital logic circuit compiling method provided in the embodiments of the present invention, the compiling steps of the digital logic circuit are obtained, and the steps are checked according to the reverse order opposite to the compiling step order, and whether the timing reports corresponding to the compiling steps meet the preset timing requirement is detected one by one, so that the compiling step that does not meet the preset timing requirement is determined as the target compiling step, and the compiling strategies in the target strategy set corresponding to the target compiling step are run in parallel, so as to determine the target compiling strategy, and finally the digital logic circuit is recompiled according to the target compiling strategy. Because the data output by the compiling step before the target compiling step can be used in the process of recompiling the digital logic circuit by adopting the target compiling strategy, the time spent by the client for recompiling the digital logic circuit can be reduced, and the efficiency of recompiling the digital logic circuit can be improved.
Referring to fig. 2, a flowchart illustrating steps of a digital logic circuit compiling method according to an embodiment of the present invention is shown, which may specifically include the following steps:
In the process of compiling the digital logic circuit by the client, the circuit code provided by the user can be compiled through a plurality of compiling steps, and finally the digital logic circuit is obtained. Each compiling step may correspond to one policy set, and each policy set includes a plurality of compiling policies, so that, before the digital logic circuit is compiled, a preset compiling policy corresponding to each compiling step needs to be determined, so that in a subsequent step, the digital logic circuit is compiled according to the preset compiling policy to obtain the digital logic circuit.
Optionally, for each compiling step, a plurality of compiling strategies in the corresponding strategy set may be run in parallel according to the preset circuit code, a timing report generated by each compiling strategy according to the preset circuit code is obtained, and the compiling strategy corresponding to the timing report meeting the preset timing requirement is used as the preset compiling strategy.
Wherein the preset circuit code is used to generate a preset digital logic circuit.
The process of obtaining the preset compiling strategy in step 201 is similar to the process of obtaining the target compiling strategy in step 105, and is not described herein again.
The client compiles according to a preset compiling strategy corresponding to each compiling step according to a circuit code provided by a user, and before generating the digital logic circuit according to data output by each compiling step, the client also needs to judge according to data output by the last compiling step to determine whether the digital logic circuit meets the preset time sequence requirement.
When the digital logic circuit to be generated is determined to meet the preset time sequence requirement, the corresponding digital logic circuit can be generated according to the data output by the compiling step. However, if the digital logic circuit does not satisfy the predetermined timing requirement, the digital logic circuit needs to be recompiled by performing the subsequent steps so that the digital logic circuit satisfies the predetermined timing requirement.
And step 204, adopting a sequence reverse to the compiling sequence of the digital logic circuit, and judging whether the time sequence reports corresponding to the compiling steps meet the preset time sequence requirements one by one.
Since the process from step 203 to step 206 is similar to the process from step 101 to step 104, it is not described herein again.
After the client acquires the timing report corresponding to each compiling strategy, each timing report can be matched with the preset timing requirement, the timing report meeting the preset timing requirement is determined, and therefore the corresponding compiling strategy is selected as the target compiling strategy.
Optionally, the client may traverse the timing report corresponding to each compiling policy, use the timing report meeting the preset timing requirement as a target timing report, select the compiling policy corresponding to the target timing report from the target policy set, and use the compiling policy corresponding to the target timing report as the target compiling policy.
Specifically, after acquiring each timing report, the client may compare the timing report corresponding to each compiling policy with the preset timing requirement, and determine whether each timing report meets the preset timing requirement. When a certain time sequence report meets the preset time sequence requirement, the time sequence report can be used as a target time sequence report, a compiling strategy corresponding to the target time sequence report is selected from a target strategy set, and finally the selected compiling strategy can be used as a target compiling strategy.
And 208, updating the preset compiling strategy corresponding to the target compiling step according to the target compiling strategy.
Each compiling step corresponds to a preset compiling strategy, but if a time sequence report corresponding to a certain preset compiling strategy does not meet the preset time sequence requirement, the preset compiling strategy is not the optimal strategy for compiling the current circuit code, and the preset compiling strategy needs to be replaced.
Therefore, the client may replace the preset compiling strategy corresponding to the target compiling step with the target compiling strategy, that is, the target compiling strategy is used as the preset compiling strategy of the target compiling step, so as to update the preset compiling strategy.
Step 209 recompiles the digital logic circuit according to the target compilation strategy.
In the process of compiling the digital logic circuit, the target compiling step may be any one of a plurality of compiling steps, and the target compiling step may be the last compiling step in the compiling process or other compiling steps.
When the target compiling step is not the last compiling step in the compiling process, compiling is further carried out according to preset compiling strategies corresponding to other compiling steps. Therefore, in the process of recompiling the digital logic circuit according to the target compiling strategy, the digital logic circuit needs to be recompiled by adopting different compiling modes according to different positions where the target compiling step is located.
Optionally, the client may determine whether the target compiling step is a last compiling step of the digital logic circuit, and when the target compiling step is the last compiling step of the digital logic circuit, recompile the digital logic circuit according to the target compiling strategy; however, when the target compiling step is not the last compiling step of the digital logic circuit, the digital logic circuit may be recompiled according to the target compiling strategy and the preset compiling strategies corresponding to the compiling steps after the target compiling step.
Specifically, when the target compiling step is the last compiling step, the previous compiling step of the target compiling step may be determined, the data output by the compiling step is obtained, the data is used as the input data of the target compiling step, and the input data is compiled through the target compiling strategy to obtain the data output by the target compiling step, so that in the subsequent steps, whether the recompiled digital logic circuit meets the preset time sequence requirement is determined according to the output data.
Correspondingly, when the target compiling step is not the last compiling step, the data output by the previous compiling step is also required to be used as the input data of the target compiling step, and then the data output by the target compiling step is used as the input data of the subsequent compiling step, so that the subsequent compiling step adopts a preset compiling strategy to carry out compiling, and finally the data used for generating the digital logic circuit is obtained.
After the client obtains the recompiled data for generating the digital logic circuit, the client can analyze and judge the data and determine whether the digital logic circuit generated according to the data meets the preset time sequence requirement or not.
When it is determined that the recompiled digital logic circuit still does not meet the preset timing requirement, step 203 to step 210 may be executed again, that is, the recompiled digital logic circuit is recompiled again, and whether the recompiled digital logic circuit meets the preset timing requirement is determined until the recompiled digital logic circuit meets the preset timing requirement.
Optionally, the client may determine whether the recompiled digital logic circuit meets the preset timing requirement, and when the recompiled digital logic circuit does not meet the preset timing requirement, recompile the digital logic circuit again until the recompiled digital logic circuit meets the preset timing requirement.
The above process is similar to the process from step 203 to step 210, and is not described herein again.
It should be noted that, when the client recompiles again, the detection may be started from the compiling step adjacent to and before the target compiling step according to the reverse order of compiling the digital logic circuit, and whether the timing report corresponding to each compiling step meets the preset timing requirement is determined, so as to determine a new target compiling step and a target compiling strategy.
For example, the order in which the digital logic circuits are compiled is: "synthesize", "transform", "place", "optimize", and "route", the reverse order, which is opposite to the compilation order, is then: the method comprises the steps of wiring, optimizing, laying out, converting and synthesizing, wherein if the laying out of the compiling step in the last recompiling process is a target compiling step, the detecting can be started from the converting of the compiling step in the recompiling process, so that the target compiling step of the recompiling process is determined.
In summary, in the digital logic circuit compiling method provided in the embodiments of the present invention, the compiling steps of the digital logic circuit are obtained, and the steps are checked according to the reverse order opposite to the compiling step order, and whether the timing reports corresponding to the compiling steps meet the preset timing requirement is detected one by one, so that the compiling step that does not meet the preset timing requirement is determined as the target compiling step, and the compiling strategies in the target strategy set corresponding to the target compiling step are run in parallel, so as to determine the target compiling strategy, and finally the digital logic circuit is recompiled according to the target compiling strategy. Because the data output by the compiling step before the target compiling step can be used in the process of recompiling the digital logic circuit by adopting the target compiling strategy, the time spent by the client for recompiling the digital logic circuit can be reduced, and the efficiency of recompiling the digital logic circuit can be improved.
Referring to fig. 3, a block diagram of a digital logic circuit compiling apparatus according to an embodiment of the present invention is shown, which may specifically include:
a first obtaining module 301, configured to obtain compiling steps of the digital logic circuit, where each compiling step corresponds to a policy set, each policy set includes at least one compiling policy, and each compiling policy has a corresponding time sequence report;
a first determining module 302, configured to determine, one by one, whether the timing report corresponding to each compiling step meets a preset timing requirement by using a sequence that is reverse to a compiling sequence of the digital logic circuit;
a step determining module 303, configured to determine, when any one of the timing reports does not meet the preset timing requirement, a compiling step corresponding to the timing report as a target compiling step;
a second obtaining module 304, configured to obtain a timing report corresponding to each compiling policy in a target policy set, where the target policy set is a policy set corresponding to the target compiling step;
a policy determining module 305, configured to use, according to the timing report corresponding to each compiling policy, the compiling policy corresponding to the timing report meeting the preset timing requirement as a target compiling policy;
a compiling module 306 for recompiling the digital logic circuit according to the target compiling strategy.
Optionally, the policy determining module 305 may include:
the report determining submodule is used for traversing the time sequence report corresponding to each compiling strategy and taking the time sequence report meeting the preset time sequence requirement as a target time sequence report;
a selection submodule for selecting a compiling strategy corresponding to the target time sequence report from the target strategy set;
and the strategy determination submodule is used for taking the compiling strategy corresponding to the target timing report as the target compiling strategy.
Optionally, the apparatus may further include:
the second judging module is used for judging whether the recompiled digital logic circuit meets the preset time sequence requirement or not;
the compiling module 306 is further configured to recompile the recompiled digital logic circuit again when the recompiled digital logic circuit does not satisfy the predetermined timing requirement until the recompiled digital logic circuit satisfies the predetermined timing requirement.
Optionally, the apparatus may further include:
the strategy operation module is used for operating a plurality of compiling strategies in a corresponding strategy set in parallel according to a preset circuit code for each compiling step, wherein the preset circuit code is used for generating a preset digital logic circuit;
the third acquisition module is used for acquiring a time sequence report generated by each compiling strategy according to the preset circuit code;
a preset policy determining module 305, configured to use the compiling policy corresponding to the timing report meeting the preset timing requirement as a preset compiling policy.
Optionally, the compiling module 306 may include:
a judging submodule for judging whether the target compiling step is the last compiling step of the digital logic circuit;
a first compiling submodule, configured to recompile the digital logic circuit according to the target compiling policy when the target compiling step is a last compiling step of the digital logic circuit;
and a second compiling submodule, configured to recompile the digital logic circuit according to the target compiling policy and preset compiling policies corresponding to compiling steps after the target compiling step, when the target compiling step is not the last compiling step of the digital logic circuit.
Optionally, the apparatus may further include:
and the updating module is used for updating the preset compiling strategy corresponding to the target compiling step according to the target compiling strategy.
Optionally, the apparatus may further include:
the third judging module is used for judging whether the digital logic circuit meets the requirement of the preset time sequence;
the first obtaining module 301 includes:
and the obtaining submodule is used for obtaining the compiling step of the digital logic circuit when the digital logic circuit does not meet the preset time sequence requirement.
The digital logic circuit compiling device provided by the embodiment of the invention can realize each process realized by the digital logic circuit compiling device in the method embodiments of fig. 1 to fig. 2, and is not described again to avoid repetition.
In summary, in the digital logic circuit compiling apparatus provided in the embodiments of the present invention, the compiling steps of the digital logic circuit are obtained, and the compiling steps are checked according to the reverse order opposite to the order of the compiling steps, and whether the timing reports corresponding to the compiling steps meet the preset timing requirement is detected one by one, so that the compiling steps that do not meet the preset timing requirement are determined as target compiling steps, and the compiling strategies in the target strategy set corresponding to the target compiling steps are run in parallel, so as to determine the target compiling strategies, and finally the digital logic circuit is recompiled according to the target compiling strategies. Because the data output by the compiling step before the target compiling step can be used in the process of recompiling the digital logic circuit by adopting the target compiling strategy, the time spent by the client for recompiling the digital logic circuit can be reduced, and the efficiency of recompiling the digital logic circuit can be improved.
Preferably, an embodiment of the present invention further provides a digital logic circuit compiling apparatus, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, where the computer program, when executed by the processor, implements each process of the digital logic circuit compiling method embodiment, and can achieve the same technical effect, and details are not described here to avoid repetition.
The embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process of the digital logic circuit compiling method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A method for compiling digital logic, the method comprising:
acquiring compiling steps of the digital logic circuit, wherein each compiling step corresponds to a strategy set, each strategy set comprises at least one compiling strategy, and each compiling strategy has a corresponding time sequence report;
adopting a sequence reverse to the compiling sequence of the digital logic circuit to judge whether the time sequence report corresponding to each compiling step meets the preset time sequence requirement one by one;
when any one time sequence report does not meet the preset time sequence requirement, determining the compiling step corresponding to the time sequence report as a target compiling step;
acquiring a time sequence report corresponding to each compiling strategy in a target strategy set, wherein the target strategy set is a strategy set corresponding to the target compiling step;
according to the time sequence report corresponding to each compiling strategy, taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a target compiling strategy;
recompiling the digital logic circuit according to the target compilation strategy;
wherein said recompiling said digital logic circuit in accordance with said target compilation strategy comprises: judging whether the target compiling step is the last compiling step of the digital logic circuit or not;
when the target compiling step is the last compiling step of the digital logic circuit, recompiling the digital logic circuit according to the target compiling strategy;
when the target compiling step is not the last compiling step of the digital logic circuit, recompiling the digital logic circuit according to the target compiling strategy and preset compiling strategies corresponding to all compiling steps after the target compiling step.
2. The method according to claim 1, wherein the using the coding strategy corresponding to the timing report satisfying the predetermined timing requirement as a target coding strategy comprises:
traversing the time sequence report corresponding to each compiling strategy, and taking the time sequence report meeting the preset time sequence requirement as a target time sequence report;
selecting a compiling strategy corresponding to the target time sequence report from the target strategy set;
and taking the compiling strategy corresponding to the target timing report as the target compiling strategy.
3. The method of claim 1, wherein after said recompiling said digital logic circuit in accordance with said target compilation strategy, said method further comprises:
judging whether the recompiled digital logic circuit meets the preset time sequence requirement or not;
when the recompiled digital logic circuit does not meet the preset time sequence requirement, recompiling the digital logic circuit again until the recompiled digital logic circuit meets the preset time sequence requirement.
4. The method of claim 1, wherein prior to said obtaining said compiled digital logic circuit step, said method further comprises:
for each compiling step, parallelly operating a plurality of compiling strategies in a corresponding strategy set according to preset circuit codes, wherein the preset circuit codes are used for generating a preset digital logic circuit;
acquiring a time sequence report generated by each compiling strategy according to the preset circuit codes;
and taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a preset compiling strategy.
5. The method according to claim 4, wherein after the coding strategy corresponding to the timing report satisfying the predetermined timing requirement is used as a target coding strategy, the method further comprises:
and updating the preset compiling strategy corresponding to the target compiling step according to the target compiling strategy.
6. The method of any of claims 1 to 5, wherein prior to said step of obtaining said compilation of digital logic circuits, said method further comprises:
judging whether the digital logic circuit meets the preset time sequence requirement or not;
the compiling step of obtaining the digital logic circuit includes:
and when the digital logic circuit does not meet the preset time sequence requirement, acquiring a compiling step of the digital logic circuit.
7. A digital logic circuit compiling apparatus, wherein the digital logic circuit compiling apparatus comprises:
the first obtaining module is used for obtaining compiling steps of the digital logic circuit, wherein each compiling step corresponds to a strategy set, each strategy set comprises at least one compiling strategy, and each compiling strategy has a corresponding time sequence report;
the first judgment module is used for judging whether the time sequence reports corresponding to the compiling steps meet the preset time sequence requirements one by one in a sequence reverse to the compiling sequence of the digital logic circuit;
a step determining module, configured to determine, when any one of the timing reports does not meet the preset timing requirement, a compiling step corresponding to the timing report as a target compiling step;
a second obtaining module, configured to obtain a timing report corresponding to each compiling policy in a target policy set, where the target policy set is a policy set corresponding to the target compiling step;
the strategy determining module is used for taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a target compiling strategy according to the time sequence report corresponding to each compiling strategy;
a compiling module for recompiling the digital logic circuit according to the target compiling strategy;
wherein the compiling module comprises:
a judging submodule for judging whether the target compiling step is the last compiling step of the digital logic circuit;
a first compiling submodule, configured to recompile the digital logic circuit according to the target compiling strategy when the target compiling step is a last compiling step of the digital logic circuit;
and the second compiling submodule is used for recompiling the digital logic circuit according to the target compiling strategy and preset compiling strategies corresponding to all compiling steps after the target compiling step when the target compiling step is not the last compiling step of the digital logic circuit.
8. The apparatus of claim 7, wherein the policy determination module comprises:
the report determining submodule is used for traversing the time sequence report corresponding to each compiling strategy and taking the time sequence report meeting the preset time sequence requirement as a target time sequence report;
the selection submodule is used for selecting a compiling strategy corresponding to the target time sequence report from the target strategy set;
and the strategy determination submodule is used for taking the compiling strategy corresponding to the target timing report as the target compiling strategy.
9. The apparatus of claim 7, further comprising:
the second judging module is used for judging whether the recompiled digital logic circuit meets the preset time sequence requirement or not;
the compiling module is further configured to recompile the digital logic circuit again when the recompiled digital logic circuit does not meet the preset timing requirement until the recompiled digital logic circuit meets the preset timing requirement.
10. The apparatus of claim 7, further comprising:
the strategy operation module is used for operating a plurality of compiling strategies in a corresponding strategy set in parallel according to preset circuit codes for each compiling step, wherein the preset circuit codes are used for generating a preset digital logic circuit;
the third acquisition module is used for acquiring a time sequence report generated by each compiling strategy according to the preset circuit codes;
and the preset strategy determining module is used for taking the compiling strategy corresponding to the time sequence report meeting the preset time sequence requirement as a preset compiling strategy.
11. The apparatus of claim 10, further comprising:
and the updating module is used for updating the preset compiling strategy corresponding to the target compiling step according to the target compiling strategy.
12. The apparatus of any of claims 7 to 11, further comprising:
the third judging module is used for judging whether the digital logic circuit meets the requirement of the preset time sequence;
the first obtaining module comprises:
and the obtaining submodule is used for obtaining the compiling step of the digital logic circuit when the digital logic circuit does not meet the preset time sequence requirement.
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