CN110532577A - Digital Logical Circuits Compilation Method and device - Google Patents
Digital Logical Circuits Compilation Method and device Download PDFInfo
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Abstract
The present invention provides a kind of Digital Logical Circuits Compilation Method and devices, it is related to field of circuit technology, this method comprises: obtaining the compilation step of Digital Logical Circuits, using the reverse sequence of the compiling sequence with Digital Logical Circuits, judge whether the corresponding sequential address of each compilation step meets default timing requirements one by one, compilation step corresponding to the sequential address for being unsatisfactory for default timing requirements is determined as Target compiling step, according to the corresponding sequential address of each compilation strategy, compilation strategy corresponding to the sequential address of default timing requirements will be met, as Target compiling strategy, Digital Logical Circuits is recompilated according to Target compiling strategy.Due to during recompilating Digital Logical Circuits using Target compiling strategy, the data of the compilation step output before Target compiling step can be used, client can be reduced and recompilate Digital Logical Circuits the time it takes, so as to improve the efficiency for recompilating Digital Logical Circuits.
Description
Technical field
The present embodiments relate to field of circuit technology more particularly to a kind of Digital Logical Circuits Compilation Method and devices.
Background technique
With the continuous development of Digital Logical Circuits, the scale of Digital Logical Circuits is also constantly expanding, and user is designing
During Digital Logical Circuits, it can compile to obtain large-scale Digital Logical Circuits by way of software and hardware combining.
In the related technology, the circuit code for being used to generate Digital Logical Circuits that the available user of client writes, and
According to the circuit code according to compilation strategy corresponding to pre-set each compilation step, execute synthesis, conversion, layout,
Multiple compilation steps such as optimization and wiring, finally compiling obtains large scale digital logic circuit.
But user after having executed each compilation step when can only know whether the Digital Logical Circuits of compiling meets
Sequence requirement, when Digital Logical Circuits is unsatisfactory for timing requirements, needs to reset compilation strategy and is compiled, and causes compiling number
Word logic circuit the time it takes is longer, the lower problem of efficiency.
Summary of the invention
The embodiment of the present invention provides a kind of Digital Logical Circuits Compilation Method and device, with solve when Digital Logical Circuits not
When meeting timing requirements, recompility Digital Logical Circuits the time it takes is longer, the lower problem of efficiency.
In order to solve the above-mentioned technical problem, the present invention is implemented as follows: a kind of Digital Logical Circuits Compilation Method, described
Method includes:
Obtain the compilation step of the Digital Logical Circuits, wherein each compilation step is corresponding with set of strategies, Mei Gece
Slightly collection includes at least one compilation strategy, and each compilation strategy has corresponding sequential address；
Using the reverse sequence of the compiling sequence with the Digital Logical Circuits, judge that each compilation step is corresponding one by one
Whether sequential address meets default timing requirements；
When any one sequential address is unsatisfactory for the default timing requirements, by compiling corresponding to the sequential address
Step is determined as Target compiling step；
It obtains target strategy and concentrates the corresponding sequential address of each compilation strategy, the target strategy collection is target volume
Translate the corresponding set of strategies of step；
According to the corresponding sequential address of each compilation strategy, will meet corresponding to the sequential address of the default timing requirements
Compilation strategy, as Target compiling strategy；
The Digital Logical Circuits is recompilated according to the Target compiling strategy.
Optionally, described to meet compilation strategy corresponding to the sequential address of the default timing requirements, as target
Compilation strategy, comprising:
The corresponding sequential address of each compilation strategy is traversed, the sequential address of the default timing requirements will be met as mesh
Mark sequential address；
It is concentrated from the target strategy and chooses compilation strategy corresponding with Goal time order report；
Will compilation strategy corresponding with Goal time order report as the Target compiling strategy.
Optionally, after the Digital Logical Circuits according to Target compiling strategy recompility, the side
Method further include:
Judge whether the Digital Logical Circuits of the recompility meets the default timing requirements；
When the Digital Logical Circuits of the recompility is unsatisfactory for the default timing requirements, number is recompilated again
Logic circuit, until the Digital Logical Circuits recompilated meets the default timing requirements.
Optionally, before the compilation step for obtaining the Digital Logical Circuits, the method also includes:
For each compilation step, multiple compilation strategies of corresponding strategy concentration are run parallel according to prewired circuit code,
The prewired circuit code is for generating preset Digital Logical Circuits；
Each compilation strategy is obtained according to the sequential address of the prewired circuit code building；
Using compilation strategy corresponding to the sequential address for meeting the default timing requirements as preset compilation strategy.
It is optionally, described to recompilate the Digital Logical Circuits according to the Target compiling strategy, comprising:
Judge the Target compiling step whether be the Digital Logical Circuits the last one compilation step；
When the Target compiling step is the last one compilation step of the Digital Logical Circuits, according to the target
Compilation strategy recompilates the Digital Logical Circuits；
When the Target compiling step is not the last one compilation step of the Digital Logical Circuits, according to the mesh
Compilation strategy is marked, and preset compilation strategy corresponding to each compilation step after the Target compiling step, weight
The newly compiled Digital Logical Circuits.
Optionally, compilation strategy corresponding to the sequential address of the default timing requirements will be met described, as mesh
After marking compilation strategy, the method also includes:
According to the Target compiling strategy, the corresponding preset compilation strategy of the Target compiling step is updated.
Optionally, before the compilation step for obtaining the Digital Logical Circuits, the method also includes:
Judge whether the Digital Logical Circuits meets the default timing requirements；
The compilation step for obtaining the Digital Logical Circuits, comprising:
When the Digital Logical Circuits is unsatisfactory for the default timing requirements, the compiling of the Digital Logical Circuits is obtained
Step.
On the other hand, the embodiment of the invention also provides a kind of Digital Logical Circuits compilation device, the Digital Logic electricity
Road compilation device includes:
First obtains module, for obtaining the compilation step of the Digital Logical Circuits, wherein each compilation step is right
There should be set of strategies, each set of strategies includes at least one compilation strategy, and each compilation strategy has corresponding sequential address；
First judgment module judges one by one for the sequence reverse using the compiling sequence with the Digital Logical Circuits
Whether the corresponding sequential address of each compilation step meets default timing requirements；
Step determining module, for when any one sequential address is unsatisfactory for the default timing requirements, when will be described
The corresponding compilation step of sequence report is determined as Target compiling step；
Second obtains module, concentrates the corresponding sequential address of each compilation strategy, the target for obtaining target strategy
Set of strategies is the corresponding set of strategies of the Target compiling step；
Tactful determining module, for that will meet the default timing and want according to the corresponding sequential address of each compilation strategy
Compilation strategy corresponding to the sequential address asked, as Target compiling strategy；
Collector, for recompilating the Digital Logical Circuits according to the Target compiling strategy.
Optionally, the tactful determining module includes:
It reports and determines that submodule will meet the default timing for traversing the corresponding sequential address of each compilation strategy
It is required that sequential address as Goal time order report；
Submodule is chosen, chooses compiling plan corresponding with Goal time order report for concentrating from the target strategy
Slightly；
Strategy determines submodule, for compiling compilation strategy corresponding with Goal time order report as the target
Translate strategy.
Optionally, described device further include:
Second judgment module is wanted for judging whether the Digital Logical Circuits of the recompility meets the default timing
It asks；
The collector is also used to be unsatisfactory for the default timing requirements when the Digital Logical Circuits of the recompility
When, Digital Logical Circuits is recompilated again, until the Digital Logical Circuits recompilated meets the default timing requirements.
Optionally, described device further include:
Strategy operation module, for running corresponding strategy collection parallel according to prewired circuit code for each compilation step
In multiple compilation strategies, the prewired circuit code is for generating preset Digital Logical Circuits；
Third obtains module, for obtaining each compilation strategy according to the sequential address of the prewired circuit code building；
Preset strategy determining module, for compilation strategy corresponding to the sequential address of the default timing requirements will to be met
As preset compilation strategy.
Optionally, the collector includes:
Judging submodule, for judge the Target compiling step whether be the Digital Logical Circuits the last one volume
Translate step；
First compiling submodule, for when the last one compiling that the Target compiling step is the Digital Logical Circuits
When step, the Digital Logical Circuits is recompilated according to the Target compiling strategy；
Second compiling submodule, for not being the last one volume of the Digital Logical Circuits when the Target compiling step
When translating step, each compilation step institute according to the Target compiling strategy, and after the Target compiling step is right
The preset compilation strategy answered, recompilates the Digital Logical Circuits.
Optionally, described device further include:
Update module, for according to the Target compiling strategy, preset compiling plan corresponding to the Target compiling step
Slightly it is updated.
Optionally, described device further include:
Third judgment module, for judging whether the Digital Logical Circuits meets the default timing requirements；
Described first, which obtains module, includes:
Acquisition submodule, for obtaining the number when the Digital Logical Circuits is unsatisfactory for the default timing requirements
The compilation step of word logic circuit.
In embodiments of the present invention, by obtain Digital Logical Circuits compilation step, according to the compilation step
Sequentially opposite reverse order is checked, and detects whether the corresponding sequential address of each compilation step meets default timing one by one
It is required that so that the compilation step for being unsatisfactory for default timing requirements is determined as Target compiling step, and operation and target parallel
Each compilation strategy that the corresponding target strategy of compilation step is concentrated, determines Target compiling strategy, finally according to Target compiling plan
Slightly recompilate Digital Logical Circuits.Due to using Target compiling strategy recompilate Digital Logical Circuits during, can
With the data for using the compilation step before Target compiling step to export, client can be reduced and recompilate Digital Logical Circuits
The time it takes, so as to improve the efficiency for recompilating Digital Logical Circuits.
Detailed description of the invention
Fig. 1 is a kind of step flow chart of Digital Logical Circuits Compilation Method provided in an embodiment of the present invention；
Fig. 2 is a kind of step flow chart of Digital Logical Circuits Compilation Method provided in an embodiment of the present invention；
Fig. 3 is a kind of structural block diagram of Digital Logical Circuits compilation device provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
Referring to Fig.1, a kind of step flow chart of Digital Logical Circuits Compilation Method of the embodiment of the present invention is shown, specifically
It may include steps of:
Step 101, the compilation step of Digital Logical Circuits is obtained.
During encoded number logic circuit, it can pass through using the circuit code that user provides as input data
Each compilation step is compiled processing, obtain processing compiling after data, finally can according to the data after compiling generate with
The corresponding Digital Logical Circuits of circuit code.
Wherein, the circuit code is for generating Digital Logical Circuits.In addition, the data of each compilation step output can be made
For the input data of next compilation step.
It before generating Digital Logical Circuits, needs to be judged according to the data after compiling, after determining according to the compiling
Data generate Digital Logical Circuits whether meet pre-set default timing requirements, if Digital Logical Circuits is unsatisfactory for
The default timing requirements, then need to re-start Digital Logical Circuits compiling, so as to can satisfy this pre- for Digital Logical Circuits
If timing requirements.
Digital Logical Circuits the time it takes is recompilated in order to reduce, client needs first to obtain Digital Logical Circuits
Compilation step, in the next steps, to be detected according to the sequence of the compilation step, with determination be unsatisfactory for presetting
Compilation step corresponding to the sequential address of timing requirements.
Wherein, each compilation step is corresponding with set of strategies, and each set of strategies includes at least one compilation strategy, Mei Gebian
Translating strategy has corresponding sequential address, and client can be compiled Digital Logical Circuits by corresponding compilation strategy,
And according to each sequential address determine corresponding compilation strategy belonging to compilation step whether meet default timing requirements.
Therefore, if desired Digital Logical Circuits is recompilated, then can obtains and compile with data according to the pre-stored data
Translate each compilation step of Digital Logical Circuits.For example, then may be used when determining that Digital Logical Circuits is unsatisfactory for default timing requirements
To obtain each volumes such as " synthesis ", " conversion ", " layout ", " optimization " and " wiring " according to the sequence of encoded number logic circuit
Translate step.
Step 102, the sequence reverse using the compiling sequence with Digital Logical Circuits, judges each compilation step pair one by one
Whether the sequential address answered meets default timing requirements.
Obtain encoded number logic circuit compilation step after, can according to the reverse order opposite with compiling sequence into
Row investigation confirms sequential address corresponding to the compilation strategy of each compilation step use, if satisfaction is set in advance from back to front
The default timing requirements set.
Specifically, client can be determining opposite with compiling sequence according to the compilation step of encoded number logic circuit
Reverse order it is default to judge whether sequential address corresponding to each compilation step meets one by one according still further to the reverse order
Timing requirements.If the corresponding sequential address of some compilation step meets default timing requirements, illustrate that the compilation step is adopted
Compilation strategy is optimal compilation strategy, is modified without the compilation strategy to the compilation step, then client can be after
It is continuous to judge whether the corresponding sequential address of next compilation step meets default timing requirements, until determining some compilation step pair
The sequential address answered is unsatisfactory for default timing requirements.
For example, the citing with step 101 is corresponding, if the sequence of encoded number logic circuit are as follows: " synthesis " " turns
Change ", " layout ", " optimization " and " wiring ", then the reverse order opposite with compiling sequence be then are as follows: " wiring ", " optimization ", " cloth
Office ", " conversion " and " synthesis ", if the corresponding sequential address of compilation step " optimization " meets default timing requirements, client
It can continue to judge whether sequential address corresponding to compilation step " layout " meets default timing requirements.
Step 103, when any one sequential address is unsatisfactory for default timing requirements, by volume corresponding to the sequential address
It translates step and is determined as Target compiling step.
After being judged according to reverse order, if detecting that any one compilation step corresponds to sequential address and is unsatisfactory for
When default timing requirements, the compilation strategy for illustrating that the compilation step uses may not be optimal compilation strategy, need to the compiling
Step use compilation strategy replaced, then the compilation step can be determined as Target compiling step by client, so as to
The compilation strategy used in subsequent step to the Target compiling step is updated.
Step 104, it obtains target strategy and concentrates the corresponding sequential address of each compilation strategy.
Wherein, which integrates as the corresponding set of strategies of Target compiling step.
After determining Target compiling strategy, the available target strategy collection corresponding with Target compiling strategy of client, and
Multiple compilation strategies that target strategy is concentrated are run parallel, the circuit generation that each compilation strategy is provided according to user
Code generates corresponding sequential address.
Wherein, which edited by user, for generating the Digital Logical Circuits for meeting user's requirement.
Specifically, client can concentrate the compilation strategy for choosing preset number from target strategy, what parallel operation was chosen
The compilation strategy of preset number, the sequential address corresponding to available each compilation strategy after operation, and again from
Target strategy concentrates the compilation strategy for choosing preset number, and runs the compilation strategy of this selection parallel, obtains each volume
The corresponding sequential address of strategy is translated, until obtaining the sequential address that target strategy concentrates each compilation strategy.
Step 105, according to the corresponding sequential address of each compilation strategy, the sequential address institute of default timing requirements will be met
Corresponding compilation strategy, as Target compiling strategy.
After obtaining target strategy and concentrating the corresponding sequential address of each compilation strategy, client can be by each timing
Report is matched with default timing requirements, and lookup obtains the sequential address to match with default timing requirements, can finally be incited somebody to action
Compilation strategy corresponding to the wrong reasons is as Target compiling strategy.
It should be noted that the embodiment of the present invention can also determine Target compiling strategy using other modes, the present invention is real
Example is applied not limit this.
For example, at step 104, client can run the compilation strategy for finishing preset number parallel, and obtain with respectively
The corresponding sequential address of a compilation strategy, then can match obtained sequential address with default timing requirements, determine
It whether include the sequential address for meeting default timing requirements in obtained sequential address.When including in obtained multiple sequential addresses
When meeting the sequential address of default timing requirements, then the corresponding compilation strategy of the sequential address can be determined as Target compiling plan
Slightly, and compilation strategy out of service, but if do not include in obtained multiple sequential addresses meet default timing requirements when
When sequence is reported, then need to run multiple compilation strategies parallel again, and matched according to the sequential address obtained again, until
Obtain with the matched sequential address of default timing requirements, so that it is determined that Target compiling strategy.
Step 106, Digital Logical Circuits is recompilated according to Target compiling strategy.
After determining Target compiling strategy, then client can according to the Target compiling strategy in Target compiling step with
And pre-set preset compilation strategy in other steps, the circuit code of user is compiled again, so as to obtain
Meet the Digital Logical Circuits of default timing requirements.
Specifically, client can determine the position where Target compiling step according to the compilation step of Digital Logical Circuits
It sets, and determines compilation step adjacent with Target compiling step and before Target compiling step, then available compiling step
Suddenly the data exported, and the data that the compilation step is exported are as the input data of Target compiling step, thus using target
Compilation strategy compiles the input data again, finally obtains the Digital Logical Circuits of recompility.
Further, if client can compile target there is also other compilation steps after Target compiling step
The data for translating step output as the input data of the compilation step after Target compiling step, and use other compilation steps
Preset compilation strategy be compiled, obtain Digital Logical Circuits.
But if other compilation steps are not present after Target compiling step, that is to say, Target compiling step is number
The last one compilation step of logic circuit, the then number that the data that can be exported according to Target compiling step generate after compiling are patrolled
Collect circuit.
In conclusion Digital Logical Circuits Compilation Method provided in an embodiment of the present invention, by obtaining Digital Logic electricity
The compilation step on road, is checked according to the reverse order opposite with the sequence of the compilation step, detects each compiling step one by one
Whether rapid corresponding sequential address meets default timing requirements, so that the compilation step for being unsatisfactory for default timing requirements is determined as
Target compiling step, and each compilation strategy that target strategy corresponding with Target compiling step is concentrated is run parallel, it determines
Target compiling strategy finally recompilates Digital Logical Circuits according to Target compiling strategy.Due to using Target compiling strategy
During recompilating Digital Logical Circuits, the data of the compilation step output before Target compiling step, energy can be used
It enough reduces client and recompilates Digital Logical Circuits the time it takes, so as to improve recompility Digital Logical Circuits
Efficiency.
Referring to Fig. 2, a kind of step flow chart of Digital Logical Circuits Compilation Method of the embodiment of the present invention is shown, specifically
It may include steps of:
Step 201, the corresponding preset compilation strategy of each compilation step is obtained.
Client is during encoded number logic circuit, the circuit that can be provided by multiple compilation steps user
Code is compiled processing, finally obtains Digital Logical Circuits.And each compilation step can correspond to a set of strategies, Mei Gece
Slightly collection includes multiple compilation strategies, therefore, before being compiled to Digital Logical Circuits, it is thus necessary to determine that each compilation step institute
Corresponding preset compilation strategy obtains Digital Logic electricity in the next steps, to be compiled according to the preset compilation strategy
Road.
Optionally, for each compilation step, the more of corresponding strategy concentration can be run parallel according to prewired circuit code
A compilation strategy obtains each compilation strategy according to the sequential address of prewired circuit code building, will meet default timing requirements
Sequential address corresponding to compilation strategy as preset compilation strategy.
Wherein, the prewired circuit code is for generating preset Digital Logical Circuits.
The process class that Target compiling strategy is obtained in the process and step 105 of preset compilation strategy is obtained in this step 201
Seemingly, details are not described herein.
Step 202, judge whether Digital Logical Circuits meets default timing requirements.
Client is carried out in the circuit code provided according to user according to the corresponding preset compilation strategy of each compilation step
Compiling, before the data exported according to each compilation step generate Digital Logical Circuits, it is also necessary to according to the last one compiling
The data of step output are judged, determine whether Digital Logical Circuits meets default timing requirements.
When the Digital Logical Circuits that determination will generate meets default timing requirements, then can be exported according to compilation step
Data generate corresponding Digital Logical Circuits.But it if Digital Logical Circuits is unsatisfactory for default timing requirements, needs to hold
Row subsequent step recompilates Digital Logical Circuits, so that Digital Logical Circuits meets default timing requirements.
Step 203, when Digital Logical Circuits is unsatisfactory for default timing requirements, the compiling step of Digital Logical Circuits is obtained
Suddenly.
Step 204, the sequence reverse using the compiling sequence with Digital Logical Circuits, judges each compilation step pair one by one
Whether the sequential address answered meets default timing requirements.
Step 205, when any one sequential address is unsatisfactory for default timing requirements, by compiling corresponding to sequential address
Step is determined as Target compiling step.
Step 206, it obtains target strategy and concentrates the corresponding sequential address of each compilation strategy.
Since the process of step 203 to step 206 and the process of step 101 to step 104 are similar, details are not described herein.
Step 207, according to the corresponding sequential address of each compilation strategy, the sequential address institute of default timing requirements will be met
Corresponding compilation strategy, as Target compiling strategy.
Client after obtaining the corresponding sequential address of each compilation strategy, can by each sequential address and it is default when
Sequence requires to be matched, and the sequential address for meeting default timing requirements is determined, to choose corresponding compilation strategy as target
Compilation strategy.
Optionally, client can traverse the corresponding sequential address of each compilation strategy, will meet default timing requirements
Sequential address is reported as Goal time order, then is concentrated from target strategy and chosen compilation strategy corresponding with Goal time order report,
Will compilation strategy corresponding with Goal time order report as Target compiling strategy.
Specifically, client, can be by the corresponding sequential address of each compilation strategy after obtaining each sequential address
It is compared with default timing requirements, judges whether each sequential address meets default timing requirements.When some sequential address is full
When foot presets timing requirements, it can be reported the sequential address as Goal time order, and concentrate and choose and the mesh from target strategy
The corresponding compilation strategy of sequential address is marked, it finally can be using the compilation strategy of selection as Target compiling strategy.
Step 208, according to Target compiling strategy, preset compilation strategy corresponding to Target compiling step is updated.
Since each compilation step corresponds to a preset compilation strategy, but if some preset compilation strategy is corresponding
When sequential address is unsatisfactory for default timing requirements, illustrate that the preset compilation strategy is not to compile the optimal plan of current circuit code
Slightly, it needs to replace the preset compilation strategy.
Therefore, preset compilation strategy corresponding to Target compiling step can be replaced with Target compiling strategy by client,
It that is to say, using Target compiling strategy as the preset compilation strategy of Target compiling step, realize the update to preset compilation strategy.
Step 209, Digital Logical Circuits is recompilated according to Target compiling strategy.
During encoded number logic circuit, Target compiling step may be any one in multiple compilation steps
Compilation step, then Target compiling step may be the last one compilation step in compilation process, it is also possible to other compiling steps
Suddenly.
When Target compiling step is not the last one compilation step in compilation process, then also need to be compiled according to other
The corresponding preset compilation strategy of step is compiled.Therefore, Digital Logical Circuits is being carried out again according to Target compiling strategy
It during compiling, needs according to the different location where Target compiling step, number is recompilated using different compiling modes
Word logic circuit.
Optionally, client may determine that Target compiling step whether be Digital Logical Circuits the last one compiling step
Suddenly, it when the Target compiling step is the last one compilation step of Digital Logical Circuits, is compiled again according to Target compiling strategy
Translate Digital Logical Circuits；It, then can be with but when Target compiling step is not the last one compilation step of Digital Logical Circuits
Preset compilation strategy corresponding to each compilation step according to Target compiling strategy, and after Target compiling step,
Recompilate Digital Logical Circuits.
Specifically, when Target compiling step is the last one compilation step, then before can determining Target compiling step
One compilation step, and the data of compilation step output are obtained, then using the data as the input data of Target compiling step,
The input data is compiled by Target compiling strategy, the data of Target compiling step output are obtained, so as in subsequent step
In rapid, determine whether the Digital Logical Circuits recompilated meets default timing requirements according to the data of the output.
Correspondingly, also needing when Target compiling step is not the last one compilation step by compilation step before
Input data of the data of output as Target compiling step, then the data that Target compiling step is exported are walked as subsequent compilation
Rapid input data finally obtains so that subsequent compilation step is compiled using preset compilation strategy for generating number
The data of logic circuit.
Step 210, when the Digital Logical Circuits of recompility is unsatisfactory for default timing requirements, number is recompilated again
Logic circuit, until the Digital Logical Circuits recompilated meets default timing requirements.
Client is being recompilated for that can divide the data after generating the data of Digital Logical Circuits
Analysis judgement, determines whether meet default timing requirements according to the Digital Logical Circuits that the data generate.
When determining that the Digital Logical Circuits recompilated still not satisfies default timing requirements, then step can be executed again
Rapid 203, to step 210, that is to say and recompilate again to Digital Logical Circuits, and judge the Digital Logic recompilated
Whether circuit meets default timing requirements, until the Digital Logical Circuits recompilated meets default timing requirements.
Optionally, client may determine that whether the Digital Logical Circuits of recompility meets default timing requirements, when weight
When newly compiled Digital Logical Circuits is unsatisfactory for default timing requirements, Digital Logical Circuits is recompilated again, until compiling again
The Digital Logical Circuits translated meets default timing requirements.
The above process is similar with the process of step 203 to step 210, and details are not described herein.
It should be noted that when client recompilates again, it can be according to opposite with encoded number logic circuit
Sequentially, since it is adjacent with Target compiling step and be located at Target compiling step before compilation step detect, judge each volume
It translates step and corresponds to whether sequential address meets default timing requirements, so that it is determined that new Target compiling step and Target compiling plan
Slightly.
For example, the sequence of encoded number logic circuit are as follows: " synthesis ", " conversion ", " layout ", " optimization " and " wiring ", with
The opposite reverse order of compiling sequence is then are as follows: and " wiring ", " optimization ", " layout ", " conversion " and " synthesis ", if the last time is again
Compilation step " layout " is that Target compiling step can be from compiling then during this recompility during compiling
Step " conversion " starts to detect, so that it is determined that the Target compiling step of this recompility.
In conclusion Digital Logical Circuits Compilation Method provided in an embodiment of the present invention, by obtaining Digital Logic electricity
The compilation step on road, is checked according to the reverse order opposite with the sequence of the compilation step, detects each compiling step one by one
Whether rapid corresponding sequential address meets default timing requirements, so that the compilation step for being unsatisfactory for default timing requirements is determined as
Target compiling step, and each compilation strategy that target strategy corresponding with Target compiling step is concentrated is run parallel, it determines
Target compiling strategy finally recompilates Digital Logical Circuits according to Target compiling strategy.Due to using Target compiling strategy
During recompilating Digital Logical Circuits, the data of the compilation step output before Target compiling step, energy can be used
It enough reduces client and recompilates Digital Logical Circuits the time it takes, so as to improve recompility Digital Logical Circuits
Efficiency.
Referring to Fig. 3, a kind of structural block diagram of Digital Logical Circuits compilation device of the embodiment of the present invention is shown, specifically may be used
To include:
First obtains module 301, for obtaining the compilation step of the Digital Logical Circuits, wherein each compilation step is equal
It is corresponding with set of strategies, each set of strategies includes at least one compilation strategy, and each compilation strategy has corresponding sequential address；
First judgment module 302 judges one by one for the sequence reverse using the compiling sequence with the Digital Logical Circuits
Whether the corresponding sequential address of each compilation step meets default timing requirements；
Step determining module 303, for when any one sequential address is unsatisfactory for the default timing requirements, by the timing
The corresponding compilation step of report is determined as Target compiling step；
Second obtains module 304, concentrates the corresponding sequential address of each compilation strategy, the target for obtaining target strategy
Set of strategies is the corresponding set of strategies of Target compiling step；
Tactful determining module 305 is wanted for according to the corresponding sequential address of each compilation strategy, will meet the default timing
Compilation strategy corresponding to the sequential address asked, as Target compiling strategy；
Collector 306, for recompilating the Digital Logical Circuits according to the Target compiling strategy.
Optionally, which may include:
It reports and determines submodule, for traversing the corresponding sequential address of each compilation strategy, the default timing will be met and wanted
The sequential address asked is reported as Goal time order；
Submodule is chosen, chooses compilation strategy corresponding with Goal time order report for concentrating from the target strategy；
Strategy determine submodule, for will compilation strategy corresponding with Goal time order report as the Target compiling plan
Slightly.
Optionally, which can also include:
Second judgment module, for judging whether the Digital Logical Circuits of the recompility meets the default timing requirements；
The collector 306 is also used to when the Digital Logical Circuits of the recompility is unsatisfactory for the default timing requirements,
Digital Logical Circuits is recompilated again, until the Digital Logical Circuits recompilated meets the default timing requirements.
Optionally, which can also include:
Strategy operation module, for running corresponding strategy collection parallel according to prewired circuit code for each compilation step
In multiple compilation strategies, the prewired circuit code is for generating preset Digital Logical Circuits；
Third obtains module, for obtaining each compilation strategy according to the sequential address of the prewired circuit code building；
Preset strategy determining module 305, for compiling plan corresponding to the sequential address of the default timing requirements will to be met
It is slightly preset compilation strategy.
Optionally, which may include:
Judging submodule, for judge the Target compiling step whether be the Digital Logical Circuits the last one compiling step
Suddenly；
First compiling submodule, for when the last one compilation step that the Target compiling step is the Digital Logical Circuits
When, the Digital Logical Circuits is recompilated according to the Target compiling strategy；
Second compiling submodule, for not being the last one compiling step of the Digital Logical Circuits when the Target compiling step
It is preset corresponding to each compilation step according to the Target compiling strategy, and after the Target compiling step when rapid
Compilation strategy recompilates the Digital Logical Circuits.
Optionally, which can also include:
Update module, for according to the Target compiling strategy, to the corresponding preset compilation strategy of the Target compiling step into
Row updates.
Optionally, which can also include:
Third judgment module, for judging whether the Digital Logical Circuits meets the default timing requirements；
This first acquisition module 301 include:
Acquisition submodule, for obtaining the Digital Logic when the Digital Logical Circuits is unsatisfactory for the default timing requirements
The compilation step of circuit.
Digital Logical Circuits compilation device provided in an embodiment of the present invention can be realized in the embodiment of the method for Fig. 1 to Fig. 2
Each process that Digital Logical Circuits compilation device is realized, to avoid repeating, which is not described herein again.
In conclusion Digital Logical Circuits compilation device provided in an embodiment of the present invention, by obtaining Digital Logic electricity
The compilation step on road, is checked according to the reverse order opposite with the sequence of the compilation step, detects each compiling step one by one
Whether rapid corresponding sequential address meets default timing requirements, so that the compilation step for being unsatisfactory for default timing requirements is determined as
Target compiling step, and each compilation strategy that target strategy corresponding with Target compiling step is concentrated is run parallel, it determines
Target compiling strategy finally recompilates Digital Logical Circuits according to Target compiling strategy.Due to using Target compiling strategy
During recompilating Digital Logical Circuits, the data of the compilation step output before Target compiling step, energy can be used
It enough reduces client and recompilates Digital Logical Circuits the time it takes, so as to improve recompility Digital Logical Circuits
Efficiency.
Preferably, the embodiment of the present invention also provides a kind of Digital Logical Circuits compilation device, including processor, memory,
The computer program that can be run on a memory and on the processor is stored, it is real when which is executed by processor
Each process of existing above-mentioned Digital Logical Circuits Compilation Method embodiment, and identical technical effect can be reached, to avoid repeating,
Which is not described herein again.
The embodiment of the present invention also provides a kind of computer readable storage medium, and meter is stored on computer readable storage medium
Calculation machine program, the computer program realize each mistake of above-mentioned Digital Logical Circuits Compilation Method embodiment when being executed by processor
Journey, and identical technical effect can be reached, to avoid repeating, which is not described herein again.Wherein, the computer-readable storage medium
Matter, such as read-only memory (Read-Only Memory, abbreviation ROM), random access memory (Random Access
Memory, abbreviation RAM), magnetic or disk etc..
It should be noted that, in this document, the terms "include", "comprise" or its any other variant are intended to non-row
His property includes, so that the process, method, article or the device that include a series of elements not only include those elements, and
And further include other elements that are not explicitly listed, or further include for this process, method, article or device institute it is intrinsic
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including being somebody's turn to do
There is also other identical elements in the process, method of element, article or device.
Through the above description of the embodiments, those skilled in the art can be understood that above-described embodiment side
Method can be realized by means of software and necessary general hardware platform, naturally it is also possible to by hardware, but in many cases
The former is more preferably embodiment.Based on this understanding, technical solution of the present invention substantially in other words does the prior art
The part contributed out can be embodied in the form of software products, which is stored in a storage medium
In (such as ROM/RAM, magnetic disk, CD), including some instructions are used so that a terminal (can be mobile phone, computer, service
Device, air conditioner or network equipment etc.) execute method described in each embodiment of the present invention.
The embodiment of the present invention is described with above attached drawing, but the invention is not limited to above-mentioned specific
Embodiment, the above mentioned embodiment is only schematical, rather than restrictive, those skilled in the art
Under the inspiration of the present invention, without breaking away from the scope protected by the purposes and claims of the present invention, it can also make very much
Form belongs within protection of the invention.
Claims (14)
1. a kind of Digital Logical Circuits Compilation Method, which is characterized in that the described method includes:
Obtain the compilation step of the Digital Logical Circuits, wherein each compilation step is corresponding with set of strategies, each set of strategies
Including at least one compilation strategy, each compilation strategy has corresponding sequential address；
Using the reverse sequence of the compiling sequence with the Digital Logical Circuits, the corresponding timing of each compilation step is judged one by one
Whether report meets default timing requirements；
When any one sequential address is unsatisfactory for the default timing requirements, by compilation step corresponding to the sequential address
It is determined as Target compiling step；
It obtains target strategy and concentrates the corresponding sequential address of each compilation strategy, the target strategy collection is Target compiling step
Rapid corresponding set of strategies；
According to the corresponding sequential address of each compilation strategy, volume corresponding to the sequential address of the default timing requirements will be met
Strategy is translated, as Target compiling strategy；
The Digital Logical Circuits is recompilated according to the Target compiling strategy.
2. the method according to claim 1, wherein the sequential address that the default timing requirements will be met
Corresponding compilation strategy, as Target compiling strategy, comprising:
The corresponding sequential address of each compilation strategy is traversed, the sequential address of the default timing requirements will be met as when target
Sequence report；
It is concentrated from the target strategy and chooses compilation strategy corresponding with Goal time order report；
Will compilation strategy corresponding with Goal time order report as the Target compiling strategy.
3. the method according to claim 1, wherein recompilating institute according to the Target compiling strategy described
After stating Digital Logical Circuits, the method also includes:
Judge whether the Digital Logical Circuits of the recompility meets the default timing requirements；
When the Digital Logical Circuits of the recompility is unsatisfactory for the default timing requirements, Digital Logic is recompilated again
Circuit, until the Digital Logical Circuits recompilated meets the default timing requirements.
4. the method according to claim 1, wherein in the compilation step for obtaining the Digital Logical Circuits
Before, the method also includes:
For each compilation step, multiple compilation strategies of corresponding strategy concentration are run parallel according to prewired circuit code, it is described
Prewired circuit code is for generating preset Digital Logical Circuits；
Each compilation strategy is obtained according to the sequential address of the prewired circuit code building；
Using compilation strategy corresponding to the sequential address for meeting the default timing requirements as preset compilation strategy.
5. according to the method described in claim 4, it is characterized in that, described according to described in Target compiling strategy recompility
Digital Logical Circuits, comprising:
Judge the Target compiling step whether be the Digital Logical Circuits the last one compilation step；
When the Target compiling step is the last one compilation step of the Digital Logical Circuits, according to the Target compiling
Strategy recompilates the Digital Logical Circuits；
When the Target compiling step is not the last one compilation step of the Digital Logical Circuits, compiled according to the target
Strategy is translated, and preset compilation strategy corresponding to each compilation step after the Target compiling step, compiled again
Translate the Digital Logical Circuits.
6. according to the method described in claim 4, it is characterized in that, in the timing report that will meet the default timing requirements
Corresponding compilation strategy is accused, after Target compiling strategy, the method also includes:
According to the Target compiling strategy, the corresponding preset compilation strategy of the Target compiling step is updated.
7. method according to any one of claims 1 to 6, which is characterized in that in the acquisition Digital Logical Circuits
Before compilation step, the method also includes:
Judge whether the Digital Logical Circuits meets the default timing requirements；
The compilation step for obtaining the Digital Logical Circuits, comprising:
When the Digital Logical Circuits is unsatisfactory for the default timing requirements, the compiling step of the Digital Logical Circuits is obtained
Suddenly.
8. a kind of Digital Logical Circuits compilation device, which is characterized in that the Digital Logical Circuits compilation device includes:
First obtains module, for obtaining the compilation step of the Digital Logical Circuits, wherein each compilation step is corresponding with
Set of strategies, each set of strategies include at least one compilation strategy, and each compilation strategy has corresponding sequential address；
First judgment module judges each one by one for the sequence reverse using the compiling sequence with the Digital Logical Circuits
Whether the corresponding sequential address of compilation step meets default timing requirements；
Step determining module, for when any one sequential address is unsatisfactory for the default timing requirements, by the timing report
It accuses corresponding compilation step and is determined as Target compiling step；
Second obtains module, concentrates the corresponding sequential address of each compilation strategy, the target strategy for obtaining target strategy
Collection is the corresponding set of strategies of the Target compiling step；
Tactful determining module, for the default timing requirements will to be met according to the corresponding sequential address of each compilation strategy
Compilation strategy corresponding to sequential address, as Target compiling strategy；
Collector, for recompilating the Digital Logical Circuits according to the Target compiling strategy.
9. device according to claim 8, which is characterized in that it is described strategy determining module include:
It reports and determines that submodule will meet the default timing requirements for traversing the corresponding sequential address of each compilation strategy
Sequential address as Goal time order report；
Submodule is chosen, chooses compilation strategy corresponding with Goal time order report for concentrating from the target strategy；
Strategy determine submodule, for will compilation strategy corresponding with Goal time order report as the Target compiling plan
Slightly.
10. device according to claim 8, which is characterized in that described device further include:
Second judgment module, for judging whether the Digital Logical Circuits of the recompility meets the default timing requirements；
The collector is also used to when the Digital Logical Circuits of the recompility is unsatisfactory for the default timing requirements, then
Secondary recompility Digital Logical Circuits, until the Digital Logical Circuits recompilated meets the default timing requirements.
11. device according to claim 8, which is characterized in that described device further include:
Strategy operation module, for running corresponding strategy concentration parallel according to prewired circuit code for each compilation step
Multiple compilation strategies, the prewired circuit code is for generating preset Digital Logical Circuits；
Third obtains module, for obtaining each compilation strategy according to the sequential address of the prewired circuit code building；
Preset strategy determining module, for compilation strategy conduct corresponding to the sequential address of the default timing requirements will to be met
Preset compilation strategy.
12. device according to claim 11, which is characterized in that the collector includes:
Judging submodule, for judge the Target compiling step whether be the Digital Logical Circuits the last one compiling step
Suddenly；
First compiling submodule, for when the last one compilation step that the Target compiling step is the Digital Logical Circuits
When, the Digital Logical Circuits is recompilated according to the Target compiling strategy；
Second compiling submodule, for not being the last one compiling step of the Digital Logical Circuits when the Target compiling step
When rapid, corresponding to each compilation step according to the Target compiling strategy, and after the Target compiling step
Preset compilation strategy recompilates the Digital Logical Circuits.
13. device according to claim 11, which is characterized in that described device further include:
Update module, for according to the Target compiling strategy, to the corresponding preset compilation strategy of the Target compiling step into
Row updates.
14. according to any device of claim 8 to 13, which is characterized in that described device further include:
Third judgment module, for judging whether the Digital Logical Circuits meets the default timing requirements；
Described first, which obtains module, includes:
Acquisition submodule, for obtaining the number and patrolling when the Digital Logical Circuits is unsatisfactory for the default timing requirements
Collect the compilation step of circuit.
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