CN110531943B

CN110531943B - USB data bridging method based on FPGA

Info

Publication number: CN110531943B
Application number: CN201910727281.3A
Authority: CN
Inventors: 张飞
Original assignee: Beijing Data Driven Technology Co ltd
Current assignee: Beijing Data Driven Technology Co ltd
Priority date: 2019-08-07
Filing date: 2019-08-07
Publication date: 2023-01-13
Anticipated expiration: 2039-08-07
Also published as: CN110531943A

Abstract

The invention relates to a USB data bridging method based on FPGA, which takes FPGA as the bridging between a cash register and a printer and implements the following steps: s1, establishing a high-speed USB link with a cash register end; s2, establishing a full-speed link with the printer; s3, receiving the configuration that whether the ARM needs to additionally print the printer data of the cash register, if so, entering a step S4, otherwise, entering a step S5; s4, adding printing data, matching byte data of a key field of an insertion position in original data, performing data truncation by adopting a mode of responding NAK to partial data to be separated and transmitted, packaging the added printing data sent by the ARM according to a USB protocol, and sending the additional printing data to a printer, and entering the step S5; and S5, forwarding the printer data, and directly sending the separated printer data to the printer. The invention solves the time requirement between the cash register and the printer, ensures the consistency of the label 0/1 of the data packet, and ensures that the data is more stably and effectively added between the cash register and the printer.

Description

USB data bridging method based on FPGA

Technical Field

The invention relates to a USB data bridging method based on an FPGA (Field-Programmable Gate Array or Field-Programmable logic Gate Array).

Background

The existing USB data bridge uses ARM/single chip and USB PHY control chip respectively. The data acquired by the ARM/single chip microcomputer are analyzed through the USB messages, and the USB underlying protocol cannot be controlled, so that the controllable part of the protocol is greatly reduced.

The technology is generally used for bridging USB data, splicing the USB data and widely used in USB data acquisition and addition. FPGAs are also currently widely used in various industries. The FPGA technology has high flexibility and strong practicability, is closer to bottom hardware and is widely used by people.

At present, the design scheme based on a single chip microcomputer is applied in the industry mostly, the single chip microcomputer receives and transmits data, the single chip microcomputer receives the analyzed USB data through a PHY chip and then forwards the data to a printer after processing, and the USB bottom layer protocol processing is not involved in the processing process. Therefore, the USB data packets are lost during the processing, and the communication between the cash register and the printer is abnormal due to the untimely data forwarding. The reason for this problem is four:

1) Data processing fails to control the USB protocol at the bottom layer, resulting in inaccurate control of data;

2) Due to the limitation of the working frequency of the single chip microcomputer, the processing speed of the single chip microcomputer is low, and the requirement of USB communication cannot be met;

3) The computer end cannot be suspended from sending data under the condition of not influencing the printing of the printer, so that the computer end is often caused to identify the abnormal condition of the printer;

4) The label 0/1 of the data packet at the computer and the printer end before and after the addition is inconsistent, so that the communication between the printer and the computer is abnormal.

Disclosure of Invention

In order to solve the technical problem, the invention provides the USB data bridging method based on the FPGA, and the USB data bridging is arranged between the computer and the printer, so that the phenomena of loss of USB data packets and abnormal communication between the computer and the printer are reduced or avoided.

The technical scheme of the invention is as follows: a USB data bridging method based on FPGA takes FPGA as the bridging between a cash register and a printer, and the FPGA implements the following steps:

s1, establishing communication with a cash register and establishing a high-speed USB link with the cash register;

s2, communication is established with the printer, and full-speed link is established with the printer;

s3, receiving the configuration of whether the ARM needs to additionally print the printer data of the cash register, if so, entering the step S4, otherwise, entering the step S5;

s4, adding printing data, sending data to the received cash register, separating out printer data, judging the head and the tail of the printer data, when byte data matched with a key field of an insertion position is found, intercepting the data by adopting a mode of responding NAK to the separated transmission part data, waiting for ARM to send the printing data needing adding printing, packing the printing data according to a USB protocol after the adding printing data are received, sending the printing data to the printer, waiting for the ARM to send an adding end mark, exiting an adding mode after the adding end mark sent by the ARM is received, and entering the step S5;

s5, the printer data is forwarded, the received cash register is sent data, the printer data is separated, the separated printer data is directly sent to the printer, the communication between the cash register and the printer is kept,

and repeating the steps S3-S5 until the printing is finished.

Preferably, the ARM receives the print data transmitted from the FPGA, monitors the print progress, sets additional printing according to a preset additional printing rule, and transmits additional print settings and corresponding additional print data to the FPGA.

The operating mode of the USB is typically a HUB operating mode.

And the FPGA receives the additionally printed printing data sent by the ARM and then repackages the additionally printed printing data, and the length of the formed USB data packet is preferably 2 times of the maximum length of the USB message.

The FPGA preferably includes:

1) A PHY3340 controller, which is mainly used to obtain data on the USB bus by controlling the PHY 3340;

2) The cash register data control module is mainly used for HUB simulation and separated data transmission control;

3) The additional module control is mainly used for matching the additional head and the additional tail and recombining additional data, and comprises the control of data length, the control of data packet types and the like;

4) The printer data control module is mainly used for forwarding the data sent to the printer by the cash register and the printing data needing to be added to the printer and controlling the data;

5) The SPI controller module is mainly used for communication of control protocols of the ARM and the FPGA, and comprises information such as whether additional printing is needed or not, the size of an additional message, the position of the additional message and the like;

6) The parallel port controller module is mainly used for establishing a data acquisition transmission channel with the ARM and transmitting printing data between the cash register and the printer;

7) And the register control module is mainly used for registering all control information and state information of the FPGA, and data of the module can be read and written through the SPI.

The invention has the beneficial effects that: the invention adopts the FPGA technology, creates a unique USB data control stage mode, solves the time requirement between the cash register and the printer, and simultaneously adopts a special additional printing data length, namely 2 times of the maximum length of the USB message, so as to ensure the consistency of the label number 0/1 of the data packet and ensure that the additional data between the cash register and the printer is more stable and effective.

Drawings

FIG. 1 is a schematic of the work flow of the present invention;

FIG. 2 is a schematic diagram of the architecture of the present invention.

Detailed Description

The starting point of the invention is how to reasonably utilize the USB protocol to achieve the data truncation and addition function, the traditional HOST-DEVICE mode can not effectively control the transmission between the computer and the printer, and the response data of the printer can not be timely fed back to the computer, thereby causing abnormal communication. The invention effectively controls the data flow of the USB from a Split transmission part (Split transmission) based on the USB HUB protocol, thereby achieving the purpose of no abnormal data transmission between a computer and a printer and simultaneously ensuring that the message label 0/1 of the subsequent USB data is consistent with the label of the data before addition.

Referring to fig. 1, the present invention uses an FPGA as a bridge between a cash register and a printer, the FPGA implementing the following steps:

s1, communication is established with a cash register. And a high-speed USB HUB protocol is realized, and a high-speed USB link is established with the cash register end.

And S2, communication is established with the printer. As the HUB communicates with the printer, a full-speed link is established with the printer, i.e., no high-speed handshake is performed with the printer, so the communication rate with the printer is full-speed.

And S3, receiving the configuration of whether the ARM (ARM processor) needs to additionally print the printer data of the cash register. If the addition is needed, the process goes to step S4, otherwise, the process goes to step S5.

And S4, adding printing data. Separating printer data from received cash register end data, judging head and tail of the printer data, when byte data matched with key fields of insertion positions are found, adopting a mode of responding NAK to separated transmission part data to perform data truncation, waiting for ARM to send print data needing additional printing, packing the print data according to a USB protocol after receiving the print data needing additional printing, sending the print data to the printer, waiting for ARM to send an additional finishing mark, exiting the additional mode after receiving the additional finishing mark sent by ARM, and entering the step S5.

And S5, forwarding the printer data. And separating printer data from the received cash register end data, directly sending the separated printer data to the printer, and keeping the communication between the cash register and the printer.

And repeating the steps S3-S5 until the printing is finished.

The invention adopts a common working mode of the USB, namely a HUB working mode.

Referring to fig. 2, the FPGA of the present invention includes:

1) A PHY3340 controller to obtain data on the USB bus by controlling PHY 3340;

2) The cash register data control module is used for HUB simulation, separated data transmission control and the like;

3) The additional module control is used for matching the additional head and the additional tail and recombining additional data, and comprises control over data length, control over data packet types and the like;

4) The printer data control module is used for forwarding the data sent to the printer by the cash register and the printing data needing to be added to the printer and controlling the data;

5) The SPI controller module is used for communication of a control protocol between the ARM and the FPGA, and comprises information such as whether additional printing is needed or not, the size of an additional message, the position of the additional message and the like;

6) The parallel port controller module is used for establishing a collected data transmission channel with the ARM and transmitting the printing data between the cash register and the printer;

7) And the register control module is used for registering all control information and state information of the FPGA, and data of the module can be read and written through the SPI.

The invention has the following three innovative characteristics:

1) The characteristics of the FPGA are fully exerted, the lowest layer of the USB protocol can be controlled, the controllability of the protocol is ensured, and the USB protocol is processed more flexibly;

2) The unique USB protocol processing mode is characterized in that communication is established with the cash register end by simulating a USB HUB protocol, and meanwhile, the USB protocol speed of the cash register end is clamped to be high, and the USB speed of the printer end is full speed, so that the FPGA can control data forwarding in a separated transmission mode, and protocol support is provided for USB data addition;

3) The length of the added data is twice of the maximum packet of the USB message, and the problem that the label numbers of the data packets before and after the addition are not consistent with each other by 0/1 is solved.

The technical means disclosed by the invention can be combined arbitrarily to form a plurality of different technical schemes except for special description and the further limitation that one technical means is another technical means.

Claims

1. A USB data bridging method based on FPGA takes FPGA as the bridging between a cash register and a printer, and the FPGA implements the following steps:

s1, establishing communication with a cash register, and establishing a high-speed USB link with a cash register end;

s2, establishing communication with the printer and establishing a full-speed link with the printer;

s4, adding printing data, separating printer data from received cash register end data, judging the head and tail of the printer data, when byte data matched with key fields of insertion positions are found, performing data truncation in a mode of responding NAK to separated transmission data, waiting for ARM to send the printing data needing to be additionally printed, after the printing data needing to be additionally printed are received, packaging the printing data according to a USB protocol and sending the printing data to a printer, waiting for the ARM to send an addition end mark, exiting an addition mode after the addition end mark sent by the ARM is received, and entering the step S5;

s5, the printer data is forwarded, the received cash register end data is separated out from the printer data, the separated printer data is directly sent to the printer, the communication between the cash register and the printer is kept,

and repeating the steps S3-S5 until the printing is finished.

2. The method of claim 1, wherein the ARM receives print data from the FPGA, monitors the progress of printing, sets additional printing according to a preset additional printing rule, and transmits additional print settings and corresponding additional print data to the FPGA.

3. The method according to claim 1, wherein the USB mode of operation is a HUB mode of operation.

4. The method as claimed in any one of claims 1 to 3, wherein the FPGA receives the additionally printed print data from the ARM and re-encapsulates the additionally printed print data to form a USB data packet with a length 2 times of the maximum length of the USB message.

5. A method according to any of claims 1-3, wherein the FPGA comprises:

1) A PHY3340 controller to obtain data on the USB bus by controlling PHY 3340;

2) The cash register data control module is used for HUB simulation and separated transmission data control;

3) The additional module control is used for matching the additional head and the additional tail and recombining additional data, and comprises the control of data length and the control of data packet type;

5) The SPI controller module is used for communication of control protocols of the ARM and the FPGA and comprises whether additional printing is needed or not, the size of an additional message and additional position information;

7) And the register control module is used for registering all control information and state information of the FPGA, and data of the module is read and written through the SPI.