CN110519012B

CN110519012B - Method and device for coding and decoding polarization code

Info

Publication number: CN110519012B
Application number: CN201910811366.XA
Authority: CN
Inventors: 徐旻子; 樊婷婷; 徐志昆
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2017-03-24
Filing date: 2017-03-24
Publication date: 2022-03-04
Anticipated expiration: 2037-03-24
Also published as: CN108631936A; CN110519012A; CN108631936B

Abstract

A method and apparatus for polar code coding, the method comprising: respectively determining an information bit position, a check bit position and a frozen bit position; generating a check equation of each check bit; wherein: the check equation of each check bit contains the check relation of the previous check bit; generating check bits according to the check equation; generating a polarization code input bit sequence; carrying out polarization code encoding on the polarization code input bit sequence to obtain a polarization code codeword; mapping the polar code words into modulation signals and transmitting the modulation signals through a channel; demodulating the transmitted modulation signal to obtain soft information of bits of the transmitted polarization code word; and processing the soft information of the bits of the polarization code words by adopting a continuous offset list decoding algorithm to obtain a decoding result. By adopting the scheme, the frame error rate of the polar code coding can be reduced.

Description

Method and device for coding and decoding polarization code

Technical Field

The embodiment of the invention relates to the field of communication, in particular to a method and a device for coding and decoding a polarization code.

Background

At present, there are two kinds of Polar Code compiling methods, namely, a Parity-Check Code assisted Polar Code (PC-Polar) compiling method and a Cyclic Redundancy Check assisted Polar Code (CRC-Polar) compiling method.

The flow of the compiling method of the PC-polar comprises the following steps: firstly, an information sequence is placed at a position with larger capacity of a bit channel, then a check bit value is calculated according to the position distribution of the information bit, the information sequence and the check bit are sent to a polar code encoder, when decoding, a Successive Cancellation List (SCL) decoding algorithm assisted by parity check is adopted for decoding, and the decoding of the check bit is obtained by carrying out the same check calculation on the decoded information bit.

The compiling method of the CRC-polar comprises the following flows: firstly, CRC encoding is carried out on an information sequence, then the information sequence and CRC check bits generated by the CRC encoding are sent to a polar code encoder, a CRC-assisted SCL decoding algorithm is adopted during decoding, when code words in a list are selected at last during decoding, all candidate code words are restored to candidate information sequences containing CRC, CRC processing is carried out on all candidate information sequences, and the candidate information sequences which pass through the CRC processing and have the highest reliability are taken as final decoding results.

However, in the conventional polar code encoding method, both encoding methods have a problem of an excessively high frame error rate.

Disclosure of Invention

The problem solved by the embodiment of the invention is how to reduce the frame error rate of polar code coding.

To solve the above problem, an embodiment of the present invention provides a method for polar code coding, where the method includes: respectively determining an information bit position, a check bit position and a frozen bit position; generating a check equation of each check bit; wherein: the check equation of each check bit contains the check relation of the previous check bit; generating check bits according to the check equation; configuring the check bit at the check bit position, acquiring an information source sequence, configuring the information bit in the information source sequence at the information bit position, configuring the frozen bit position, and generating a polarization code input bit sequence; carrying out polarization code encoding on the polarization code input bit sequence to obtain a polarization code codeword; mapping the polar code words into modulation signals and transmitting the modulation signals through a channel; demodulating the transmitted modulation signal to obtain soft information of bits of the transmitted polarization code word; and processing the soft information of the bits of the polarization code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

Optionally, the determining the information bit position, the check bit position, and the frozen bit position respectively includes: acquiring the length K of a required information bit, the length M of a required polarization code and the length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: k; determining a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, wherein n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin are provided; determining the number Fp of the check bit positions; judging the size of the position number n and the number Fp with the minimum row weight dmin, and determining the Fp position with the row weight dmin of the corresponding generating matrix in the third subsequence and the best reliability as the check bit position when n is larger than Fp; determining positions where (Fp + n)/2 rows in the third subsequence are repeated to dmin and positions where (Fp-n)/2 rows in the third subsequence are repeated to 2dmin as the check bit positions when n is less than or equal to Fp; marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

Optionally, the generating a parity equation for each parity bit includes: dividing a sequence formed by the check bits at the check bit positions into s segments; wherein: s is a non-zero natural number; and adding the check bit corresponding to the previous check bit position to the check equation of the check bit corresponding to each check bit position of any section.

Optionally, after adding the parity bit corresponding to the previous parity bit position, the method further includes: setting an information bit position interval as an interval p; wherein the interval p is a prime number; for any check bit, selecting an information bit position which is before the check bit position where the check bit is located and has a check interval with the check bit being a multiple of the interval p; and adding the information bits corresponding to the information bit positions into a check equation of the check bits.

Optionally, after adding the parity bit corresponding to the previous parity bit position, the method further includes: counting information bit positions before an ith check bit position to obtain a sequence Iindex formed by information bits, wherein the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

Optionally, the correspondingly adding the information bits on the position sequence number a to a check equation according to the size relationship between the position sequence number a and the length Isize includes: when the position serial number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iindex is not marked, adding the a-th information bit in the sequence Iindex into a check equation of the i-th check bit, marking, self-adding (q-i +1) the position serial number a, and repeating the judging of the size relationship between the position serial number a and the length Isize; if the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

The embodiment of the invention provides a method for coding and decoding a polar code, which comprises the following steps: respectively determining an information bit position, a check bit position and a frozen bit position; sorting the parity bit positions according to the reliability, selecting x parity bit positions from the minimum reliability, marking the parity bit positions except the selected x parity bit positions as first parity bits, and marking the x parity bit positions as second parity bits; wherein: the first parity bits are adapted for decoding, the second parity bits are adapted for picking a decoding path, and 0< x ≦ (number of parity bit positions); generating a check equation of the first check bit and the second check bit; wherein: adding the information bits at the information bit positions to a check equation of the second check bits with a random probability; generating the first parity bit according to a parity equation of the first parity bit; configuring the second parity bits at the x parity bit positions, configuring the first parity bits at parity bit positions other than the x parity bit positions, and acquiring an information source sequence, configuring information bits in the information source sequence at the information bit positions, and configuring the frozen bit positions, thereby generating a polar code input bit sequence; carrying out polarization code encoding on the polarization code input bit sequence to obtain a polarization code codeword; mapping the polar code words into modulation signals and transmitting the modulation signals through a channel; demodulating the transmitted modulation signal to obtain soft information of bits of the transmitted polarization code word; and processing the soft information of the bits of the polarization code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

Optionally, generating a parity equation for the second parity bit includes: setting a corresponding random probability P (0< P <1) for any second check bit; the information bit positions are added to the parity equation for the second parity bit with the probability P.

Optionally, the check equation of any one of the first check bits includes a check relation of a previous first check bit.

Optionally, generating a parity equation of the first parity bit includes: dividing a sequence formed by the first check bits into s segments; wherein: s is a non-zero natural number; and adding the first check bit corresponding to the previous check bit position to the check equation of the first check bit corresponding to each check bit position of any section.

Optionally, after adding the first parity bit corresponding to the previous parity bit position, the method further includes: setting an information bit position interval as an interval p; wherein the interval p is a prime number; for any first check bit, selecting an information bit position which is before the check bit position of the first check bit and has a check interval with the first check bit being a multiple of the interval p; and adding the information bit corresponding to the information bit position into a check equation of the first check bit.

Optionally, after adding the first parity bit corresponding to the previous parity bit position, the method further includes: counting the information bit position before the ith check bit position; arranging the information bit positions from small to large according to the position sequence numbers to obtain a sequence Iindex formed by information bits, wherein the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

Optionally, the determining the information bit position, the check bit position, and the frozen bit position respectively includes: acquiring the length K of a required information bit, the length M of a required polarization code and the length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: k; determining a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, wherein n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin are provided; determining the number Fp of the check bit positions; judging the size of the number n and the number Fp of the positions with the minimum row weight dmin, determining the Fp position with the row weight dmin and the best reliability of the corresponding generating matrix in the third subsequence as the check bit position when n > Fp, and determining the position with (Fp + n)/2 row weights dmin in the third subsequence and the position with (Fp-n)/2 row weights 2dmin in the third subsequence as the check bit position when n is less than or equal to Fp; marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

Optionally, the processing the soft information of the bits of the polar code codeword by using a continuous cancellation list decoding algorithm to obtain a decoding result includes: determining the bit value of each position according to the mapping relation between the position attribute of each bit position and the bit value to form a plurality of candidate code words and form a candidate code word list; when the second check bit number is not 0, performing parity check on each candidate code word by adopting the second check bit, and calculating the reliability of all candidate code words in the candidate code word list; selecting the candidate code word which has the maximum reliability and can pass the second check bit check as a decoding result; and when the second check bit number is 0, selecting the candidate code word with the maximum reliability as a decoding result.

Optionally, the determining the bit value of each bit position according to the mapping relationship between the position attribute of each bit position and the bit value includes: when the current bit position is the frozen bit position, determining that the bit value at the position is 0, when the current bit position is the information bit position or the position corresponding to the second check bit, equally dividing the bit value at the position into two values, namely 0 and 1, and when the current bit position is the position corresponding to the first check bit, calculating the value of the first check bit according to a check equation of the first check bit to be used as the bit value at the position.

The embodiment of the invention provides a device for coding and decoding a polarization code, which comprises: a first determining unit adapted to determine an information bit position, a check bit position and a frozen bit position, respectively; a first generation unit adapted to generate a check equation for each check bit; wherein: the check equation of each check bit contains the check relation of the previous check bit; a first generating unit adapted to generate parity bits according to the parity equation; a second generating unit, adapted to configure the parity bits at the parity bit positions, obtain an information source sequence, configure information bits in the information source sequence at the information bit positions, and configure the frozen bit positions, and generate a polar code input bit sequence; the first coding unit is suitable for carrying out polarization code coding on the polarization code input bit sequence to obtain a polarization code codeword; the first modulation unit is suitable for mapping the polar code words into modulation signals and transmitting the modulation signals through a channel; the first demodulation unit is suitable for demodulating the transmitted modulation signal to obtain the soft information of the bits of the transmitted polarization code words; and the first decoding unit is suitable for processing the soft information of the bits of the polar code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

Optionally, the first determining unit is adapted to obtain a length K of a required information bit, a length M of a required polarization code, and a length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: k; determining a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, wherein n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin are provided; determining the number Fp of the check bit positions; judging the size of the position number n and the number Fp with the minimum row weight dmin, and determining the Fp position with the row weight dmin of the corresponding generating matrix in the third subsequence and the best reliability as the check bit position when n is larger than Fp; determining positions where (Fp + n)/2 rows in the third subsequence are repeated to dmin and positions where (Fp-n)/2 rows in the third subsequence are repeated to 2dmin as the check bit positions when n is less than or equal to Fp; marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

Optionally, the first generating unit is adapted to divide a sequence of check bits at the check bit positions into s segments; wherein: s is a non-zero natural number; and adding the check bit corresponding to the previous check bit position to the check equation of the check bit corresponding to each check bit position of any section.

Optionally, the first generating unit is further adapted to set an information bit position interval to be an interval p after the parity bit corresponding to the previous parity bit position is added; wherein the interval p is a prime number; for any check bit, selecting an information bit position which is before the check bit position where the check bit is located and has a check interval with the check bit being a multiple of the interval p; and adding the information bits corresponding to the information bit positions into a check equation of the check bits.

Optionally, the first generating unit is further adapted to, after the parity bit corresponding to the previous parity bit position is added, count the information bit position before the ith parity bit position to obtain a sequence Iindex formed by the information bits, where the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

Optionally, the first generating unit is adapted to, when the position sequence number a is not greater than Isize and the information bit at the a-th information bit position in the sequence Iindex is not marked, add the a-th information bit in the sequence Iindex to a parity equation of the i-th parity bit and mark, and self-add (q-i +1) the position sequence number a, and repeat the determining of the size relationship between the position sequence number a and the length Isize; if the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

The embodiment of the invention provides a device for coding and decoding a polarization code, which comprises: a second determining unit adapted to determine an information bit position, a check bit position and a frozen bit position, respectively; a marking unit, adapted to sort the parity bit positions according to reliability, select x parity bit positions from the smallest reliability, mark parity bit positions other than the x selected parity bit positions as first parity bits, and mark the x parity bit positions as second parity bits; wherein: the first parity bits are adapted for decoding, the second parity bits are adapted for picking a decoding path, and 0< x ≦ (number of parity bit positions); a third generating unit adapted to generate a check equation of the first check bit; a fourth generating unit adapted to generate a parity equation for the second parity bit; wherein: adding the information bits at the information bit positions to a check equation of the second check bits with a random probability; a second generating unit adapted to generate the first parity bit according to a parity equation of the first parity bit; a fifth generating unit, adapted to configure the second parity bits at the x parity bit positions, configure the first parity bits at parity bit positions other than the x parity bit positions, and obtain an information source sequence, configure information bits in the information source sequence at the information bit positions, and configure the frozen bit positions, thereby generating a polar code input bit sequence; the second coding unit is suitable for carrying out polarization code coding on the polarization code input bit sequence to obtain a polarization code codeword; the second modulation unit is suitable for mapping the polar code words into modulation signals and transmitting the modulation signals through a channel; the second demodulation unit is suitable for demodulating the transmitted modulation signal to obtain the soft information of the bits of the transmitted polarization code words; and the second decoding unit is suitable for processing the soft information of the bits of the polar code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

Optionally, the fourth generating unit is adapted to set a corresponding random probability P (0< P <1) for any one of the second parity bits; the information bit positions are added to the parity equation for the second parity bit with the probability P.

Optionally, the third generating unit is adapted to divide the sequence of the first parity bits into s segments; wherein: s is a non-zero natural number; and adding the first check bit corresponding to the previous check bit position to the check equation of the first check bit corresponding to each check bit position of any section.

Optionally, the third generating unit is adapted to set an information bit position interval to be an interval p after the first parity bit corresponding to the previous parity bit position is added; wherein the interval p is a prime number; for any first check bit, selecting an information bit position which is before the check bit position of the first check bit and has a check interval with the first check bit being a multiple of the interval p; and adding the information bit corresponding to the information bit position into a check equation of the first check bit.

Optionally, the third generating unit is further adapted to count information bit positions before an ith check bit position; arranging the information bit positions from small to large according to the position sequence numbers to obtain a sequence Iindex formed by information bits, wherein the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

Optionally, the third generating unit is adapted to, when the position sequence number a is less than or equal to Isize, and an information bit at an a-th information bit position in the sequence Iindex is not marked, add the a-th information bit in the sequence Iindex to a parity equation of an i-th parity bit, and mark, and self-add (q-i +1) the position sequence number a, and repeat the determining of the size relationship between the position sequence number a and the length Isize; if the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

Optionally, the second determining unit is adapted to obtain a length K of a required information bit, a length M of a required polarization code, and a length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: k; determining a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, wherein n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin are provided; determining the number Fp of the check bit positions; judging the size of the number n and the number Fp of the positions with the minimum row weight dmin, determining the Fp position with the row weight dmin and the best reliability of the corresponding generating matrix in the third subsequence as the check bit position when n > Fp, and determining the position with (Fp + n)/2 row weights dmin in the third subsequence and the position with (Fp-n)/2 row weights 2dmin in the third subsequence as the check bit position when n is less than or equal to Fp; marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

Optionally, the second decoding unit is adapted to determine, according to a mapping relationship between a position attribute of each bit position and a bit value, the bit value of each position to form a plurality of candidate codewords, so as to form a candidate codeword list; when the second check bit number is not 0, performing parity check on each candidate code word by adopting the second check bit, and calculating the reliability of all candidate code words in the candidate code word list; selecting the candidate code word which has the maximum reliability and can pass the second check bit check as a decoding result; and when the second check bit number is 0, selecting the candidate code word with the maximum reliability as a decoding result.

Optionally, the second decoding unit is adapted to determine that a bit value at a current bit position is 0 when the current bit position is a frozen bit position, divide the bit value at the current bit position into two values, i.e., 0 and 1, when the current bit position is an information bit position or a position corresponding to the second parity bit, and calculate a value of the first parity bit as the bit value at the current bit position according to a parity equation of the first parity bit when the current bit position is the position corresponding to the first parity bit.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the above scheme, since the check equation of each check bit includes the check relation of the previous check bit, multiple checks can be performed on the information bits, and the check bits can be mutually checked and supplemented, so that the frame error rate of polar code coding can be reduced.

In the above scheme, the parity bits are divided into the first parity bits for decoding and the second parity bits for selecting the decoding path, and all information bits participate in the generation of the second parity bits at random probability, so that the information bit range protected by the parity bits can be enlarged, and the error level of the polar code coding can be reduced.

Furthermore, the check equation of each check bit also contains the check relation of the previous check bit, so that the false alarm rate of polar code coding can be reduced.

In addition, as the check interval values with different lengths are set for each check bit, the randomness of the check relation can be increased, and the error rate of the polar code coding can be further reduced.

Drawings

FIG. 1 is a flow chart of a compiling method of CRC-polar in the prior art;

FIG. 2 is a flow chart of a compiling method of PC-polar in the prior art;

FIG. 3 is a flowchart illustrating a method for polar code encoding according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a relationship between check bits and information bits according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating frame error rate performance obtained by a method for coding a polar code according to an embodiment of the present invention;

FIG. 6 is a flow chart of another method for polar code encoding in an embodiment of the present invention;

FIG. 7 is a diagram illustrating frame error rate performance obtained by a method for coding a polar code according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating false alarm rate performance obtained by a method for encoding and decoding a polarization code according to an embodiment of the present invention;

FIG. 9 is a flowchart illustrating another method for encoding and decoding polar codes according to an embodiment of the present invention;

FIG. 10 is a diagram of a mother code sequence in an embodiment of the invention;

FIG. 11 is a diagram illustrating a relationship between check bits according to an embodiment of the present invention;

FIG. 12 is a diagram illustrating another exemplary relationship between parity bits according to an embodiment of the present invention;

FIG. 13 is a block diagram of an apparatus for polar code encoding according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of another polar code encoding apparatus in the embodiment of the present invention.

Detailed Description

Fig. 1 shows a flow of a compiling method of CRC-polar, and as shown in fig. 1, the flow of the compiling method of CRC-polar is as follows:

firstly, CRC encoding is carried out on an input information sequence by a CRC encoder, and then the information sequence and CRC check bits generated by the CRC encoding are sent to a Polar encoder together; polar encoder generates Polar code words and outputs to modulator.

The modulator maps the polar code words into modulation signals and transmits the modulation signals to the demodulator through a channel; and the demodulator demodulates the transmitted modulation signal to obtain soft information of the bits of the transmitted Polar code words, and the soft information is input to a Polar-CRC joint decoder for decoding. When decoding is carried out on the Polar-CRC combined decoder, a CRC-assisted SCL decoding algorithm is adopted, when the code words in the list are selected at last in decoding, all candidate code words are restored to candidate information sequences containing CRC, CRC processing is carried out on all candidate information sequences, and the candidate information sequence which passes through the CRC processing and has the highest reliability is taken as a final decoding result.

FIG. 2 shows a flow of a compiling method of PC-polar, and as shown in FIG. 2, the flow of the compiling method of PC-polar is as follows:

the PC coder places the information sequence at the position with larger capacity of the bit channel, calculates the check bit value according to the position distribution of the information bit, sends the information sequence and the check bit into a Polar coder, and the Polar coder generates a Polar code word and outputs the Polar code word to the modulator.

The modulator maps the Polar code words into modulation signals and transmits the modulation signals through a channel, the demodulator demodulates the transmitted modulation signals to obtain soft information of bits of the transmitted Polar code words, the soft information is input to a Polar-CRC joint decoder for decoding, when the Polar-CRC joint decoder decodes, a parity check auxiliary SCL decoding algorithm is adopted for decoding, and the decoded information bits are subjected to the same check calculation to obtain the decoding of check bits.

In order to solve the above problem, the check equation of each check bit in the embodiment of the present invention includes a check relation of a previous check bit, so that multiple checks can be performed on information bits, and check bits can be mutually checked and supplemented, so that a frame error rate of polar code coding can be reduced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 is a flowchart illustrating a method for polar code coding according to an embodiment of the present invention, and the method is described in detail with reference to fig. 3, where as shown in fig. 3, the method may include the following steps:

step S31: and respectively determining an information bit position, a check bit position and a frozen bit position.

In specific implementation, how to respectively determine an information bit position, a check bit position and a freeze bit position, the length K of a required information bit, the length M of a required polarization code and the length N of a corresponding polarization code mother code can be firstly obtained, then N bit channels are ordered from low to high according to reliability to obtain a sequence Q, then a puncturing position T is determined, and then the sequence Q is split into a first subsequence, a second subsequence and a third subsequence according to the puncturing position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: K.

then, after the third subsequence is obtained by splitting, the minimum value dmin of the row weight of the generator matrix corresponding to the third subsequence can be determined, n positions of the generator matrix corresponding to the third subsequence having the minimum row weight dmin are provided, the number Fp of the check bit positions is determined, and the number n of the positions having the minimum row weight dmin and the size of the number Fp are determined.

Specifically, when n > Fp, determining Fp positions with the best reliability, where dmin is the row of the corresponding generator matrix in the third subsequence, as the check bit positions; and when n is less than or equal to Fp, determining the position with (Fp + n)/2 rows being as dmin in the third subsequence and the position with (Fp-n)/2 rows being as 2dmin in the third subsequence as the check bit position.

On the sequence Q, K information bit positions may be marked in order of high reliability, skipping the puncturing position T and the position that has been determined as the check bit position, the remaining positions in the sequence Q are all marked as the frozen bit positions, and a position having the same row weight as the check bit position is selected from the frozen bit positions and marked as the check bit position, and all the check bit positions constitute a sequence length of Q.

Step S32: a parity equation for each parity bit is generated.

In a specific implementation, the check equation for each check bit contains the check relation for the previous check bit.

In a specific implementation, a sequence formed by the check bits at the check bit positions may be divided into s segments, where s is a non-zero natural number. And adding the check bit corresponding to the previous check bit position to the check equation of the check bit corresponding to each check bit position of any section so as to generate the check equation of each check bit.

In an embodiment of the present invention, in the process of generating the check equation for each check bit, after adding the check bit corresponding to the previous check bit position, an information bit position interval may also be set to be an interval p, then, for any check bit, an information bit position that is before the check bit position where the check bit is located and whose check interval with the check bit is a multiple of the interval p is selected, and then, the information bit corresponding to the information bit position is added to the check equation for the check bit.

In other words, the value of the check bit at the current bit position can be obtained by performing an exclusive-or operation on the corresponding information bit value. Note that the interval p is a prime number. Therefore, the complexity and the amount of calculation of the compilation can be reduced.

In order to make those skilled in the art better understand and implement the present invention, fig. 4 shows a relationship diagram of parity bits and information bits in an embodiment of the present invention, where P is 5, and P1, P2, P3, and P4 characterize parity bits. As shown in fig. 4, the white-filled lattices represent frozen bit positions, the black-filled lattices represent information bit positions, the gray-filled lattices represent check bit positions, and the black-filled lattices connected to the gray-filled lattices by the arrowed curve are information bits participating in the check bit generation, that is, the black-filled lattices may be added to the check equation of the check bits represented by the gray-filled lattices.

In order to increase the randomness of the check relationship and further reduce the error rate of the polar code coding, in another embodiment of the present invention, check interval values with different lengths may be set for each check bit.

Specifically, in the process of generating the parity equation for each parity bit, after adding the parity bit corresponding to the previous parity bit position, the information bit position before the ith parity bit position may be counted to obtain a sequence Iindex formed by the information bits, where the length of the sequence Iindex is Isize: 0< i < (q + 1). And then configuring an initial value a of the position serial number as i, judging the size relationship between the position serial number a and the length Isize, and correspondingly adding the information bit on the position serial number a into a check equation according to the size relationship between the position serial number a and the length Isize.

In a specific implementation, how to add the information bits on the position sequence number a to the check equation according to the size relationship between the position sequence number a and the length Isize. In detail, when the position sequence number a is not greater than Isize, and the information bit at the a-th information bit position in the sequence Iindex is not marked, the a-th information bit in the sequence Iindex is added to the parity equation of the i-th parity bit, and is marked, and the position sequence number a is added with (q-i +1), and the determination of the size relationship between the position sequence number a and the length Isize is repeated. If the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

For example, when q is 4, i is 1, Isize is 0, and the position number 1>0, i is incremented by 1.

When q is 4, i is 2, Isize is 7, the position number 2 is not more than 7, and the information bit at the 2 nd information bit position in the sequence Iindex is not marked, adding the 2 nd information bit in the sequence Iindex into the check equation of the 2 nd check bit, marking, adding 3 to the position number 2, and repeating the judging of the size relationship between the position number 5 and the length 7. And when the position serial number is not more than 5 and not more than 7, and the information bit at the 5 th information bit position in the sequence Iindex is not marked, adding the 5 th information bit in the sequence Iindex into a check equation of the 2 nd check bit, marking, adding 3 to the position serial number 5, and repeating the step of judging the size relationship between the position serial number 8 and the length 7. At the position number 8, the position number 8 is greater than the length 7, i is incremented by 1.

When q is 4, i is 3, Isize is 7, the position number 3 is not more than 7, and the information bit at the 3 rd information bit position in the sequence Iindex is not marked, adding the 3 rd information bit in the sequence Iindex into the check equation of the 3 rd check bit, marking, adding 2 to the position number 3, and repeating the above steps to judge the size relationship between the position number 5 and the length 7.

And when the position serial number 5 is less than or equal to 7 and the information bit at the 5 th information bit position in the sequence Iidex is marked, adding 2 to the position serial number 5, and repeatedly judging the size relationship between the position serial number 7 and the length 7. And when the position serial number 7 is less than or equal to 7, and the information bit at the 7 th information bit position in the sequence Iindex is not marked, adding the 7 th information bit in the sequence Iindex into a check equation of the 3 rd check bit, marking, adding 2 to the position serial number 7, and repeating the judging of the size relationship between the position serial number 9 and the length 7. At the position number 9, the position number 9 is greater than the length 7, i is incremented by 1.

When q is 4, i is 4, Isize is 8, the position number 4 is not more than 8, and the information bit at the 4 th information bit position in the sequence Iindex is not marked, adding the 4 th information bit in the sequence Iindex into the check equation of the 4 th check bit, marking, adding 1 to the position number 4, and repeating the above steps to judge the size relationship between the position number 5 and the length 8.

And when the position serial number 5 is less than or equal to 8 and the information bit at the 5 th information bit position in the sequence Iidex is marked, adding 1 to the position serial number 5, and repeatedly judging the size relationship between the position serial number 6 and the length 8. And when the position serial number 6 is less than or equal to 8, and the information bit at the 6 th information bit position in the sequence Iindex is not marked, adding the 6 th information bit in the sequence Iindex into a check equation of the 4 th check bit, marking, adding 1 to the position serial number 6, and repeating the judgment of the size relationship between the position serial number 7 and the length 8.

And when the position serial number 7 is less than or equal to 8 and the information bit at the 7 th information bit position in the sequence Iidex is marked, adding 1 to the position serial number 7, and repeatedly judging the size relationship between the position serial number 8 and the length 8. And when the position serial number 8 is less than or equal to 8, and the information bit at the 8 th information bit position in the sequence Iindex is not marked, adding the 8 th information bit in the sequence Iindex into a check equation of the 4 th check bit, marking, adding 1 to the position serial number 8, and repeating the judging of the size relationship between the position serial number 9 and the length 8. When the position number 9>8, the position number 9 is greater than the length 8, and i equals q, the execution is stopped.

Step S33: generating parity bits according to the parity check equation.

Step S34: and configuring the check bit at the check bit position, acquiring an information source sequence, configuring the information bit in the information source sequence at the information bit position, configuring the frozen bit position, and generating a polarization code input bit sequence.

Step S35: and carrying out polarization code encoding on the polarization code input bit sequence to obtain a polarization code word.

Step S36: and mapping the polar code words into modulation signals and transmitting the modulation signals through a channel.

Step S37: and demodulating the transmitted modulation signal to obtain the soft information of the bits of the transmitted polar code words.

Step S38: and processing the soft information of the bits of the polarization code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

In order to compare frame error rate performance of the embodiments of the present invention so as to make those skilled in the art better understand and implement the present invention, fig. 5 shows frame error rate performance of a parity bit obtained by using a coding method of a polar code in the embodiments of the present invention, and an abscissa E_b/N₀The vertical axis FER represents the frame error rate. It should be noted that, the number of check bits for selecting the decoding path is not configured here, and the frame error rate performance of the signal obtained by the existing coding and decoding methods of CRC-polar and PC-polar is given at the same time, the length of the polar code is 2000, the length of the mother code is 2048, the length of the information bit is 1000, the code rate is 0.5, and the length of the list is 32. The method adopts a Quasi-uniform puncturing (QUP), the channel is AWGN channel, and the modulation adopts a Quadrature Phase Shift Keying (QPSK) mode. The CRC takes 16 bits and the generator polynomial is 0x 18005. The construction method of the polarization code is Gaussian approximate construction, and the constructed signal-to-noise ratio Eb/N0 is 1.75 dB.

As shown in fig. 5, the upper triangular curve 52 represents the frame error rate performance of the Polar code assisted by the conventional CRC16, the lower triangular curve 51 represents the frame error rate performance of the conventional PC-Polar code, and the square curve 53 represents the frame error rate performance of the PC-Polar code in this embodiment. It can be seen that after the snr is 1.8dB, a signal obtained by using the coding method of the polar code in the embodiment of the present invention has a lower frame error rate performance, so that the error floor of the original PC-polar code can be effectively reduced.

At present, the problem of too high frame error rate exists by adopting a PC-polar compiling method and a CRC-polar compiling method.

The check equation of each check bit in the embodiment of the invention contains the check relation of the previous check bit, so that multiple checks can be carried out on the information bit, and the check bits can be mutually checked and supplemented, thereby reducing the frame error rate of polar code compiling.

For better understanding and implementation of the present invention by those skilled in the art, fig. 6 shows a flowchart of a method for polar code coding in an embodiment of the present invention, which is described in detail with reference to fig. 6 and may include the following steps:

s61: and respectively determining an information bit position, a check bit position and a frozen bit position.

In a specific implementation, the determining the information bit position, the check bit position, and the freeze bit position respectively includes: acquiring the length K of a required information bit, the length M of a required polarization code and the length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: K.

in a specific implementation, after obtaining a third subsequence, a minimum value dmin of row weights of generator matrices corresponding to the third subsequence can be determined, and n positions where the generator matrices corresponding to the third subsequence have the minimum row weight dmin are provided; determining the number Fp of the check bit positions; and judging the number n of the positions with the minimum row weight dmin and the size of the number Fp, determining the Fp position with the best reliability of the row weight dmin of the corresponding generating matrix in the third subsequence as the check bit position when n is larger than Fp, and determining the position with (Fp + n)/2 row weights dmin in the third subsequence and the position with (Fp-n)/2 row weights 2dmin in the third subsequence as the check bit position when n is smaller than or equal to Fp.

In a specific implementation, K information bit positions may be marked on the sequence Q in order of high reliability and by skipping the puncturing position T and the position that has been determined as the parity bit position; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

S62: sorting the check bit positions according to the reliability, selecting x check bit positions from the minimum reliability, marking the check bit positions except the selected x check bit positions as first check bits, and marking the x check bit positions as second check bits.

In a specific implementation, the parity bit positions may be sorted according to the reliability, x parity bit positions with the smallest reliability may be selected to be marked as second parity bits, and parity bit positions other than the selected x parity bit positions may be marked as first parity bits. Wherein: the first parity bits are adapted for decoding, the second parity bits are adapted for picking a decoding path, and 0< x ≦ (number of parity bit positions).

It should be noted that, for convenience of description, the first parity bit may be referred to as PC, and the second parity bit may be referred to as PCselect.

S63: generating a check equation of the first check bit and the second check bit; wherein: the information bits at the information bit positions are added to the parity check equations for the second parity bits with random probability.

In a specific implementation, regarding the process of generating the parity equations of the second parity bits, in detail, a corresponding random probability P (0< P <1) may be set for any one second parity bit, and then the information bit positions are added to the parity equations of the second parity bits with the probability P.

S64: generating the first parity bit according to a parity equation of the first parity bit.

S65: and configuring the second parity bits at the x parity bit positions, configuring the first parity bits at parity bit positions other than the x parity bit positions, acquiring an information source sequence, configuring information bits in the information source sequence at the information bit positions, configuring the frozen bit positions, and generating a polar code input bit sequence.

S66: and carrying out polarization code encoding on the polarization code input bit sequence to obtain a polarization code word.

S67: and mapping the polar code words into modulation signals and transmitting the modulation signals through a channel.

S68: and demodulating the transmitted modulation signal to obtain the soft information of the bits of the transmitted polar code words.

S69: and processing the soft information of the bits of the polarization code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

In a specific implementation, a continuous cancellation list decoding algorithm may be used to process soft information of bits of the polar code codeword to obtain a decoding result. Specifically, the bit value of each bit position may be determined according to a mapping relationship between the position attribute of each bit position and the bit value, a plurality of candidate codewords are formed, a candidate codeword list is formed, when the second parity bit number is not 0, parity check is performed on each candidate codeword by using the second parity bit, and the reliability of all candidate codewords in the candidate codeword list is calculated; selecting the candidate code word which has the maximum reliability and can pass the second check bit check as a decoding result; and when the second check bit number is 0, selecting the candidate code word with the maximum reliability as a decoding result.

In an embodiment of the present invention, according to a mapping relationship between a position attribute of each bit position and a bit value, when a current bit position is a frozen bit position, it may be determined that the bit value at the position is 0, when the current bit position is an information bit position or a position corresponding to the second parity bit, the bit value at the position is divided into two, i.e., 0 and 1, and when the current bit position is a position corresponding to the first parity bit, a value of the first parity bit is calculated according to a check equation of the first parity bit and is used as the bit value at the position.

In order to compare the error floor performance of the embodiment of the present invention so as to make those skilled in the art better understand and implement the present invention, fig. 7 shows the frame error rate performance of a signal obtained by using the coding method of the polar code in the embodiment of the present invention, and at the same time, shows the frame error rate performance of a signal obtained by using the existing coding method of the PC-polar.

As shown in fig. 7, the abscissa E_b/N₀The vertical axis FER represents the frame error rate. The length of the polar code is 128, the length of the information bit is 64, the code rate is 0.5, and the length of the list is 32. The channel is AWGN channel and the modulation uses QPSK. The polarization code adopts a Gaussian approximate structure, and the signal-to-noise ratio E of the structure_b/N₀-1.59 dB. And setting the number x of PCselect to be 5, selecting 5 check bit positions with the minimum reliability to set PCselect, giving a random probability P equal to 0.5, adding each information bit into a parity check equation of PCselect with a probability of 0.5, and generating the first check bit according to the current generation mode of the PC-Polar code. And generating parity check equations of all PCselect according to the rule.

In fig. 7, an upper triangular curve 72 represents the frame error rate performance of the existing PC-polar code when x is equal to 0, and a square curve 71 represents the frame error rate performance of the coding method according to the embodiment of the present invention, and as can be seen from fig. 7, the coding method according to the embodiment of the present invention has better frame error rate performance and error floor performance at a high snr.

At present, two polar code compiling methods are provided, namely a PC-polar compiling method and a CRC-polar compiling method, but both the two compiling methods have the problem of over high frame error rate.

In the embodiment of the invention, the check bits are divided into the first check bits for decoding and the second check bits for selecting the decoding path, and all the information bits participate in the generation of the second check bits with random probability P, so that the information bit range protected by the check bits can be enlarged, and the error level of polar code coding can be reduced.

In a specific implementation, the check equation of any one of the first check bits may include a check relation of a previous first check bit, so that multiple checks may be performed, and a frame error rate of decoding the polar code may be reduced. Also, the false alarm rate of compilation may be reduced.

In a specific implementation, the following steps may be adopted to generate the check equation of the first check bit. Specifically, the sequence formed by the first parity bits may be divided into s segments; wherein: s is a non-zero natural number; and adding the first check bit corresponding to the previous check bit position to the check equation of the first check bit corresponding to each check bit position of any section.

In specific implementation, after the first parity bit corresponding to the previous parity bit position is added, an information bit position interval may also be set to be an interval p; the interval p is a prime number, then for any first check bit, an information bit position which is before the check bit position where the first check bit is located and has a check interval with the first check bit being a multiple of the interval p is selected, and finally the information bit corresponding to the information bit position is added to a check equation of the first check bit, so that the calculation amount in the encoding process can be reduced.

In order to increase the randomness of the check relationship and further reduce the frame error rate of the coding, in a specific implementation, after the first check bit corresponding to the previous check bit position is added, check interval values with different lengths may be set for each check bit.

In detail, the information bit positions before the ith parity bit position may be counted, and then the information bit positions are arranged from small to large according to the position sequence number to obtain a sequence Iindex formed by the information bits, where the length of the sequence Iindex is Isize; wherein: 0< i < (q +1), then configuring an initial value a of a position serial number as i, judging the size relationship between the position serial number a and the length Isize, and correspondingly adding the information bit on the position serial number a into a check equation according to the size relationship between the position serial number a and the length Isize.

In a specific implementation, the correspondingly adding the information bits on the position sequence number a to the check equation according to the size relationship between the position sequence number a and the length Isize may be implemented according to the following steps: when the position sequence number a is not greater than Isize, and the information bit at the a-th information bit position in the sequence Iindex is not marked, adding the a-th information bit in the sequence Iindex into a parity equation of the i-th parity bit, marking, self-adding (q-i +1) the position sequence number a, and repeating the judging of the size relationship between the position sequence number a and the length Isize. If the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

In order to compare the false alarm rate performance of the embodiment of the present invention so as to make those skilled in the art understand and implement the present invention better, fig. 8 shows the false alarm rate performance of a signal obtained by using the coding method of the polar code in the embodiment of the present invention, and simultaneously shows the performance of the existing CRC4-polar scheme for selecting a decoding path with an extra 4-bit CRC, and the performance of the existing PC-polar scheme, that is, the pcelsect without selecting a path.

As shown in fig. 8, the upper triangular curve 81 represents the false alarm rate performance of the conventional CRC4-Polar code, the lower triangular curve 82 represents the false alarm rate performance of the conventional PC-Polar code, and the square curve 83 represents the PC-Polar false alarm rate performance of the present embodiment. The length of the polar code is 64, the length of the information bit is 32, the code rate is 0.5, and the length of the list is 8. The channel is AWGN channel and the modulation uses QPSK. The polarization code is constructed by adopting Gaussian approximation, and the constructed Eb/N0 is 1.25 dB. In the three curves, the CRC length used for the statistics of the false alarm rate is 16, and the generator polynomial is 0x 18005.

In order to obtain the false alarm rate, part of the check bits may be configured to be used for counting the false alarm rate, specifically, information bit positions of the Polar code, CRC positions, check bit positions, and frozen bit positions used for counting the false alarm rate may be determined, and the reliability of the CRC positions is only second to that of the information bits. And in the process of generating the check equation of each check bit, the CRC bit is also regarded as the information bit and added to the check equation. And setting the number x of PCselect as 3, selecting 3 PCs with the minimum reliability as the PCselect, giving a random probability P equal to 0.5, adding each information bit into a parity check equation of the PCselect according to the probability 0.5, and generating the parity check equations of all the PCselect according to the rule. After the receiving end demodulates, the soft information of the receiving sequence is sent to an SCL decoder, and CRC does not participate in decoding and is only used for counting the false alarm rate after decoding. The number of code words passing the check but decoding errors is recorded as FAerror, and the total number of error code words is frameError.

The statistical False alarm rate formula is as follows:

false alarm rate ═ FAerror/frameError; the false alarm rate is the ratio of the number of code words passing the check but decoding errors to the total number of code words in error.

In fig. 8, the upper triangular curve represents the performance of the existing CRC4 assisted Polar code, the lower triangular curve represents the performance of the existing PC-Polar code, and the square curve represents the performance of the PC-Polar code of this embodiment, and it can be seen from fig. 8 that the Polar code compiling method in the embodiment of the present invention can have better false alarm rate performance.

For those skilled in the art to better understand and implement the present invention, fig. 9 shows a flowchart of another method for coding polarization codes in the embodiment of the present invention, and as shown in fig. 9, the method may be implemented according to the following steps:

step S901: the information bit positions, check bit positions and frozen bit positions of the polarization code are determined.

It should be noted that the information bit length is K, the code length is M, and the mother code length is N ═ 2^ M, where M is a positive integer. In a specific implementation, the following steps can be taken to determine the information bit positions, check bit positions and freeze bit positions of the polarization code. In detail, firstly, the reliability of the N bit channels is calculated by using gaussian approximation, so as to obtain a sequence Q of the reliability of the bit channels from low to high, and the puncturing position T is determined by adopting an QUP puncturing scheme. The sequence Q is then divided into three parts, the sequence with the highest reliability has a length K, and for convenience of description, the sequence with the length K may be referred to as the sequence Q, and specifically, refer to fig. 10, where the sequence Q is a rightmost part of the sequence in fig. 10.

In a specific implementation, each element of the sequence Q may correspond to a row of a corresponding element in a generator matrix of the polarization code, and the number of 1 s in each row is the row weight of the row. The minimum row weight dmin can be found from the rightmost K-long sequence, which is designated dmin, and the sequence with the rightmost K-long sequence has a minimum row weight dmin at n positions.

In a specific implementation, the number Fp preset to the PC position may be calculated according to the following formula:

Fp＝ceil(log2(N*K)/2)；

moreover, the sizes of n and Fp can be judged, and the check bit position can be marked according to the size relation of the n and the Fp. In detail, when n is greater than Fp, the position of Fp with the best reliability in the marking sequence Q is used as PC; otherwise, the locations (Fp + n)/2 rows with weights of dmin and (Fp-n)/2 rows with weights of 2dmin are marked as PCs.

Referring to fig. 10, in a specific implementation, K information bits may be marked in order of high to low reliability, i.e., in order from right to left, and the punching position T and the position marked as PC in the previous step are skipped in the marking process.

In a specific implementation, the remaining positions may be marked with the frozen bit positions, and then a position having the same row weight as the PC bit position is selected from the frozen bit positions and marked with the PC bit position.

Step S902: parity bits for selecting the decoding path and a parity equation of the parity bits for decoding are generated.

It should be noted that, in step S901, the length of the total marked parity bit positions is q, the parity bit positions are not used for configuring the parity bits for selecting the decoding path, and are not used for decoding, so before performing the check equation for generating the parity bits for selecting the decoding path and the parity bits for decoding, a part of the parity bit positions may be first selected to be marked as the parity bits for selecting the decoding path. For convenience of description, the check bits for picking the decoding path may be recorded as PCselect.

In a specific implementation, the reliabilities of all check bit positions with length q may be sorted, and the x PC positions with the minimum reliability are selected for being marked as PCselect, and x >0, and x ≦ q.

In order to reduce the false alarm rate of the polar code coding, in a specific implementation, the information bits can be set to randomly participate in the generation of the check bits so as to increase the information bit range protected by the check bits. In detail, the parity check equation of PCselect can be configured with a high density. The generation process of the PCselect parity check equation with high density can be that a random probability P (0< P <1) is given to a PCselect, and each information bit is added into the parity check equation of the PCselect according to the probability P. Moreover, different PCselect probabilities P can be set for different PCselect, so that the randomness can be further improved, and the frame error rate can be further reduced.

In a specific implementation, when generating the check equation for the decoded check bits, the check equation may be implemented by first dividing a q-long check bit position sequence into s segments (s >0), and adding each check bit in each segment to the check equation of an immediately following check bit in the segment, but this relationship only applies to the check bits of the same segment, and the last check bit of each segment does not participate in the check equation of the first check bit of the next segment.

Specifically, referring to fig. 11, as shown in fig. 11, the sequence with the entire length of q is divided into s segments, which are respectively the 1 st segment, the 2 nd segment … and the s th segment, the 1 st segment includes parity bits P1, P2 … and Pi, the 2 nd segment includes parity bits P (i +1) …, and the s th segment includes parity bits … P (q-1) and Pq. The parity check equation of the next parity bit in each segment includes the previous parity bit in units of segments, and is represented by a connected arrow in fig. 11. The check equations such as P2 include the check equation of P1 and the check equation of Pq includes the check equation of P (q-1). However, the check equation for P (i +1) does not include the check equation for Pi, since the two do not belong to the same segment.

In order to increase the randomness of the check relationship and further reduce the false alarm rate, in a specific implementation, check interval values with different lengths may be set for each check bit. In detail, the step (a) may be performed: counting the information bits before the ith (0< i < q +1) check bit, arranging the position sequence numbers of the information bits from small to large, and for convenience of description, recording the position sequence of the obtained information bits as Ilndex and the length as Isize.

The step (b): an initial value a ═ i is set.

The step (c): and then judging the size relationship between the initial value and the length of the position sequence of the information bits, when a < Isize, and if the a-th information bit in Iindex is not added into the check equation, adding the a-th information bit in Iindex into the check equation of the i-th check bit, marking the a-th information bit, and then executing the step (d). Specifically, the value of a is increased, a + (q-i +1), and step (c) is repeatedly performed. That is, the relationship between the increased initial value and the length of the position sequence of the information bits is repeatedly determined, when the increased initial value a < Isize, and if the a-th information bit in Iindex is not added to the check equation, the a-th information bit in Iindex may be added to the check equation of the i-th check bit and labeled, and then the value of a is increased, a ═ a + (q-i +1), until i ═ q.

If the a-th information bit in Iindex is marked in the previous check equation, the value of a is increased, and a ═ a + (q-i +1), then step (c) can be directly executed.

The step (d): and (c) increasing the value of a, wherein a is a + (q-i +1), and repeating the step (c).

In a specific implementation, when a > Isize, i ═ i +1, step (a) is repeated until i ═ q, that is, steps (a) to (d) are performed for all information bit positions.

In a specific implementation, if no information bit position participates in the parity equation for checking bit positions, the information bit position can be coded as a frozen bit position.

In a specific implementation, the check relationship of the bit positions obtained in the steps (a) to (d) may refer to fig. 12. As shown in fig. 12, the white-filled boxes represent the frozen bit positions, the black-filled boxes represent the information bit positions, the gray-filled boxes represent the parity bit positions, and the gray-filled boxes connected to the black-filled boxes are the information bits participating in the parity equation. The check relations of different check bits are distinguished by lines with different thicknesses and virtual and real values of the lines, and check equations between bit positions of arrow connecting lines with the same virtual and real values and thickness have included check relations.

As shown in fig. 12, I1, I2, … indicate information bits, F1, F2, … indicate frozen bits, P1, P2, … indicate PC bits, and the total number of PC bits q is 10, since there is no information bit before P1-P5, when the frozen bits are processed, correspondingly, P1-P5 are also decoded as frozen bits during decoding. When I is 6, the initial value a is 6, the increment interval of a is q-I +1 is 5, and the bits participating in the calculation of the check bit of P6 are P5, I6, I11 and I16. When I is 7, the initial value a is 7, the increment interval of a is q-I +1 is 4, and the bits participating in the calculation of the check bit of P7 are P6, I7 and I15.

Step S903: and placing the information bits at the information bit positions, generating parity check bits according to a check equation, placing the parity check bits in the corresponding check bit positions, and placing 0 s in other bits.

In a specific implementation, the other positions, namely the frozen bit positions, are set to 0.

Step S904: and sending the information source sequence into a polarization code encoder to generate a polarization code word.

Step S905: and according to the punching pattern T, punching the code words of the polarization codes, mapping the punched code words into modulation symbols and sending the modulation symbols to a channel.

Because the length of the mother code sequence is a power of 2, the mother code can not be directly the length of the required code word sequence, so in specific implementation, the polarization code word can be subjected to punching processing according to the punching pattern T. For example, if the length of the mother code sequence is 8 and the length of the required codeword sequence is 7, one codeword bit can be deleted by puncturing.

Step S906: the transmitted modulation symbols are passed through a channel to produce noisy modulation symbols.

Step S907: the receiving end demodulates the modulated symbol with noise and sends the demodulated soft information to the SCL decoder assisted by PC.

Step S908: PC assisted SCL decoding.

In a specific implementation, the PC-assisted SCL decoding method may include the following steps: firstly, soft information of an information source sequence can be sequentially calculated according to an SCL decoding algorithm, and then when the bit is a frozen bit, the bit is directly judged to be 0. When the bit is an information bit or a PCselect position, two decoding paths are divided, and the information bit is judged to be 0 and 1 respectively. When the bit is a PC location that is not PCselect, the value of the parity bit is calculated according to its parity equation. It should be noted that the presence or absence of the PCselect position is related to the size of x, and when x is zero, the PCselect position does not exist, and is directly a check bit for decoding. When x is not zero, the PCselect position can be determined and decoded in a corresponding manner.

In the specific implementation, since there are multiple determination results when determining the specific content of the bit position, for example, when the bit is an information bit or a PCselect position, two decoding paths are divided, so that multiple combinations of determination results can be correspondingly generated, and a candidate codeword list, that is, all possible combinations of determination results, can be formed. Parity checking can then be performed on the x PCselect positions of each candidate codeword in the candidate codeword list, that is, a modulo two sum is calculated for all positions participating in the check equation for PCselect, and if the modulo two sum is equal to the value of this bit PCselect, the check is passed, otherwise the check is not passed.

In a specific implementation, the candidate code word with the highest reliability and passing all the PCselect checks can be selected as the final decoding result. And if no candidate code word passes the check of all PCselect, selecting the candidate code word with the highest reliability as the final decoding result.

In summary, the embodiment of the present invention improves the error floor and false alarm probability performance of the PC-polar and the CRC-polar on the basis of the PC-polar by changing the generation mode of the parity bits under the condition of ensuring the frame error rate performance.

In order to make those skilled in the art better understand and implement the present invention, fig. 13 shows a schematic structural diagram of an apparatus for polar code coding in an embodiment of the present invention, as shown in fig. 13, the apparatus may include: first determining section 131, first generating section 132, first generating section 133, second generating section 134, first encoding section 135, first modulating section 136, first demodulating section 137, and first decoding section 138, wherein:

a first determining unit 131 adapted to determine an information bit position, a check bit position and a frozen bit position, respectively;

a first generating unit 132 adapted to generate a parity equation for each parity bit; wherein: the check equation of each check bit contains the check relation of the previous check bit;

a first generating unit 133 adapted to generate parity bits according to the parity equation;

a second generating unit 134, adapted to configure the parity bits at the parity bit positions, obtain an information source sequence, configure information bits in the information source sequence at the information bit positions, and configure the frozen bit positions, and generate a polar code input bit sequence;

a first encoding unit 135, adapted to perform polarization code encoding on the polarization code input bit sequence to obtain a polarization code codeword;

a first modulation unit 136, adapted to map the polar code codeword into a modulated signal, and transmit the modulated signal through a channel;

a first demodulation unit 137, adapted to demodulate the transmitted modulated signal to obtain the soft information of the bits of the transmitted polar code codeword;

the first decoding unit 138 is adapted to process the soft information of the bits of the polar code codeword by using a continuous cancellation list decoding algorithm to obtain a decoding result.

In summary, the check equation of each check bit generated by the first generating unit 132 in the embodiment of the present invention includes the check relationship of the previous check bit, so that multiple checks can be performed on each check bit, and the check bits can be mutually checked and complemented, thereby reducing the frame error rate of polar code coding.

In a specific implementation, the first determining unit 131 is adapted to obtain a length K of a required information bit, a length M of a required polarization code, and a length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: K.

in a specific implementation, the first determining unit 131 is adapted to determine a minimum value dmin of row weights of generator matrices corresponding to the third subsequence, and n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin; determining the number Fp of the check bit positions; and judging the size of the position number n and the number Fp with the minimum row weight dmin, and determining the Fp position with the row weight dmin of the corresponding generating matrix in the third subsequence and the best reliability as the check bit position when n is larger than Fp.

In a specific implementation, the first determining unit 131 is adapted to determine, as the check bit positions, (Fp + n)/2 rows of positions with a weight of dmin in the third subsequence and (Fp-n)/2 rows of positions with a weight of 2dmin in the third subsequence, when n ≦ Fp; marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

In a specific implementation, the first generating unit 132 is adapted to divide the sequence of the check bits at the check bit positions into s segments; wherein: s is a non-zero natural number; and adding the check bit corresponding to the previous check bit position to the check equation of the check bit corresponding to each check bit position of any section.

In a specific implementation, the first generating unit 132 is further adapted to set an information bit position interval to be an interval p after the parity bit corresponding to the previous parity bit position is added; wherein the interval p is a prime number; for any check bit, selecting an information bit position which is before the check bit position where the check bit is located and has a check interval with the check bit being a multiple of the interval p; and adding the information bits corresponding to the information bit positions into a check equation of the check bits.

In a specific implementation, the first generating unit 132 is further adapted to, after the parity bit corresponding to the previous parity bit position is added, count the information bit position before the ith parity bit position to obtain a sequence Iindex formed by the information bits, where the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

In a specific implementation, the first generating unit 132 is adapted to, when the position sequence number a is not greater than Isize, and the information bit at the position of the a-th information bit in the sequence Iindex is not marked, add the a-th information bit in the sequence Iindex to a parity equation of the i-th parity bit, and mark, and self-add (q-i +1) the position sequence number a, and repeat the determining of the size relationship between the position sequence number a and the length Isize. If the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

In order to make those skilled in the art better understand and implement the present invention, fig. 14 shows a schematic structural diagram of another polar code compiling apparatus in an embodiment of the present invention, and as shown in fig. 14, the apparatus may include: second determining section 141, labeling section 142, third generating section 143, fourth generating section 144, second generating section 145, fifth generating section 146, second encoding section 147, second modulating section 148, second demodulating section 149, and second decoding section 150, wherein:

a second determining unit 141 adapted to determine an information bit position, a check bit position and a frozen bit position, respectively;

a marking unit 142, adapted to sort the parity bit positions according to reliability, select x parity bit positions from the smallest reliability, mark parity bit positions other than the selected x parity bit positions as first parity bits, and mark the x parity bit positions as second parity bits; wherein: the first parity bits are adapted for decoding, the second parity bits are adapted for picking a decoding path, and 0< x ≦ (number of parity bit positions);

a third generating unit 143 adapted to generate a parity equation of the first parity bit;

a fourth generating unit 144 adapted to generate a parity equation for the second parity bits; wherein: adding the information bits at the information bit positions to a check equation of the second check bits with a random probability;

a second generating unit 145 adapted to generate the first parity bit according to a parity equation of the first parity bit;

a fifth generating unit 146, adapted to configure the second parity bits at the x parity bit positions, configure the first parity bits at parity bit positions other than the x parity bit positions, and obtain a source sequence, configure information bits in the source sequence at the information bit positions, and configure the frozen bit positions, thereby generating a polar code input bit sequence;

the second encoding unit 147 is adapted to perform polarization code encoding on the polarization code input bit sequence to obtain a polarization code codeword;

a second modulation unit 148, adapted to map the polar code codeword into a modulated signal and transmit the modulated signal through a channel;

a second demodulation unit 149, adapted to demodulate the transmitted modulated signal to obtain the soft information of the bits of the transmitted polar code codeword;

the second decoding unit 150 is adapted to process the soft information of the bits of the polar code codeword by using a continuous cancellation list decoding algorithm to obtain a decoding result.

In summary, in the embodiment of the present invention, the parity bits are divided into the first parity bits for decoding and the second parity bits for selecting the decoding path, and the fourth generating unit 144 participates all the information bits in the generation of the parity equation of the second parity bits with random probability when generating the parity equation of the second parity bits, so that the information bit range protected by the parity bits can be increased, and thus the error floor of the polar code coding can be reduced.

In a specific implementation, the fourth generating unit 144 is adapted to set a corresponding random probability P (0< P <1) for any one of the second parity bits; the information bit positions are added to the parity equation for the second parity bit with the probability P.

In order to increase the false alarm rate of the polar code encoding and decoding, in a specific implementation, the check equation of any one of the first check bits includes a check relation of a previous first check bit.

In a specific implementation, the third generating unit 143 is adapted to divide the sequence of the first parity bits into s segments; wherein: s is a non-zero natural number; and adding the first check bit corresponding to the previous check bit position to the check equation of the first check bit corresponding to each check bit position of any section.

In a specific implementation, the third generating unit 143 is adapted to set an information bit position interval to be an interval p after the first parity bit corresponding to the previous parity bit position is added; wherein the interval p is a prime number; for any first check bit, selecting an information bit position which is before the check bit position of the first check bit and has a check interval with the first check bit being a multiple of the interval p; and adding the information bit corresponding to the information bit position into a check equation of the first check bit.

In a specific implementation, the third generating unit 143 is further adapted to count information bit positions before an i-th parity bit position; arranging the information bit positions from small to large according to the position sequence numbers to obtain a sequence Iindex formed by information bits, wherein the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

In a specific implementation, the third generating unit 143 is adapted to, when the position sequence number a is not greater than Isize and the information bit at the position of the a-th information bit in the sequence Iindex is not marked, add the a-th information bit in the sequence Iindex to a parity equation of the i-th parity bit and mark, and self-add (q-i +1) the position sequence number a, and repeat the determining of the size relationship between the position sequence number a and the length Isize.

In a specific implementation, the third generating unit 143 is adapted to, if the position sequence number a is not greater than Isize and the information bit at the a-th information bit position in the sequence Iindex is already marked, superimpose (q-i +1) the position sequence number a, and continue to repeat the determining of the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i ═ q.

In a specific implementation, the second determining unit 141 is adapted to obtain a length K of a required information bit, a length M of a required polarization code, and a length N of a corresponding polarization code mother code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: K.

in a specific implementation, the second determining unit 141 is adapted to determine a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, and n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin; determining the number Fp of the check bit positions; and judging the number n of the positions with the minimum row weight dmin and the size of the number Fp, determining the Fp position with the best reliability of the row weight dmin of the corresponding generating matrix in the third subsequence as the check bit position when n is larger than Fp, and determining the position with (Fp + n)/2 row weights dmin in the third subsequence and the position with (Fp-n)/2 row weights 2dmin in the third subsequence as the check bit position when n is smaller than or equal to Fp.

In a specific implementation, the second determining unit 141 is adapted to mark K information bit positions on the sequence Q in order from high to low reliability, and skip the puncturing positions T and the positions that have been determined as the parity bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

In a specific implementation, the second decoding unit 150 is adapted to determine a bit value of each bit position according to a mapping relationship between a position attribute of each bit position and the bit value, so as to form a plurality of candidate codewords, and form a candidate codeword list; when the second check bit number is not 0, performing parity check on each candidate code word by adopting the second check bit, and calculating the reliability of all candidate code words in the candidate code word list; selecting the candidate code word which has the maximum reliability and can pass the second check bit check as a decoding result; and when the second check bit number is 0, selecting the candidate code word with the maximum reliability as a decoding result.

In a specific implementation, the second decoding unit 150 is adapted to determine that the bit value at the current bit position is 0 when the current bit position is the frozen bit position, divide the bit value at the current bit position into two values, i.e., 0 and 1, when the current bit position is the information bit position or the position corresponding to the second parity bit, and calculate the value of the first parity bit as the bit value at the current bit position according to the check equation of the first parity bit when the current bit position is the position corresponding to the first parity bit.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer-readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of polar code coding, comprising:

respectively determining an information bit position, a check bit position and a frozen bit position;

sorting the parity bit positions according to the reliability, selecting x parity bit positions from the minimum reliability, marking the parity bit positions except the selected x parity bit positions as first parity bits, and marking the x parity bit positions as second parity bits; wherein: the first parity bits are adapted for decoding, the second parity bits are adapted for picking a decoding path, and 0< x ≦ (number of parity bit positions);

generating a check equation of the first check bit and the second check bit; wherein: adding the information bits at the information bit positions to a check equation of the second check bits with a random probability;

generating the first parity bit according to a parity equation of the first parity bit;

configuring the second parity bits at the x parity bit positions, configuring the first parity bits at parity bit positions other than the x parity bit positions, and acquiring an information source sequence, configuring information bits in the information source sequence at the information bit positions, and configuring the frozen bit positions, thereby generating a polar code input bit sequence;

carrying out polarization code encoding on the polarization code input bit sequence to obtain a polarization code codeword;

mapping the polar code words into modulation signals and transmitting the modulation signals through a channel;

demodulating the transmitted modulation signal to obtain soft information of bits of the transmitted polarization code word;

and processing the soft information of the bits of the polarization code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

2. The polar code coding method according to claim 1, wherein generating the parity equations for the second parity bits comprises:

setting a corresponding random probability P (0< P <1) for any second check bit;

the information bit positions are added to the parity equation for the second parity bit with the probability P.

3. The polar code coding method according to claim 1, wherein the check equation of any one of the first check bits contains a check relation of a previous first check bit.

4. The polar code coding method according to claim 3, wherein generating the parity equation for the first parity bit comprises:

dividing a sequence formed by the first check bits into s segments; wherein: s is a non-zero natural number;

and adding the first check bit corresponding to the previous check bit position to the check equation of the first check bit corresponding to each check bit position of any section.

5. The method for polar code coding according to claim 4, wherein after the adding the first parity bit corresponding to the previous parity bit position, further comprising:

setting an information bit position interval as an interval p; wherein the interval p is a prime number;

for any first check bit, selecting an information bit position which is before the check bit position of the first check bit and has a check interval with the first check bit being a multiple of the interval p;

and adding the information bit corresponding to the information bit position into a check equation of the first check bit.

6. The method for polar code coding according to claim 5, wherein after the adding the first parity bit corresponding to the previous parity bit position, further comprising:

counting the information bit position before the ith check bit position;

arranging the information bit positions from small to large according to the position sequence numbers to obtain a sequence Iindex formed by information bits, wherein the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1);

configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize;

and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

7. The method for coding polar codes according to claim 6, wherein the adding information bits on the position sequence number a to the check equation according to the size relationship between the position sequence number a and the length Isize comprises:

when the position serial number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iindex is not marked, adding the a-th information bit in the sequence Iindex into a check equation of the i-th check bit, marking, self-adding (q-i +1) the position serial number a, and repeating the judging of the size relationship between the position serial number a and the length Isize; if the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i = q.

8. The method for polar code coding according to claim 1, wherein the separately determining the information bit positions, the check bit positions and the frozen bit positions comprises:

acquiring the length K of a required information bit, the length M of a required polarization code and the length N of a corresponding polarization code mother code;

sequencing N bit channels from low to high according to the reliability to obtain a sequence Q;

determining a punching position T;

splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: k;

determining a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, wherein n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin are provided;

determining the number Fp of the check bit positions;

judging the size of the number n and the number Fp of the positions with the minimum row weight dmin, determining the Fp position with the row weight dmin and the best reliability of the corresponding generating matrix in the third subsequence as the check bit position when n > Fp, and determining the position with (Fp + n)/2 row weights dmin in the third subsequence and the position with (Fp-n)/2 row weights 2dmin in the third subsequence as the check bit position when n is less than or equal to Fp;

marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions;

and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

9. The method for coding a polar code according to claim 1, wherein the processing the soft information of the bits of the polar code codeword by using the successive cancellation list decoding algorithm to obtain the decoding result comprises:

determining the bit value of each position according to the mapping relation between the position attribute of each bit position and the bit value to form a plurality of candidate code words and form a candidate code word list;

when the second check bit number is not 0, performing parity check on each candidate code word by adopting the second check bit, and calculating the reliability of all candidate code words in the candidate code word list; selecting the candidate code word which has the maximum reliability and can pass the second check bit check as a decoding result; and when the second check bit number is 0, selecting the candidate code word with the maximum reliability as a decoding result.

10. The method for polar code coding according to claim 9, wherein the determining the bit value of each bit position according to the mapping relationship between the position attribute and the bit value of each bit position comprises:

when the current bit position is the frozen bit position, determining that the bit value at the position is 0, when the current bit position is the information bit position or the position corresponding to the second check bit, equally dividing the bit value at the position into two values, namely 0 and 1, and when the current bit position is the position corresponding to the first check bit, calculating the value of the first check bit according to a check equation of the first check bit to be used as the bit value at the position.

11. An apparatus for polar code coding, comprising:

a second determining unit adapted to determine an information bit position, a check bit position and a frozen bit position, respectively;

a marking unit, adapted to sort the parity bit positions according to reliability, select x parity bit positions from the smallest reliability, mark parity bit positions other than the x selected parity bit positions as first parity bits, and mark the x parity bit positions as second parity bits; wherein: the first parity bits are adapted for decoding, the second parity bits are adapted for picking a decoding path, and 0< x ≦ (number of parity bit positions);

a third generating unit adapted to generate a check equation of the first check bit;

a fourth generating unit adapted to generate a parity equation for the second parity bit; wherein: adding the information bits at the information bit positions to a check equation of the second check bits with a random probability;

a second generating unit adapted to generate the first parity bit according to a parity equation of the first parity bit;

a fifth generating unit, adapted to configure the second parity bits at the x parity bit positions, configure the first parity bits at parity bit positions other than the x parity bit positions, and obtain an information source sequence, configure information bits in the information source sequence at the information bit positions, and configure the frozen bit positions, thereby generating a polar code input bit sequence;

the second coding unit is suitable for carrying out polarization code coding on the polarization code input bit sequence to obtain a polarization code codeword;

the second modulation unit is suitable for mapping the polar code words into modulation signals and transmitting the modulation signals through a channel;

the second demodulation unit is suitable for demodulating the transmitted modulation signal to obtain the soft information of the bits of the transmitted polarization code words;

and the second decoding unit is suitable for processing the soft information of the bits of the polar code words by adopting a continuous offset list decoding algorithm to obtain a decoding result.

12. The apparatus for polar code coding according to claim 11, wherein the fourth generating unit is adapted to set a corresponding random probability P (0< P <1) for any one of the second parity bits; the information bit positions are added to the parity equation for the second parity bit with the probability P.

13. The apparatus for polar code coding according to claim 11, wherein the check equation of any one of the first check bits contains a check relation of a previous first check bit.

14. The apparatus for polar code coding according to claim 13, wherein the third generating unit is adapted to divide the sequence of the first check bits into s segments; wherein: s is a non-zero natural number; and adding the first check bit corresponding to the previous check bit position to the check equation of the first check bit corresponding to each check bit position of any section.

15. The apparatus for polar code coding according to claim 14, wherein the third generating unit is adapted to set an information bit position interval to an interval p after the adding of the first parity bit corresponding to the previous parity bit position; wherein the interval p is a prime number; for any first check bit, selecting an information bit position which is before the check bit position of the first check bit and has a check interval with the first check bit being a multiple of the interval p; and adding the information bit corresponding to the information bit position into a check equation of the first check bit.

16. The apparatus for polar code coding according to claim 14, wherein the third generating unit is further adapted to count information bit positions before an i-th check bit position; arranging the information bit positions from small to large according to the position sequence numbers to obtain a sequence Iindex formed by information bits, wherein the length of the sequence Iindex is Isize; wherein: 0< i < (q + 1); configuring an initial value a of the position serial number as i, and judging the size relationship between the position serial number a and the length Isize; and correspondingly adding the information bits on the position serial number a into a check equation according to the size relation between the position serial number a and the length Isize.

17. The apparatus for polar code coding according to claim 16, wherein the third generating unit is adapted to add the a-th information bit in the sequence Iindex to a parity equation of the i-th parity bit and mark it, and self-add the position sequence number a by (q-i +1), and repeat the determining the size relationship of the position sequence number a to the length Isize, when the position sequence number a ≦ Isize and the information bit at the a-th information bit position in the sequence Iindex is not marked; if the position sequence number a is not more than Isize, and the information bit at the a-th information bit position in the sequence Iidedex is marked, superposing (q-i +1) the position sequence number a, and continuously repeating the steps to judge the size relationship between the position sequence number a and the length Isize; when the position serial number a is larger than Isize, increasing i by 1; until i = q.

18. The apparatus for encoding and decoding polar codes according to claim 11, wherein the second determining unit is adapted to obtain a length K of a required information bit, a length M of a required polar code, and a length N of a corresponding mother code of a polar code; sequencing N bit channels from low to high according to the reliability to obtain a sequence Q; determining a punching position T; splitting the sequence Q into a first subsequence, a second subsequence and a third subsequence according to the punching position T; wherein: the length of the first subsequence is: (N-M), the length of the second subsequence being: (M-K), the length of the third subsequence being: k; determining a minimum value dmin of row weights of the generator matrices corresponding to the third subsequence, wherein n positions of the generator matrices corresponding to the third subsequence having the minimum row weight dmin are provided; determining the number Fp of the check bit positions; judging the size of the number n and the number Fp of the positions with the minimum row weight dmin, determining the Fp position with the row weight dmin and the best reliability of the corresponding generating matrix in the third subsequence as the check bit position when n > Fp, and determining the position with (Fp + n)/2 row weights dmin in the third subsequence and the position with (Fp-n)/2 row weights 2dmin in the third subsequence as the check bit position when n is less than or equal to Fp; marking K information bit positions on the sequence Q in the order of high reliability and skipping the puncturing positions T and the positions determined as the check bit positions; and marking the rest positions in the sequence Q as the frozen bit positions, selecting positions with the same row weight as the check bit positions from the frozen bit positions, and marking the positions as the check bit positions, wherein the sequence length formed by all the check bit positions is Q.

19. The apparatus for polar code coding according to claim 11, wherein the second decoding unit is adapted to determine the bit value of each bit position according to a mapping relationship between the position attribute and the bit value of each bit position, and form a plurality of candidate codewords to form a candidate codeword list; when the second check bit number is not 0, performing parity check on each candidate code word by adopting the second check bit, and calculating the reliability of all candidate code words in the candidate code word list; selecting the candidate code word which has the maximum reliability and can pass the second check bit check as a decoding result; and when the second check bit number is 0, selecting the candidate code word with the maximum reliability as a decoding result.

20. The apparatus for polar code encoding according to claim 19, wherein the second decoding unit is adapted to determine that the bit value at the position is 0 when the current bit position is a frozen bit position, divide the bit value at the position into two, i.e. 0 and 1, when the current bit position is an information bit position or a position corresponding to the second parity bit, and calculate the value of the first parity bit as the bit value at the position according to the check equation of the first parity bit when the current bit position is the position corresponding to the first parity bit.