CN108631936A

CN108631936A - The method and device of polarization code compiling

Info

Publication number: CN108631936A
Application number: CN201710185923.2A
Authority: CN
Inventors: 徐旻子; 樊婷婷; 徐志昆
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2017-03-24
Filing date: 2017-03-24
Publication date: 2018-10-09
Anticipated expiration: 2037-03-24
Also published as: CN110519012B; CN110519012A; CN108631936B

Abstract

A kind of method and device of polarization code compiling, the method includes：Information bit position, check bit position are determined respectively and freeze bit position；Generate the check equations of each check bit；Wherein：The check equations of each check bit include the verification relationship of previous check bit；Check bit is generated according to the check equations；Generate polarization code input bit sequence；Polarization code coding is carried out to the polarization code input bit sequence, obtains polarization code code word；The polarization code code word is mapped to modulated signal, and is transmitted by channel；Modulated signal of the demodulation by transmission obtains the Soft Inform ation of the bit of the polarization code code word by transmission；Using the continuous Soft Inform ation offset list decoding and handle the bit of the polarization code code word, decoding result is obtained.Using the above scheme, the frame error rate of polarization code compiling can be reduced.

Description

The method and device of polarization code compiling

Technical field

The present embodiments relate to the method and devices that the communications field more particularly to a kind of polarization code compile.

Background technology

It is currently, there are the Compilation Method of two kinds of polarization codes, the respectively polarization code (Parity- of parity check code auxiliary Check Polar Code, PC-polar) Compilation Method and cyclic redundancy check auxiliary polarization code (Cyclic Redundancy CheckPolar Code, CRC-polar) Compilation Method.

The flow of the Compilation Method of PC-polar is：Information sequence is placed on the larger position of bit channel capacity first, Further according to the position distribution computation of parity bits value of information bit, information sequence and check bit are sent into polarization code coder, When decoding, is decoded and calculated using the continuous counteracting list (Successive Cancellation List, SCL) of even-odd check auxiliary Method decodes, and the decoding of check bit is calculated by carrying out identical verify to the information bit that has translated.

The flow of the Compilation Method of CRC-polar is：Information sequence is subjected to CRC codings first, then by information sequence and The CRC check bit that CRC codings generate is sent into polarization code coder together, using the SCL decoding algorithms of CRC auxiliary when decoding, In the code word in decoding last pick-list, all candidate codewords are first reduced into the candidate information sequence containing CRC, to institute There is candidate information sequence to do CRC processing, will be handled by CRC and the highest candidate information sequence of reliability is used as final translate Code result.

But in existing polarization code Compilation Method, but both Compilation Methods have that frame error rate is excessively high.

Invention content

The embodiment of the present invention solves the problems, such as it is how to reduce the frame error rate of polarization code compiling.

To solve the above problems, an embodiment of the present invention provides a kind of method of polarization code compiling, the method includes：Point Information bit position, check bit position and bit position Que Ding not be freezed；Generate the check equations of each check bit；Its In：The check equations of each check bit include the verification relationship of previous check bit；School is generated according to the check equations Test bit；The check bit is configured at the check bit position, and obtains source sequence, it will be in the source sequence Information bit is configured at described information bit position, and freezes bit position described in configuration, generates polarization code input bit sequence； Polarization code coding is carried out to the polarization code input bit sequence, obtains polarization code code word；The polarization code code word is mapped to Modulated signal, and be transmitted by channel；Modulated signal of the demodulation by transmission obtains the polarization by transmission The Soft Inform ation of the bit of code code word；Using the continuous soft letter offset list decoding and handle the bit of the polarization code code word Breath obtains decoding result.

Optionally, described to determine information bit position, check bit position respectively and freeze bit position, including：It obtains The length N of the length K of required information bit, required polarization code code length M and corresponding polarization code mother code；N number of bit is believed Road sorts from low to high according to reliability, obtains sequence Q；Determine punch position T；According to the punch position T, by the sequence Q is split as the first subsequence, the second subsequence and third subsequence；Wherein：The length of first subsequence is：(N-M), institute The length for stating the second subsequence is：(M-K), the length of the third subsequence is：K；It determines corresponding to the third subsequence Generator matrix row weight minimum value dmin, and corresponding generator matrix in the third subsequence has minimum row weight The position of dmin has n；Determine the number Fp of the check bit position；Judge the position with minimum row weight dmin The size of number n and number Fp, work as n>It is dmin by the row weight of generator matrix corresponding in the third subsequence and can when Fp By spending Fp best location determination as the check bit position；As n≤Fp, by (the Fp+ in the third subsequence N) the location determination conduct that (Fp-n)/2 row weight in position and the third subsequence that/2 row weight is dmin is 2dmin The check bit position；On the sequence Q, according to the sequence of reliability from high to low, and skip over the punch position T and The position of the check bit position is had determined as, K information bit position is marked；By the rest position in the sequence Q Label freezes to be selected in bit position with the check bit position with identical to freeze bit position from described The position of row weight, is marked as the check bit position, and the sequence length that all check bit positions are constituted is q.

Optionally, the check equations for generating each check bit, including：By the verification on the check bit position The sequence that bit is constituted is divided into s sections；Wherein：S is non-zero natural number；It is right to any one section of each check bit position institute The check bit corresponding to previous check bit position is added in the check equations for the check bit answered.

Optionally, after the check bit being added corresponding to previous check bit position, further include：Setting information Interval p is divided between bit position；Wherein, the interval p is prime number；To any one check bit, it is chosen at the verification ratio The information bit of the multiple of the interval p is divided into before check bit position where special and between the verification of the check bit Position；Information bit corresponding to described information bit position is added to the check equations of the check bit.

Optionally, after the check bit being added corresponding to previous check bit position, further include：Statistics i-th Information bit position before a check bit position obtains the sequence Iindex that information bit is constituted, and the sequence The length of Iindex is Isize；Wherein：0<i<(q+1)；Allocation position serial number initial value a is i, judges position number a and the length Spend the magnitude relationship of Isize；According to the magnitude relationship of the position number a and the length Isize, correspondingly by the position Information bit on serial number a is added to check equations.

Optionally, the magnitude relationship according to the position number a and the length Isize, correspondingly by institute's rheme The information bit set on serial number a is added to check equations, including：As the position number a≤Isize, and the sequence When the information bit on a-th of information bit position in Iindex is not labeled, by a-th of letter in the sequence Iindex Breath bit is added to the check equations of i-th of check bit, and marks, and the position number a is added (q-i+1) certainly, and again The multiple magnitude relationship for carrying out judging position number a and the length Isize；If the position number a≤Isize, and When the information bit on a-th of information bit position in the sequence Iindex has been labeled, the position number a is superimposed (q-i+1), continue to repeat the magnitude relationship for carrying out judging position number a and the length Isize；When the position number A is more than Isize, and i is incremented by 1；Until i=q.

An embodiment of the present invention provides a kind of polarization code compiling method, the method includes：Information bit is determined respectively Position, check bit position and freeze bit position；The check bit position is sorted according to reliability, from the reliable of minimum Degree starts, and picks out x check bit position, the check bit position except the x check bit position that will be singled out Labeled as the first check bit, the x check bit position mark is the second check bit；Wherein：The first verification ratio Spy is suitable for decoding, and second check bit is suitable for selecting decoding path, and 0 ＜ x≤(quantity of the check bit position)； Generate the check equations of first check bit and the second check bit；Wherein：Information ratio on described information bit position Spy is added with random chance to the check equations of second check bit；It is produced according to the check equations of first check bit Raw first check bit；Second check bit is configured at x check bit position, described first is verified Check bit position of the bit configuration except x check bit position, and source sequence is obtained, by the source sequence In information bit be configured at described information bit position, and freeze bit position described in configuring, generate polarization code input bit Sequence；Polarization code coding is carried out to the polarization code input bit sequence, obtains polarization code code word；The polarization code code word is reflected Modulated signal is penetrated into, and is transmitted by channel；Modulated signal of the demodulation by transmission obtains described by the described of transmission The Soft Inform ation of the bit of polarization code code word；The soft of the bit of the polarization code code word is handled using continuous counteracting list decoding Information obtains decoding result.

Optionally, the check equations of second check bit are generated, including：To any one the second check bit, if Set a corresponding random chance P (0<P<1)；Second check bit is added with the probability P in described information bit position Check equations.

Optionally, the check equations of any one of first check bit include the verification of previous first check bit Relationship.

Optionally, the check equations of first check bit are generated, including：First check bit is constituted Sequence is divided into s sections；Wherein：S is non-zero natural number；The first verification corresponding to each check bit position to any one section The first check bit corresponding to previous check bit position is added in the check equations of bit.

Optionally, after first check bit being added corresponding to previous check bit position, further include：Setting Information bit location interval is interval p；Wherein, the interval p is prime number；To any one the first check bit, it is chosen at institute Before stating the check bit position where the first check bit, and be divided between the verification of first check bit it is described between Every the information bit position of the multiple of p；Information bit corresponding to described information bit position is added to first verification The check equations of bit.

Optionally, after first check bit being added corresponding to previous check bit position, further include：Statistics Information bit position before i-th of check bit position；Described information bit position is arranged from small to large according to position number Row obtain the sequence Iindex that information bit is constituted, and the length of the sequence Iindex is Isize；Wherein：0<i<(q+ 1)；Allocation position serial number initial value a is i, judges the magnitude relationship of position number a and the length Isize；According to the position-order The magnitude relationship of number a and the length Isize, correspondingly the information bit on the position number a is added to check equations.

Optionally, described to determine information bit position, check bit position respectively and freeze bit position, including：It obtains The length N of the length K of required information bit, required polarization code code length M and corresponding polarization code mother code；N number of bit is believed Road sorts from low to high according to reliability, obtains sequence Q；Determine punch position T；According to the punch position T, by the sequence Q is split as the first subsequence, the second subsequence and third subsequence；Wherein：The length of first subsequence is：(N-M), institute The length for stating the second subsequence is：(M-K), the length of the third subsequence is：K；It determines corresponding to the third subsequence Generator matrix row weight minimum value dmin, and corresponding generator matrix in the third subsequence has minimum row weight The position of dmin has n；Determine the number Fp of the check bit position；Judge the position with minimum row weight dmin The size of number n and number Fp, work as n>It is dmin by the row weight of generator matrix corresponding in the third subsequence and can when Fp By spending Fp best location determination as the check bit position, as n≤Fp, by (the Fp+ in the third subsequence N) the location determination conduct that (Fp-n)/2 row weight in position and the third subsequence that/2 row weight is dmin is 2dmin The check bit position；On the sequence Q, according to the sequence of reliability from high to low, and skip over the punch position T and The position of the check bit position is had determined as, K information bit position is marked；By the rest position in the sequence Q Label freezes to be selected in bit position with the check bit position with identical to freeze bit position from described The position of row weight, is marked as the check bit position, and the sequence length that all check bit positions are constituted is q.

Optionally, the Soft Inform ation of the bit that the polarization code code word is handled using continuous counteracting list decoding, It is decoded as a result, including：According to the mapping relations of the position attribution of each bit position and bit value, each position is determined The bit value set forms multiple candidate codewords, constitutes candidate codewords list；When the second check bit number is not 0, using second Check bit carries out even-odd check to each candidate codewords, and calculates all candidate codewords in the candidate codewords list Reliability；The candidate codewords that reliability is maximum and can be verified by the second check bit are picked out, as decoding result；When second When check bit number is 0, the maximum candidate codewords of reliability are picked out, as decoding result.

Optionally, the mapping relations of the position attribution and bit value of each bit position of the basis determine described each The bit value of position, including：When current bit position is to freeze bit position, determine that the bit value on the position is 0, It, will be on the position when the position corresponding to current bit position is information bit position or second check bit Bit value is divided into 0 and 1 two, when current bit position is the position corresponding to first check bit, according to The value of first check bit is calculated in the check equations of first check bit, as the bit on the position Value.

An embodiment of the present invention provides a kind of device of polarization code compiling, described device includes：First determination unit, is suitable for Information bit position, check bit position are determined respectively and freeze bit position；First generation unit is suitable for generating each verification The check equations of bit；Wherein：The check equations of each check bit include the verification relationship of previous check bit；First production Raw unit is suitable for generating check bit according to the check equations；Second generation unit, suitable for the check bit to be configured at The check bit position, and source sequence is obtained, the information bit in the source sequence is configured at described information bit Position, and freeze bit position described in configuration, generate polarization code input bit sequence；First coding unit is suitable for the pole Change code input bit sequence and carry out polarization code coding, obtains polarization code code word；First modulation unit is suitable for the polarization code code Word is mapped to modulated signal, and is transmitted by channel；First demodulating unit is suitable for demodulating the modulated signal by transmission, Obtain the Soft Inform ation of the bit of the polarization code code word by transmission；First decoding unit is suitable for offsetting using continuous List decoding handles the Soft Inform ation of the bit of the polarization code code word, obtains decoding result.

Optionally, first determination unit is suitable for obtaining length K, the required polarization code code of required information bit The length N of long M and corresponding polarization code mother code；N number of bit channel is sorted from low to high according to reliability, obtains sequence Q；Really Determine punch position T；According to the punch position T, the sequence Q is split as the first subsequence, the second subsequence and third Sequence；Wherein：The length of first subsequence is：(N-M), the length of second subsequence is：(M-K), the third The length of subsequence is：K；Determine the minimum value dmin of the row weight of the generator matrix corresponding to the third subsequence, and in institute Stating generator matrix corresponding in third subsequence, there is the position of minimum row weight dmin to have n；Determine the check bit position The number Fp set；Judge the size with position the number n and number Fp of minimum row weight dmin, works as n>It, will be described when Fp The Fp location determination that the row weight of corresponding generator matrix is dmin in third subsequence and reliability is best is as the school Test bit position；As n≤Fp, the position for dmin and the third by (Fp+n)/2 row weight in the third subsequence (Fp-n)/2 row weight in subsequence is the location determination of 2dmin as the check bit position；On the sequence Q, According to the sequence of reliability from high to low, and skips over the punch position T and have determined as the position of the check bit position It sets, marks K information bit position；Rest position in the sequence Q is marked to freeze bit position, and from institute It states and freezes selection and position of the check bit position with weight of mutually going together in bit position, be marked as the check bit position It sets, the sequence length that all check bit positions are constituted is q.

Optionally, first generation unit, suitable for the sequence for being constituted the check bit on the check bit position Row are divided into s sections；Wherein：S is non-zero natural number；The check bit corresponding to each check bit position to any one section The check bit corresponding to previous check bit position is added in check equations.

Optionally, first generation unit is further adapted in the verification being added corresponding to previous check bit position After bit, interval p is divided between setting information bit position；Wherein, the interval p is prime number；To any one check bit, Check bit position where being chosen at the check bit is divided into the interval p before and between the verification of the check bit Multiple information bit position；Information bit corresponding to described information bit position is added to the school of the check bit Proved recipe journey.

Optionally, first generation unit is further adapted in the verification being added corresponding to previous check bit position After bit, the information bit position before i-th of check bit position is counted, the sequence that information bit is constituted is obtained Iindex, and the length of the sequence Iindex is Isize；Wherein：0<i<(q+1)；Allocation position serial number initial value a is i, is judged The magnitude relationship of position number a and the length Isize；It is closed according to the size of the position number a and length Isize System, correspondingly the information bit on the position number a is added to check equations.

Optionally, first generation unit is suitable for working as the position number a≤Isize, and in the sequence Iindex A-th of information bit position on information bit it is not labeled when, a-th of information bit in the sequence Iindex is added Enter to the check equations of i-th of check bit, and mark, and by the position number a from plus (q-i+1), and repeat it is described into Row judges the magnitude relationship of position number a and the length Isize；If the position number a≤Isize, and the sequence When the information bit on a-th of information bit position in Iindex has been labeled, the position number a is superimposed (q-i+1), Continue to repeat the magnitude relationship for carrying out judging position number a and the length Isize；When the position number a is more than I is incremented by 1 by Isize；Until i=q.

An embodiment of the present invention provides a kind of device of polarization code compiling, described device includes：Second determination unit, is suitable for Information bit position, check bit position are determined respectively and freeze bit position；Marking unit is suitable for the check bit position It sets and sorts according to reliability, since minimum reliability, pick out x check bit position, the x school that will be singled out The check bit position mark tested except bit position is the first check bit, and the x check bit position mark is second Check bit；Wherein：First check bit is suitable for decoding, and second check bit is suitable for selecting decoding path, and 0 ＜ X≤(quantity of the check bit position)；Third generation unit is suitable for generating the check equations of first check bit； 4th generation unit is suitable for generating the check equations of second check bit；Wherein：Information on described information bit position Bit is added with random chance to the check equations of second check bit；Second generates unit, is suitable for according to described first The check equations of check bit generate first check bit；5th generation unit, suitable for matching second check bit It is placed in x check bit position, first check bit is configured at the verification except x check bit position Bit position, and source sequence is obtained, the information bit in the source sequence is configured at described information bit position, and match Freeze bit position described in setting, generates polarization code input bit sequence；Second coding unit is suitable for inputting ratio to the polarization code Special sequence carries out polarization code coding, obtains polarization code code word；Second modulation unit, suitable for the polarization code code word is mapped to tune Signal processed, and be transmitted by channel；Second demodulating unit is suitable for demodulating the modulated signal by transmission, obtains the warp Cross the Soft Inform ation of the bit of the polarization code code word of transmission；Second decoding unit is suitable for calculating using continuous list decoding of offsetting Method handles the Soft Inform ation of the bit of the polarization code code word, obtains decoding result.

Optionally, the 4th generation unit is suitable for any one the second check bit, and setting one is corresponding random Probability P (0<P<1)；The check equations of second check bit are added with the probability P for described information bit position.

Optionally, the third generation unit, the sequence suitable for being constituted first check bit are divided into s sections；Its In：S is non-zero natural number；The verification side of the first check bit corresponding to each check bit position to any one section The first check bit corresponding to previous check bit position is added in journey.

Optionally, the third generation unit is suitable in first school being added corresponding to previous check bit position It tests after bit, interval p is divided between setting information bit position；Wherein, the interval p is prime number；To any one the first school Test bit, be chosen at before the check bit position where first check bit, and with first check bit The information bit position of the multiple of the interval p is divided between verification；Information bit corresponding to described information bit position is added Enter to the check equations of first check bit.

Optionally, the third generation unit is further adapted for counting the information bit position before i-th of check bit position It sets；Described information bit position is arranged from small to large according to position number, obtains the sequence Iindex that information bit is constituted, And the length of the sequence Iindex is Isize；Wherein：0<i<(q+1)；Allocation position serial number initial value a is i, judges position-order The magnitude relationship of number a and the length Isize；According to the magnitude relationship of the position number a and the length Isize, accordingly Information bit on the position number a is added to check equations on ground.

Optionally, the third generation unit is suitable for working as the position number a≤Isize, and in the sequence Iindex A-th of information bit position on information bit it is not labeled when, a-th of information bit in the sequence Iindex is added Enter to the check equations of i-th of check bit, and mark, and by the position number a from plus (q-i+1), and repeat it is described into Row judges the magnitude relationship of position number a and the length Isize；If the position number a≤Isize, and the sequence When the information bit on a-th of information bit position in Iindex has been labeled, the position number a is superimposed (q-i+1), Continue to repeat the magnitude relationship for carrying out judging position number a and the length Isize；When the position number a is more than I is incremented by 1 by Isize；Until i=q.

Optionally, second determination unit is suitable for obtaining length K, the required polarization code code of required information bit The length N of long M and corresponding polarization code mother code；N number of bit channel is sorted from low to high according to reliability, obtains sequence Q；Really Determine punch position T；According to the punch position T, the sequence Q is split as the first subsequence, the second subsequence and third Sequence；Wherein：The length of first subsequence is：(N-M), the length of second subsequence is：(M-K), the third The length of subsequence is：K；Determine the minimum value dmin of the row weight of the generator matrix corresponding to the third subsequence, and in institute Stating generator matrix corresponding in third subsequence, there is the position of minimum row weight dmin to have n；Determine the check bit position The number Fp set；Judge the size with position the number n and number Fp of minimum row weight dmin, works as n>It, will be described when Fp The Fp location determination that the row weight of corresponding generator matrix is dmin in third subsequence and reliability is best is as the school Bit position is tested, as n≤Fp, the position for dmin and the third by (Fp+n)/2 row weight in the third subsequence (Fp-n)/2 row weight in subsequence is the location determination of 2dmin as the check bit position；On the sequence Q, According to the sequence of reliability from high to low, and skips over the punch position T and have determined as the position of the check bit position It sets, marks K information bit position；Rest position in the sequence Q is marked to freeze bit position, and from institute It states and freezes selection and position of the check bit position with weight of mutually going together in bit position, be marked as the check bit position It sets, the sequence length that all check bit positions are constituted is q.

Optionally, second decoding unit is suitable for the mapping of the position attribution and bit value according to each bit position Relationship determines the bit value of each position, forms multiple candidate codewords, constitutes candidate codewords list；When the second verification ratio When special number is not 0, even-odd check is carried out to each candidate codewords using the second check bit, and calculate the candidate codewords The reliability of all candidate codewords in list；Pick out the Candidate key that reliability is maximum and can be verified by the second check bit Word, as decoding result；When the second check bit number is 0, the maximum candidate codewords of reliability are picked out, are tied as decoding Fruit.

Optionally, second decoding unit, described in when current bit position is to freeze bit position, determining Bit value on position is 0, when current bit position is the position corresponding to information bit position or second check bit When setting, the bit value on the position is divided into 0 and 1 two, is first check bit in current bit position When corresponding position, the value of first check bit is calculated according to the check equations of first check bit, makees For the bit value on the position.

Compared with prior art, technical scheme of the present invention has the following advantages：

Above-mentioned scheme, since the check equations of each check bit include the verification relationship of previous check bit, therefore Multiple check can be carried out to information bit, mutually can also verify and supplement between check bit, therefore can reduce polarization code volume The frame error rate translated.

Above-mentioned scheme, due to being divided into check bit for the first check bit of decoding and for selecting decoding path The second check bit, and all information bits, random chance participates in the generation of second check bit, therefore can To increase the information bit range of check bit protection, therefore the error floor of polarization code compiling can be reduced.

Further, since the check equations of each check bit also include the verification relationship of previous check bit, The false alarm rate of polarization code compiling can be reduced.

In addition, the verification interval value due to each check bit being arranged different length, can increase verification relationship Randomness, therefore can further reduce polarization code compiling the bit error rate.

Description of the drawings

Fig. 1 is the flow diagram of the Compilation Method of CRC-polar in the prior art；

Fig. 2 is the flow diagram of the Compilation Method of PC-polar in the prior art；

Fig. 3 is a kind of flow diagram of the method for polarization code compiling in the embodiment of the present invention；

Fig. 4 is the relation schematic diagram of a kind of check bit and information bit in the embodiment of the present invention；

Fig. 5 is the schematic diagram of the frame error rate performance obtained using the Compilation Method of polarization code in the embodiment of the present invention；

Fig. 6 is the flow diagram of the method for another polarization code compiling in the embodiment of the present invention；

Fig. 7 is the schematic diagram of the frame error rate performance obtained using the Compilation Method of polarization code in the embodiment of the present invention；

Fig. 8 is the schematic diagram of the false alarm rate performance obtained using the Compilation Method of polarization code in the embodiment of the present invention；

Fig. 9 is the flow diagram of the Compilation Method of another polarization code in the embodiment of the present invention；

Figure 10 is a kind of schematic diagram of female code sequence in the embodiment of the present invention；

Figure 11 is the relation schematic diagram of a kind of check bit to each other in the embodiment of the present invention；

Figure 12 is the relation schematic diagram of another check bit to each other in the embodiment of the present invention；

Figure 13 is a kind of structural schematic diagram of the device of polarization code compiling in the embodiment of the present invention；

Figure 14 is the structural schematic diagram of the device of another polarization code compiling in the embodiment of the present invention.

Specific implementation mode

It is currently, there are the Compilation Method of two kinds of polarization codes, the respectively polarization code (Parity- of parity check code auxiliary Check Polar Code, PC-polar) Compilation Method and cyclic redundancy check auxiliary polarization code (Cyclic Redundancy Check Polar Code, CRC-polar) Compilation Method.

Fig. 1 shows the flow of the Compilation Method of CRC-polar, as shown in Figure 1, the stream of the Compilation Method of CRC-polar Cheng Wei：

The information sequence of input is carried out CRC codings by CRC encoders first, then information sequence and CRC codings are generated CRC check bit is sent into Polar encoders together；Polar encoders generate polarization code code word and export to modulator.

The polarization code code word is mapped to modulated signal by modulator, and is transmitted to demodulator by channel；Demodulation Modulated signal of the device demodulation by transmission, obtains the Soft Inform ation of the bit of the polarization code code word by transmission, input To Polar-CRC joint decoders into row decoding.It is decoded and is calculated using the SCL of CRC auxiliary when Polar-CRC joint decoders decode All candidate codewords are first reduced into the candidate information sequence containing CRC by method in the code word in decoding last pick-list, CRC processing is done to all candidate information sequences, will be handled by CRC and the highest candidate information sequence of reliability is used as finally Decoding result.

Fig. 2 shows the flows of the Compilation Method of PC-polar, as shown in Fig. 2, the flow of the Compilation Method of PC-polar For：

Information sequence is placed on the larger position of bit channel capacity by PC encoders, further according to the position distribution of information bit Computation of parity bits value, send information sequence and check bit into Polar encoders, and polarization code code is generated by Polar encoders Word is simultaneously exported to modulator.

The polarization code code word is mapped to modulated signal by modulator, and is transmitted by channel, demodulator solution menstruation regulating The modulated signal for crossing transmission obtains the Soft Inform ation of the bit of the polarization code code word by transmission, is input to Polar- CRC joint decoders are into row decoding, when Polar-CRC joint decoders decode, using the SCL decoding algorithms of even-odd check auxiliary It decodes, and the decoding of check bit is calculated by carrying out identical verify to the information bit that has translated.

To solve the above problems, the check equations of each check bit in the embodiment of the present invention include previous verification ratio Special verification relationship, therefore multiple check can be carried out for information bit, mutually it can also verify and supplement between check bit, therefore The frame error rate of polarization code compiling can be reduced.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 3 shows a kind of flow diagram of the method for the compiling of polarization code in the embodiment of the present invention, below with reference to Fig. 3 The method is discussed in detail step by step, as shown in figure 3, the method may include following flows：

Step S31：Information bit position, check bit position are determined respectively and freeze bit position.

In specific implementation, on how to determine information bit position, check bit position respectively and freeze bit position, The length K of required information bit, the length N of required polarization code code length M and corresponding polarization code mother code can be obtained first, And then N number of bit channel sorts from low to high according to reliability, sequence Q is obtained, then determines punch position T, then basis The sequence Q is split as the first subsequence, the second subsequence and third subsequence by the punch position T；Wherein：Described The length of one subsequence is：(N-M), the length of second subsequence is：(M-K), the length of the third subsequence is：K.

Then, after fractionation obtains third subsequence, it may be determined that generator matrix corresponding to the third subsequence The minimum value dmin of row weight, and there is corresponding generator matrix in the third subsequence position of minimum row weight dmin to have It n, determines the number Fp of the check bit position, judges the position number n and number Fp with minimum row weight dmin Size.

Specifically, working as n>It is dmin by the row weight of generator matrix corresponding in the third subsequence and can when Fp By spending Fp best location determination as the check bit position；As n≤Fp, by (the Fp+ in the third subsequence N) the location determination conduct that (Fp-n)/2 row weight in position and the third subsequence that/2 row weight is dmin is 2dmin The check bit position.

, can be according to the sequence of reliability from high to low on the sequence Q, and skip over the punch position T and It is determined as the position of the check bit position, marks K information bit position, the rest position in the sequence Q is marked Freeze bit position described in being denoted as, and freezes to select that there is weight of mutually going together with the check bit position in bit position from described Position, be marked as the check bit position, the sequence length that all check bit positions are constituted is q.

Step S32：Generate the check equations of each check bit.

In specific implementation, the check equations of each check bit include the verification relationship of previous check bit.

In specific implementation, the sequence that the check bit on the check bit position is constituted can be divided into s sections, s For non-zero natural number.The check equations of the check bit corresponding to each check bit position to any one section, before addition Check bit corresponding to one check bit position, the check equations of each check bit are generated with this.

In an embodiment of the present invention, during generating the check equations of each check bit, when the previous school of addition It tests after the check bit corresponding to bit position, it can be to be divided into interval p between setting information bit position, then to any one A check bit, be chosen at before the check bit position where the check bit and with the verification interval of the check bit For it is described interval p multiple information bit position, then by the information bit corresponding to described information bit position be added to The check equations of the check bit.

In other words, the school on current bit location can be obtained by carrying out XOR operation to corresponding information bit Test the value of bit.It should be noted that the interval p is prime number.Therefore, the complexity and calculation amount of compiling can be reduced.

To make those skilled in the art more fully understand and realizing that the present invention, Fig. 4 are shown in the embodiment of the present invention A kind of relation schematic diagram of check bit and information bit, p=5, P1, P2, P3 and P4 characterize check bit.As shown in figure 4, filling out Bit position is freezed in the grid expression for filling white, and the grid for filling black indicates information bit position, fills the lattice of gray bar Subrepresentation check bit position, the grid for filling black being connected with curve with the arrow with the grid of filling gray bar, i.e., For participate in the check bit generation information bit, namely filling black grid can be added to filling gray bar grid The check equations of represented check bit.

In order to increase the randomness of verification relationship, further to reduce the bit error rate of polarization code compiling, of the invention another In one embodiment, each check bit can be arranged the verification interval value of different length.

Specifically, can be during generating the check equations of each check bit, when the previous check bit of addition After check bit corresponding to position, the information bit position before i-th of check bit position can also be counted, letter is obtained The sequence Iindex that breath bit is constituted, and the length of the sequence Iindex is Isize, wherein：0<i<(q+1).Then match Seated position serial number initial value a is i, the magnitude relationship of position number a and the length Isize is judged, then according to the position-order The magnitude relationship of number a and the length Isize, correspondingly the information bit on the position number a is added to check equations.

In specific implementation, on how to according to the magnitude relationship of the position number a and the length Isize, accordingly Information bit on the position number a is added to check equations on ground.In detail, can the position number a≤ Isize, and when the information bit on a-th of information bit position in the sequence Iindex is not labeled, by the sequence A-th of information bit in Iindex is added to the check equations of i-th of check bit, and marks, and by the position number a Add (q-i+1), and repeats the magnitude relationship for carrying out judging position number a and the length Isize.If the position-order Number a≤Isize, and when the information bit on a-th of information bit position in the sequence Iindex has been labeled, it will be described Position number a superpositions (q-i+1) continue to repeat the magnitude relationship for carrying out judging position number a and the length Isize； When the position number a be more than Isize, i is incremented by 1；Until i=q.

For example, working as q=4, i=1, Isize=0, in the position number 1>0, i is incremented by 1.

Work as q=4, i=2, Isize=7, the 2nd information in the position number 2≤7, and in the sequence Iindex Information bit on bit position is not labeled, and the 2nd information bit in the sequence Iindex is added to the 2nd and is verified Check equations of bit, and marking, and by the position number 2 plus 3, and repeat it is described judge position number 5 with it is described The magnitude relationship of length 7.On the 5th information bit position in the position number 5≤7, and in the sequence Iindex Information bit is not labeled, and the 5th information bit in the sequence Iindex is added to the verification side of the 2nd check bit Journey, and mark, and by the position number 5 plus 3, and repeat the size pass for carrying out judging position number 8 with the length 7 System.In the position number 8, the position number 8 is more than the length 7, i is incremented by 1.

Work as q=4, i=3, Isize=7, the 3rd information in the position number 3≤7, and in the sequence Iindex Information bit on bit position is not labeled, and the 3rd information bit in the sequence Iindex is added to the 3rd and is verified Check equations of bit, and marking, and by the position number 3 plus 2, and repeat it is described judge position number 5 with it is described The magnitude relationship of length 7.

The information bit on the 5th information bit position in the position number 5≤7, and in the sequence Iindex It has been be labeled that, by the position number 5 plus 2, and repeat the magnitude relationship for carrying out judging position number 7 and the length 7. The information bit on the 7th information bit position in the position number 7≤7, and in the sequence Iindex is not labeled, The 7th information bit in the sequence Iindex is added to the check equations of the 3rd check bit, and is marked, and by institute Position number 7 plus 2 are stated, and repeat the magnitude relationship for carrying out judging position number 9 and the length 7.In the position-order Numbers 9, the position number 9 is more than the length 7, and i is incremented by 1.

Work as q=4, i=4, Isize=8, the 4th information in the position number 4≤8, and in the sequence Iindex Information bit on bit position is not labeled, and the 4th information bit in the sequence Iindex is added to the 4th and is verified Check equations of bit, and marking, and by the position number 4 plus 1, and repeat it is described judge position number 5 with it is described The magnitude relationship of length 8.

The information bit on the 5th information bit position in the position number 5≤8, and in the sequence Iindex It has been be labeled that, by the position number 5 plus 1, and repeat the magnitude relationship for carrying out judging position number 6 and the length 8. The information bit on the 6th information bit position in the position number 6≤8, and in the sequence Iindex is not labeled, The 6th information bit in the sequence Iindex is added to the check equations of the 4th check bit, and is marked, and by institute Position number 6 plus 1 are stated, and repeats the magnitude relationship for carrying out judging position number 7 and the length 8.

The information bit on the 7th information bit position in the position number 7≤8, and in the sequence Iindex It has been be labeled that, by the position number 7 plus 1, and repeat the magnitude relationship for carrying out judging position number 8 and the length 8. The information bit on the 8th information bit position in the position number 8≤8, and in the sequence Iindex is not labeled, The 8th information bit in the sequence Iindex is added to the check equations of the 4th check bit, and is marked, and by institute Position number 8 plus 1 are stated, and repeats the magnitude relationship for carrying out judging position number 9 and the length 8.In the position-order Numbers 9>8, the position number 9 is more than the length 8, and i=q, stops implementing.

Step S33：Check bit is generated according to the check equations.

Step S34：The check bit is configured at the check bit position, and obtains source sequence, by the letter Information bit in source sequence is configured at described information bit position, and freezes bit position described in configuration, and it is defeated to generate polarization code Enter bit sequence.

Step S35：Polarization code coding is carried out to the polarization code input bit sequence, obtains polarization code code word.

Step S36：The polarization code code word is mapped to modulated signal, and is transmitted by channel.

Step S37：Modulated signal of the demodulation by transmission obtains the bit of the polarization code code word by transmission Soft Inform ation.

Step S38：Using the continuous Soft Inform ation offset list decoding and handle the bit of the polarization code code word, obtain Decode result.

In order to compare the frame error rate performance of the embodiment of the present invention, so that those skilled in the art more fully understand and realize The present invention, Fig. 5 show the mistake frame using a kind of check bit of the Compilation Method of polarization code obtained in the embodiment of the present invention Rate performance, abscissa E_b/N₀, indicate that signal-to-noise ratio, longitudinal axis FER indicate frame error rate.It should be noted that be not configured to herein The check bit number of decoding path is selected, and at the same time giving the volume of existing CRC-polar and existing PC-polar The frame error rate performance for the signal of interpretation method obtained, polarization code code length 2000, female code length 2048, information bit length 1000, Code check 0.5, list length 32.It is using accurate uniformly punching (Quasi-uniform puncturing, QUP) method, channel Awgn channel, modulation use quadrature phase shift keying (Quadrature Phase Shift Keying, QPSK) mode.CRC is used 16, generator polynomial 0x18005.The building method of polarization code is Gaussian approximation construction, the signal-to-noise ratio Eb/N0=of construction 1.75dB。

As shown in figure 5, upper trigonometric curve 52 indicates the frame error rate performance of the Polar codes of existing CRC16 auxiliary, lower triangle Curve 51 indicates that the frame error rate performance of existing PC-polar codes, rectangular curve 53 indicate that the PC-polar codes of the present embodiment miss frame Rate performance.It can be seen that after signal-to-noise ratio 1.8dB, one obtained using the Compilation Method of polarization code in the embodiment of the present invention Kind signal has lower frame error rate performance, therefore can also effectively reduce the error floor of original PC-polar codes.

Currently, using the Compilation Method of PC-polar and the Compilation Method of CRC-polar, ask there are frame error rate is excessively high Topic.

And the check equations of each check bit in the embodiment of the present invention include the verification relationship of previous check bit, Therefore multiple check can be carried out to information bit, mutually it can also verify and supplement between check bit, therefore polarization code can be reduced The frame error rate of compiling.

To make those skilled in the art more fully understand and realizing that the present invention, Fig. 6 are shown in the embodiment of the present invention A kind of flow diagram of the method for polarization code compiling, is discussed in detail the method below with reference to Fig. 6 step by step, described Method may include steps of：

S61：Information bit position, check bit position are determined respectively and freeze bit position.

In specific implementation, described to determine information bit position, check bit position respectively and freeze bit position, it wraps It includes：The length K of information bit needed for obtaining, the length N of required polarization code code length M and corresponding polarization code mother code；It will be N number of Bit channel sorts from low to high according to reliability, obtains sequence Q；Determine punch position T；According to the punch position T, by institute It states sequence Q and is split as the first subsequence, the second subsequence and third subsequence；Wherein：The length of first subsequence is： (N-M), the length of second subsequence is：(M-K), the length of the third subsequence is：K.

In specific implementation, after obtaining third subsequence, it may be determined that the generation corresponding to the third subsequence The minimum value dmin of the row weight of matrix, and corresponding generator matrix in the third subsequence has minimum row weight dmin's Position has n；Determine the number Fp of the check bit position；Judge have the minimum row weight dmin position number n with The size of number Fp, works as n>It is dmin and reliability by the row weight of generator matrix corresponding in the third subsequence when Fp Fp best location determination is as the check bit position, as n≤Fp, by (Fp+n)/2 in the third subsequence Described in the location determination that (Fp-n)/2 row weight in position and the third subsequence that a row weight is dmin is 2dmin is used as Check bit position.

In specific implementation, can be on the sequence Q, according to the sequence of reliability from high to low, and skip over described beat Hole site T and the position for having determined as the check bit position mark K information bit position；It will be in the sequence Q Rest position marks to freeze bit position, and freezes selection and the check bit position in bit position from described Position with weight of mutually going together, is marked as the check bit position, the sequence that all check bit positions are constituted Length is q.

S62：The check bit position is sorted according to reliability, since minimum reliability, picks out x verification Bit position, the check bit position mark except the x check bit position that will be singled out are the first check bit, institute It is the second check bit to state x check bit position mark.

In specific implementation, the check bit position can be sorted according to reliability, picks out the x of reliability minimum A check bit position, to be labeled as the second check bit, the verification except the x check bit position that will be singled out Bit position is labeled as the first check bit.Wherein：First check bit is suitable for decoding, and second check bit is suitable for Select decoding path, and 0 ＜ x≤(quantity of the check bit position).

It should be noted that for ease of description, can the first check bit be known as PC, the second check bit is known as PCselect。

S63：Generate the check equations of first check bit and the second check bit；Wherein：Described information bit The information bit set is added with random chance to the check equations of second check bit.

In specific implementation, the process about the check equations for generating second check bit in detail can be right A corresponding random chance P (0 is arranged in any one second check bit<P<1), then described information bit position with institute State the check equations that second check bit is added in probability P.

S64：First check bit is generated according to the check equations of first check bit.

S65：Second check bit is configured at x check bit position, first check bit is matched It is placed in the check bit position except x check bit position, and obtains source sequence, by the letter in the source sequence Bit configuration is ceased in described information bit position, and freezes bit position described in configuration, generates polarization code input bit sequence.

S66：Polarization code coding is carried out to the polarization code input bit sequence, obtains polarization code code word.

S67：The polarization code code word is mapped to modulated signal, and is transmitted by channel.

S68：Modulated signal of the demodulation by transmission obtains the soft of the bit of the polarization code code word by transmission Information.

S69：Using the continuous Soft Inform ation offset list decoding and handle the bit of the polarization code code word, decoded As a result.

In specific implementation, may be used it is continuous offset list decoding handle the polarization code code word bit it is soft Information obtains decoding result.Specifically, can according to the position attribution of each bit position and the mapping relations of bit value, The bit value for determining each position, forms multiple candidate codewords, constitutes candidate codewords list, when the second check bit number not When being 0, even-odd check is carried out to each candidate codewords using the second check bit, and calculate in the candidate codewords list The reliability of all candidate codewords；The candidate codewords that reliability is maximum and can be verified by the second check bit are picked out, as Decode result；When the second check bit number is 0, the maximum candidate codewords of reliability are picked out, as decoding result.

It in an embodiment of the present invention, can be with according to the mapping relations of the position attribution of each bit position and bit value When current bit position is to freeze bit position, determine that the bit value on the position is 0, when current bit position is When position corresponding to information bit position or second check bit, the bit value on the position is divided into 0 and 1 Two, when current bit position is the position corresponding to first check bit, according to first check bit The value of first check bit is calculated in check equations, as the bit value on the position.

In order to compare the error floor performance of the embodiment of the present invention, so that those skilled in the art more fully understand and reality The existing present invention, Fig. 7 show the frame error rate using a kind of signal of the Compilation Method of polarization code obtained in the embodiment of the present invention Performance, and at the same time giving the frame error rate performance for the signal of the coding and decoding method of existing PC-polar obtained.

As shown in fig. 7, abscissa E_b/N₀, indicate that signal-to-noise ratio, longitudinal axis FER indicate frame error rate.Polarization code code length 128, information Bit length 64, code check 0.5, list length 32.Channel is awgn channel, and modulation uses QPSK.Polarization code uses Gaussian approximation structure It makes, the signal-to-noise ratio E of construction_b/N₀=-1.59dB.And the number x that PCselect is arranged is set as 5, selects the 5 of reliability minimum PCselect is arranged in a check bit position, gives random chance P=0.5, each information bit is added with probability 0.5 The parity check equation of PCselect, also, the first check bit herein can be the life according to current PC-Polar codes It is generated at mode.The parity check equation of all PCselect is generated by this rule.

In the figure 7, upper trigonometric curve 72 indicates the frame error rate performance of existing PC-polar codes when x=0, rectangular curve 71 The frame error rate performance of the coding and decoding method using the embodiment of the present invention is indicated, from fig.7, it can be seen that real using the present invention under high s/n ratio Preferable frame error rate performance and error floor performance can be had by applying example and being compiled code.

It is currently, there are the Compilation Method of two kinds of polarization codes, the respectively Compilation Method of PC-polar and the volume of CRC-polar Method is translated, but both Compilation Methods have that frame error rate is excessively high.

And check bit is divided into for the first check bit of decoding and for selecting decoding path by the embodiment of the present invention The second check bit, and all information bits, random chance P are participated in the generation of second check bit, therefore The information bit range of check bit protection can be increased, therefore the error floor of polarization code compiling can be reduced.

In specific implementation, the check equations of any one of first check bit can include previous first verification The verification relationship of bit, therefore multiple check can be carried out, therefore the frame error rate of polarization code compiling can be reduced.And it is possible to drop The false alarm rate of low compiling.

In specific implementation, following steps may be used, to generate the check equations of first check bit.Specifically may be used Think that the sequence for being constituted first check bit is divided into s sections；Wherein：S is non-zero natural number；It is each to any one section The check equations of the first check bit corresponding to a check bit position are added first corresponding to previous check bit position Check bit.

In specific implementation, after first check bit being added corresponding to previous check bit position, may be used also To be divided into interval p between setting information bit position；Wherein, the interval p is prime number, and then to any one the first verification ratio Spy is chosen at before the check bit position where first check bit, and with the verification of first check bit Between be divided into it is described interval p multiple information bit position, finally the information bit corresponding to described information bit position is added Enter to the check equations of first check bit, therefore the calculation amount of cataloged procedure can be reduced.

In order to increase the randomness of verification relationship, to further decrease the frame error rate of compiling, in specific implementation, described It is added after the first check bit corresponding to previous check bit position, can also different length be set to each check bit Verification interval value.

In detail, the information bit position before i-th of check bit position can be counted, then by described information ratio Special position arranges from small to large according to position number, obtains the sequence Iindex that information bit is constituted, and the sequence The length of Iindex is Isize；Wherein：0<i<(q+1), then allocation position serial number initial value a is i, judges position number a and institute The magnitude relationship of length Isize is stated, and then according to the magnitude relationship of the position number a and the length Isize, correspondingly will Information bit on the position number a is added to check equations.

In specific implementation, the magnitude relationship according to the position number a and the length Isize correspondingly will Information bit on the position number a is added to check equations, can implement in accordance with the following steps：It can be in the position-order Number a≤Isize, and when the information bit on a-th of information bit position in the sequence Iindex is not labeled, it will be described A-th of information bit in sequence Iindex is added to the check equations of i-th of check bit, and marks, and by the position Serial number a adds (q-i+1) certainly, and repeats the magnitude relationship for carrying out judging position number a and the length Isize.If institute Position number a≤Isize is stated, and the information bit on a-th of information bit position in the sequence Iindex has been labeled When, the position number a is superimposed (q-i+1), continues to repeat described judge the position number a's and length Isize Magnitude relationship；When the position number a be more than Isize, i is incremented by 1；Until i=q.

In order to compare the false alarm rate performance of the embodiment of the present invention, so that those skilled in the art more fully understand and realize The present invention, Fig. 8 show forthright using a kind of false-alarm of the signal of the Compilation Method of polarization code obtained in the embodiment of the present invention Can, and at the same time giving the existing CRC4-polar scheme performances for selecting decoding path with additional 4 bit CRC, Yi Jixian Some PC-polar schemes, that is, the performance without the PCselsect for selecting path.

As shown in figure 8, upper trigonometric curve 81 indicates the false alarm rate performance of existing CRC4-Polar codes, lower trigonometric curve 82 Indicate that the false alarm rate performance of existing PC-polar codes, rectangular curve 83 indicate the PC-polar false alarm rate performances of the present embodiment. Polarization code code length 64, information bit length 32, code check 0.5, list length 8.Channel is awgn channel, and modulation uses QPSK.Polarization Code is constructed using Gaussian approximation, the Eb/N0=1.25dB of construction.It is equal for counting CRC length used in false alarm rate in three curves It is 16, generator polynomial 0x18005.

And in order to get false alarm rate, part check bit can be configured for statistics false alarm rate, it specifically can be with The information bit position for determining Polar codes, the CRC bit for counting false alarm rate sets, check bit position and freezes bit position, And the reliability set of CRC bit is only second to the reliability of information bit.And in the process for the check equations for generating each check bit In, also check equations are added depending on doing information bit in CRC bits.And the number x of PCselect is set as 3, select reliability most 3 small PC give a random chance P=0.5 as PCselect, each information bit is added with probability 0.5 The parity check equation of PCselect is generated the parity check equation of all PCselect by this rule.It, will after receiving terminal demodulation The Soft Inform ation for receiving sequence is sent into SCL decoders, and CRC is not involved in after decoding is only used for decoding and counts false alarm rate.Verification will be passed through But the code word number of decoding error is denoted as FAerror, and total wrong code word number is frameError.

It is as follows to count false alarm rate False alarm rate formula：

False alarm rate=FAerror/frameError；False alarm rate is the code word by verification but decoding error The ratio of number and total wrong code word number.

In fig. 8, upper trigonometric curve indicates that the performance of the Polar codes of existing CRC4 auxiliary, lower trigonometric curve indicate existing The performance of some PC-polar codes, rectangular curve indicate the performance of the PC-polar codes of the present embodiment, as can see from Figure 8, Using the polarization code Compilation Method in the embodiment of the present invention, there can be better false alarm rate performance.

To make those skilled in the art more fully understand and realizing that the present invention, Fig. 9 are shown in the embodiment of the present invention The flow diagram of the Compilation Method of another polarization code, as shown in figure 9, the method can be implemented in accordance with the following steps：

Step S901：It determines the information bit position of polarization code, check bit position and freezes bit position.

It should be noted that information bit length is K, code length M, female code length is N=2^m, and wherein m is positive integer. In specific implementation, following steps may be used, determine the information bit position of polarization code, check bit position and freeze bit Position.In detail, i.e., the reliability that N number of bit channel is first calculated with Gaussian approximation obtains the reliability of bit channel by low To high sequence Q, punch position T is determined using QUP puncturing schemes.Then sequence Q is divided into three parts, the sequence of highest reliability Row length is K, for ease of description, can the sequence that length is k be become sequence Q, specifically can be schemed with reference chart 10, sequence Q A part of sequence of rightmost in 10.

In specific implementation, each element of sequence Q can correspond to the row of respective element in the generator matrix of polarization code, often 1 number is the row weight of the row in row.Minimum row weight can be found from the sequence of rightmost K length, be denoted as dmin, rightmost N position is shared in the sequence of K length has minimum row weight dmin.

In specific implementation, the number Fp for being set to the positions PC in advance can be calculated according to the following formula：

Fp=ceil (log2 (N*K)/2)；

And it is possible to judge the size of n and Fp, and check bit position is marked according to the magnitude relationship of the two.In detail It says, can be when n be more than Fp, the row weight in flag sequence Q is dmin, and the best Fp position of reliability is as PC；It is no The position and (Fp-n)/2 row weight that then just label (Fp+n)/2 row weight is dmin are the position of 2dmin as PC.

With reference to figure 10, in specific implementation, can turn left according to the sequence of reliability from high to low, namely according to from the right side Sequentially, K information bit is marked, and is skipping the position of punch position T and previous step labeled as PC in labeling process.

In specific implementation, first rest position all can be marked and freezes bit position, then from freezing in bit position The position with the bit positions PC with weight of mutually going together is selected, PC bits are marked as, for ease of description and illustrates, will can in total mark The check bit position length of note is known as q.

Step S902：Generate the verification side of the check bit for selecting decoding path and the check bit for decoding Journey.

It should be noted that the check bit position length marked in total in step S901 is q, check bit position is wanted It is not used in the check bit for being configured to select decoding path, otherwise for the check bit of decoding, therefore be used for generate Before selecting the check bit of decoding path and the check equations for the check bit of decoding, a part can be first sorted out Check bit position is to labeled as the check bit for selecting decoding path.For ease of description, will can be used to select to translate The check bit in code path is recorded as PCselect.

In specific implementation, the reliability for the check bit position that all length is q can be ranked up, picking out can The x PC position minimum by degree, for being labeled as PCselect also, x ＞ 0, and x≤q.

False alarm rate in order to reduce polarization code compiling can randomly be participated in specific implementation with setting information bit In the generation of check bit, to increase the information bit range of check bit protection.In detail, it may be used highdensity strange Even parity check equation configures the verification relationship of PCselect.Highdensity PCselect parity check equations product process can be first To some PCselect, a random chance P (0 is given<P<1), each information bit is added the PCselect's with probability P Parity check equation.Moreover, for different PCselect, different random chance P can also be set, therefore can further be carried High randomness, and then frame error rate can be reduced.

It in specific implementation, can be according to following flow reality when generating the check equations for the check bit of decoding It applies, i.e., the check bit position sequence of q long is divided into s sections of (s first>0), each check bit in every section is added in the section tightly In the check equations of an adjacent check bit thereafter, but this relationship is only applicable to same section of check bit, and every section most The latter check bit and be not involved in next section first check bit check equations.

Specifically can be with reference chart 11, as shown in figure 11, the sequence of entire q length is divided into s sections, respectively paragraph 1, the 2nd Section ... and s sections, the check bit that paragraph 1 includes is P1, P2 ... and Pi, and the 2nd section of check bit for including is P (i+1) ..., the The s sections of check bits for including are ... P (q-1) and Pq.And as unit of section, the check equations packet of the latter check bit in every section Containing previous bit check bit, and the arrow of line is used to be characterized in fig. 11.For example the check equations of P2 include the school of P1 Proved recipe journey, the check equations of Pq include the check equations of P (q-1).But the check equations of P (i+1) do not include the verification of Pi Equation, because the two and being not belonging to same section.

It, in specific implementation, can be to each school to further decrease false alarm rate in order to increase the randomness of verification relationship Test the verification interval value of bit setting different length.In detail, (a) step can be executed：Statistics i-th (0<i<Q+1) a Information bit before check bit, by the ascending arrangement of the position number of information bit, for ease of description, information bit can will be obtained Position sequence be denoted as Iindex, length is denoted as Isize.

(b) step：One initial value a=i is set.

(c) step：And then judge the magnitude relationship of the length of initial value and the position sequence of information bit, work as a<Isize, and If check equations were not added for a-th of information bit in Iindex, a-th of information bit in Iindex can be added to It in the check equations of i check bit, and is marked, then executes (d) step.Specifically, increasing the value of a, a= A+ (q-i+1), and repeat step the (c) step.Namely repeat the position-order of initial value and information bit after judging to increase The magnitude relationship of the length of row, initial value a after increase<Isize, and if a-th of information bit in Iindex be not added When check equations, a-th of information bit in Iindex can be added in the check equations of i-th of check bit, and to its into Then line flag increases the value of a, a=a+ (q-i+1), until i=q.

If a-th of information bit in Iindex is labeled the check equations before being added, increase the value of a, a=a+ (q-i+1), then (c) step can directly be executed.

(d) step：Increase the value of a, a=a+ (q-i+1) repeats (c) step.

In specific implementation, work as a>When Isize, i=i+1 repeats (a) step, until i=q, that is, for institute Some information bit positions carry out (a) step~(d) step.

It in specific implementation, can be with if there is no the participation of information bit position in the check equations of check bit position It is compiled code as bit position is freezed.

In specific implementation, the verification relationship of the bit position obtained by (a) step to (d) step can be with reference chart 12.As shown in figure 12, bit position is freezed in the grid expression for filling white, and the grid for filling black indicates information bit position, The grid for filling grey indicates check bit position, and the grid for the filling grey being connected with the grid of filling black participates in the school The information bit of proved recipe journey.The lines of verification relationship different thicknesses and the actual situation of lines of different check position are distinguish, tool Have check equations between the bit position of the arrow line of identical actual situation and thickness have comprising verification relationship.

As shown in figure 12, I1, I2 ... indicate that information bit, F1, F2 ... expression freeze bit, and P1, P2 ... indicate PC ratios Spy, and PC total number of bits is q=10, due to there is no information bit before P1-P5, as position processing is freezed, correspondingly, decoding When P1-P5 also as freezing position into row decoding.As i=6, the incremental spacing of initial value a=6, a are q-i+1=5, are participated in Ratio peculiar P5, I6, I11 and the I16 that P6 check bits calculate.As i=7, the incremental spacing of initial value a=7, a are q-i+1= 4, therefore participate in ratio peculiar P6, I7 and the I15 of the calculating of P7 check bits.

Step S903：Information bit is placed on information bit position, Parity Check Bits is generated according to check equations, puts In corresponding check bit position, other positions put 0.

In specific implementation, the other positions refer to and freeze bit position, are placed as 0.

Step S904：Source sequence is sent into polarization code coder, generates polarization code code word.

Step S905：According to punching pattern T, polarization code code word is subjected to punching processing, the code word after punching is mapped to Modulation symbol is sent to channel.

Due to the power side that the length of female code sequence is 2, female code directly can be not necessarily the length of required codeword sequence Degree, therefore in specific implementation, polarization code code word can be subjected to punching processing according to punching pattern T.Such as female code sequence length It is 8, required codeword sequence length is 7, then can delete a code word bits by punching.

Step S906：The modulation symbol of transmission passes through channel, the modulation symbol for generating plus making an uproar.

Step S907：Receiving terminal will add the modulation symbol made an uproar to demodulate, and the Soft Inform ation after demodulation is sent into PC auxiliary SCL decoders.

Step S908：The SCL decodings of PC auxiliary.

In specific implementation, the SCL decoded modes of PC auxiliary may include following flow：It can be decoded first according to SCL Algorithm calculates the Soft Inform ation of source sequence successively, and then it is to freeze position to work as the bit, is directly judged to 0.And when the bit is When information bit or the positions PCselect, two decoding paths will be differentiated, the information bit is judged to 0 and 1 respectively.When this When bit is the positions PC of non-PCselect, the value of check bit is calculated according to its check equations.It should be noted that The positions PCselect are with the presence or absence of related with the size of above-mentioned x, and when x is zero, the positions PCselect are not present, and are directly To the check bit decoded.When x is not zero, the positions PCselect are just may determine that, and in the corresponding way into row decoding.

In specific implementation, when particular content due to judging bit position, there are many judging result, for example above-mentioned work as When the bit is information bit or the positions PCselect, two decoding paths will be differentiated, therefore can correspondingly be generated a variety of The combination of judging result can form candidate codewords list, i.e., the combination of all possible judging result.It then can be in candidate In codeword list, even-odd check, the i.e. verification to participating in PCselect are carried out to the x position PCselect of each candidate codewords All positions in equation calculate two He of mould, if mould two and the value equal to this PCselect, verification passes through, and otherwise verifies Do not pass through.

In specific implementation, it can pick out that reliability is maximum, and the Candidate key verified by all PCselect Word is as final decoding result.And if picking out reliability most by the verification of all PCselect without candidate codewords Big candidate codewords are as final decoding result.

To sum up, the embodiment of the present invention, by changing the producing method of check bit, is ensureing on the basis of PC-polar The error floor and false-alarm probability performance of PC-polar and CRC-polar are improved in the case of frame error rate performance.

To make those skilled in the art more fully understand and realizing that the present invention, Figure 13 are shown in the embodiment of the present invention A kind of structural schematic diagram of the device of polarization code compiling, as shown in figure 13, described device may include：First determination unit 131, First generation unit 132, first generates unit 133, the second generation unit 134, the first coding unit 135, the first modulation unit 136, the first demodulating unit 137 and the first decoding unit 138, wherein：

First determination unit 131, suitable for determining information bit position, check bit position respectively and freezing bit position；

First generation unit 132 is suitable for generating the check equations of each check bit；Wherein：The school of each check bit Proved recipe journey includes the verification relationship of previous check bit；

First generates unit 133, is suitable for generating check bit according to the check equations；

Second generation unit 134 suitable for the check bit is configured at the check bit position, and obtains information source sequence Information bit in the source sequence is configured at described information bit position, and freezes bit position described in configuration by row, raw Polarization code input bit sequence；

First coding unit 135 is suitable for carrying out polarization code coding to the polarization code input bit sequence, obtains polarization code Code word；

First modulation unit 136 suitable for the polarization code code word is mapped to modulated signal, and is passed by channel It is defeated；

First demodulating unit 137 is suitable for demodulating the modulated signal by transmission, obtains the polarization by transmission The Soft Inform ation of the bit of code code word；

First decoding unit 138, suitable for using the continuous bit offset list decoding and handle the polarization code code word Soft Inform ation, obtain decoding result.

To sum up, in the check equations for each check bit that the first generation unit 132 in the embodiment of the present invention is generated Include the verification relationship of previous check bit, therefore multiple check can be carried out for each check bit, then between check bit Mutually it can verify and supplement, therefore the frame error rate of polarization code compiling can be reduced.

In specific implementation, first determination unit 131, be suitable for obtaining needed for information bit length K, required The length N of polarization code code length M and corresponding polarization code mother code；N number of bit channel is sorted from low to high according to reliability, is obtained Sequence Q；Determine punch position T；According to the punch position T, the sequence Q is split as the first subsequence, the second subsequence And third subsequence；Wherein：The length of first subsequence is：(N-M), the length of second subsequence is：(M-K), The length of the third subsequence is：K.

In specific implementation, first determination unit 131 is adapted to determine that the generation square corresponding to the third subsequence The minimum value dmin of the row weight of battle array, and corresponding generator matrix in the third subsequence has the position of minimum row weight dmin It is equipped with n；Determine the number Fp of the check bit position；Judge have the minimum row weight dmin position number n with The size of number Fp, works as n>When Fp, by the row weight of generator matrix corresponding in the third subsequence be dmin and reliability most Fp good location determination is as the check bit position.

In specific implementation, first determination unit 131 is suitable for as n≤Fp, will be in the third subsequence (Fp+n)/2 the location determination that (Fp-n)/2 row weight in row weight is dmin position and the third subsequence is 2dmin As the check bit position；On the sequence Q, according to the sequence of reliability from high to low, and the punching position is skipped over It sets T and has determined as the position of the check bit position, mark K information bit position；By the residue in the sequence Q Position marks to freeze bit position, and freezes to select to have with the check bit position in bit position from described The mutually position of colleague's weight, is marked as the check bit position, the sequence length that all check bit positions are constituted For q.

In specific implementation, first generation unit 132 is suitable for the check bit institute on the check bit position The sequence of composition is divided into s sections；Wherein：S is non-zero natural number；The school corresponding to each check bit position to any one section The check bit corresponding to previous check bit position is added in the check equations for testing bit.

In specific implementation, first generation unit 132, it is right in the previous check bit position institute of the addition to be further adapted for After the check bit answered, interval p is divided between setting information bit position；Wherein, the interval p is prime number；To any one Check bit is divided into before being chosen at the check bit position where the check bit and between the verification of the check bit The information bit position of the multiple of the interval p；Information bit corresponding to described information bit position is added to the school Test the check equations of bit.

In specific implementation, first generation unit 132, it is right in the previous check bit position institute of the addition to be further adapted for After the check bit answered, the information bit position before i-th of check bit position is counted, obtains what information bit was constituted Sequence Iindex, and the length of the sequence Iindex is Isize；Wherein：0<i<(q+1)；Allocation position serial number initial value a is i, Judge the magnitude relationship of position number a and the length Isize；According to the size of the position number a and the length Isize Correspondingly the information bit on the position number a is added to check equations for relationship.

In specific implementation, first generation unit 132 is suitable for working as the position number a≤Isize, and the sequence When the information bit on a-th of information bit position in row Iindex is not labeled, by a-th in the sequence Iindex Information bit is added to the check equations of i-th of check bit, and marks, and the position number a is added (q-i+1) certainly, and Repeat the magnitude relationship for carrying out judging position number a and the length Isize.If the position number a≤Isize, And the information bit on a-th of information bit position in the sequence Iindex is folded the position number a when being labeled Add (q-i+1), continues to repeat the magnitude relationship for carrying out judging position number a and the length Isize；When the position-order Number a is more than Isize, and i is incremented by 1；Until i=q.

To make those skilled in the art more fully understand and realizing that the present invention, Figure 14 are shown in the embodiment of the present invention The structural schematic diagram of the device of another polarization code compiling, as shown in figure 14, described device may include：Second determination unit 141, marking unit 142, third generation unit 143, the 4th generation unit 144, second generate unit 145, the 5th generation unit 146, the second coding unit 147, the second modulation unit 148, the second demodulating unit 149 and the second decoding unit 150, wherein：

Second determination unit 141, suitable for determining information bit position, check bit position respectively and freezing bit position；

Marking unit 142, suitable for the check bit position is sorted according to reliability, since minimum reliability, X check bit position is picked out, the check bit position mark except the x check bit position that will be singled out is the One check bit, the x check bit position mark are the second check bit；Wherein：First check bit is suitable for translating Code, second check bit are suitable for selecting decoding path, and 0 ＜ x≤(quantity of the check bit position)；

Third generation unit 143 is suitable for generating the check equations of first check bit；

4th generation unit 144 is suitable for generating the check equations of second check bit；Wherein：Described information bit Information bit on position is added with random chance to the check equations of second check bit；

Second generates unit 145, is suitable for generating the first verification ratio according to the check equations of first check bit It is special；

5th generation unit 146, suitable for second check bit is configured at x check bit position, by institute The check bit position that the first check bit is configured at except x check bit position is stated, and obtains source sequence, by institute It states the information bit in source sequence and is configured at described information bit position, and freeze bit position described in configuration, generate polarization Code input bit sequence；

Second coding unit 147 is suitable for carrying out polarization code coding to the polarization code input bit sequence, obtains polarization code Code word；

Second modulation unit 148 suitable for the polarization code code word is mapped to modulated signal, and is passed by channel It is defeated；

Second demodulating unit 149 is suitable for demodulating the modulated signal by transmission, obtains the polarization by transmission The Soft Inform ation of the bit of code code word；

Second decoding unit 150, suitable for using the continuous bit offset list decoding and handle the polarization code code word Soft Inform ation, obtain decoding result.

To sum up, check bit is divided into for the first check bit of decoding in the embodiment of the present invention and is decoded for selecting Second check bit in path, and the 4th generation unit 144 generate the second check bit check equations when, by all information Bit is participated in the generation of the check equations of second check bit with random chance, therefore can increase check bit The information bit range of protection, therefore the error floor of polarization code compiling can be reduced.

In specific implementation, the 4th generation unit 144 is suitable for, to any one the second check bit, being arranged one Corresponding random chance P (0<P<1)；The verification of second check bit is added with the probability P for described information bit position Equation.

In order to improve the false alarm rate of polarization code coding/decoding, in specific implementation, any one of first check bit Check equations include the verification relationship of previous first check bit.

In specific implementation, the third generation unit 143, suitable for the sequence point for being constituted first check bit It is s sections；Wherein：S is non-zero natural number；The first check bit corresponding to each check bit position to any one section The first check bit corresponding to previous check bit position is added in check equations.

In specific implementation, the third generation unit 143 is suitable for being added corresponding to previous check bit position described The first check bit after, be divided between setting information bit position interval p；Wherein, the interval p is prime number；To any one A first check bit is chosen at before the check bit position where first check bit, and with first school The information bit position for the multiple for being divided into the interval p is tested between the verification of bit；By the letter corresponding to described information bit position Breath bit is added to the check equations of first check bit.

In specific implementation, the third generation unit 143 is further adapted for counting the letter before i-th of check bit position Cease bit position；Described information bit position is arranged from small to large according to position number, obtains the sequence that information bit is constituted Iindex is arranged, and the length of the sequence Iindex is Isize；Wherein：0<i<(q+1)；Allocation position serial number initial value a is i, is sentenced The magnitude relationship of disconnected position number a and the length Isize；It is closed according to the size of the position number a and length Isize System, correspondingly the information bit on the position number a is added to check equations.

In specific implementation, the third generation unit 143 is suitable for working as the position number a≤Isize, and the sequence When the information bit on a-th of information bit position in row Iindex is not labeled, by a-th in the sequence Iindex Information bit is added to the check equations of i-th of check bit, and marks, and the position number a is added (q-i+1) certainly, and Repeat the magnitude relationship for carrying out judging position number a and the length Isize.

In specific implementation, the third generation unit 143, if it is suitable for the position number a≤Isize, and it is described When the information bit on a-th of information bit position in sequence Iindex has been labeled, the position number a is superimposed (q-i + 1), continue to repeat the magnitude relationship for carrying out judging position number a and the length Isize；When the position number a is big In Isize, i is incremented by 1；Until i=q.

In specific implementation, second determination unit 141, be suitable for obtaining needed for information bit length K, required The length N of polarization code code length M and corresponding polarization code mother code；N number of bit channel is sorted from low to high according to reliability, is obtained Sequence Q；Determine punch position T；According to the punch position T, the sequence Q is split as the first subsequence, the second subsequence And third subsequence；Wherein：The length of first subsequence is：(N-M), the length of second subsequence is：(M-K), The length of the third subsequence is：K.

In specific implementation, second determination unit 141, suitable for that can determine the life corresponding to the third subsequence At the minimum value dmin of the row weight of matrix, and corresponding generator matrix in the third subsequence has minimum row weight dmin Position have n；Determine the number Fp of the check bit position；Judge the position number n with minimum row weight dmin With the size of number Fp, work as n>It is dmin and reliable by the row weight of generator matrix corresponding in the third subsequence when Fp Fp best location determination is spent as the check bit position, as n≤Fp, by (the Fp+ in the third subsequence N) the location determination conduct that (Fp-n)/2 row weight in position and the third subsequence that/2 row weight is dmin is 2dmin The check bit position.

In specific implementation, second determination unit 141 is suitable on the sequence Q, from high to low according to reliability Sequence, and skip over the punch position T and have determined as the position of the check bit position, mark K information bit Position；Rest position in the sequence Q is marked to freeze bit position, and freezes to select in bit position from described Selecting has the position for weight of mutually going together with the check bit position, is marked as the check bit position, all verifications The sequence length that bit position is constituted is q.

In specific implementation, second decoding unit 150 is suitable for position attribution and bit according to each bit position The mapping relations of value determine the bit value of each position, form multiple candidate codewords, constitute candidate codewords list；When When two verification bit numbers are not 0, even-odd check is carried out to each candidate codewords using the second check bit, and described in calculating The reliability of all candidate codewords in candidate codewords list；It is maximum and can be verified by the second check bit to pick out reliability Candidate codewords, as decoding result；When the second check bit number is 0, the maximum candidate codewords of reliability are picked out, as translating Code result.

In specific implementation, second decoding unit 150, suitable for being to freeze bit position in current bit position When, determine that the bit value on the position is 0, when current bit position is information bit position or second check bit When corresponding position, the bit value on the position is divided into 0 and 1 two, is described in current bit position When position corresponding to one check bit, the first verification ratio is calculated according to the check equations of first check bit Special value, as the bit value on the position.

One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can It is completed with instructing relevant hardware by program, which can be stored in computer readable storage medium, to store Medium may include：ROM, RAM, disk or CD etc..

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of method of polarization code compiling, which is characterized in that including：

Information bit position, check bit position are determined respectively and freeze bit position；

Generate the check equations of each check bit；Wherein：The check equations of each check bit include previous check bit Verification relationship；

Check bit is generated according to the check equations；

The check bit is configured at the check bit position, and obtains source sequence, by the letter in the source sequence Bit configuration is ceased in described information bit position, and freezes bit position described in configuration, generates polarization code input bit sequence；

Polarization code coding is carried out to the polarization code input bit sequence, obtains polarization code code word；

The polarization code code word is mapped to modulated signal, and is transmitted by channel；

Modulated signal of the demodulation by transmission obtains the Soft Inform ation of the bit of the polarization code code word by transmission；

Using the continuous Soft Inform ation offset list decoding and handle the bit of the polarization code code word, decoding result is obtained.

2. the method for polarization code compiling as described in claim 1, which is characterized in that the information bit position determining respectively, Check bit position and freeze bit position, including：

The length K of information bit needed for obtaining, the length N of required polarization code code length M and corresponding polarization code mother code；

N number of bit channel is sorted from low to high according to reliability, obtains sequence Q；

Determine punch position T；

According to the punch position T, the sequence Q is split as the first subsequence, the second subsequence and third subsequence；Its In：The length of first subsequence is：(N-M), the length of second subsequence is：(M-K), the third subsequence Length is：K；

Determine the minimum value dmin of the row weight of the generator matrix corresponding to the third subsequence, and in the third subsequence There is corresponding generator matrix the position of minimum row weight dmin to have n；

Determine the number Fp of the check bit position；

Judge the size with position the number n and number Fp of minimum row weight dmin, works as n>When Fp, by the sub- sequence of the third The Fp location determination that the row weight of corresponding generator matrix is dmin in row and reliability is best is as the check bit position It sets；As n≤Fp, in the position and the third subsequence for being dmin by (Fp+n)/2 row weight in the third subsequence (Fp-n)/2 row weight be 2dmin location determination as the check bit position；

On the sequence Q, according to the sequence of reliability from high to low, and skips over the punch position T and have determined as institute The position of check bit position is stated, K information bit position is marked；

Rest position in the sequence Q is marked to freeze bit position, and freezes to select in bit position from described Selecting has the position for weight of mutually going together with the check bit position, is marked as the check bit position, all verifications The sequence length that bit position is constituted is q.

3. the method for polarization code compiling as claimed in claim 2, which is characterized in that the verification for generating each check bit Equation, including：

The sequence that check bit on the check bit position is constituted is divided into s sections；Wherein：S is non-zero natural number；

The check equations of the check bit corresponding to each check bit position to any one section, are added previous check bit Check bit corresponding to position.

4. the method for polarization code compiling as claimed in claim 3, which is characterized in that previous check bit position is added described After corresponding check bit, further include：

Interval p is divided between setting information bit position；Wherein, the interval p is prime number；

To any one check bit, be chosen at before the check bit position where the check bit and with the verification ratio The information bit position of the multiple of the interval p is divided between special verification；

Information bit corresponding to described information bit position is added to the check equations of the check bit.

5. the method for polarization code compiling as claimed in claim 3, which is characterized in that previous check bit position is added described After corresponding check bit, further include：

The information bit position before i-th of check bit position is counted, the sequence Iindex that information bit is constituted is obtained, and The length of the sequence Iindex is Isize；Wherein：0<i<(q+1)；

Allocation position serial number initial value a is i, judges the magnitude relationship of position number a and the length Isize；

According to the magnitude relationship of the position number a and the length Isize, correspondingly by the information on the position number a Bit is added to check equations.

6. the method for polarization code compiling as claimed in claim 5, which is characterized in that described according to the position number a and institute The magnitude relationship of length Isize is stated, correspondingly the information bit on the position number a is added to check equations, including：

The information bit on a-th of information bit position as the position number a≤Isize, and in the sequence Iindex When not labeled, a-th of information bit in the sequence Iindex is added to the check equations of i-th of check bit, and Label, and by the position number a from plus (q-i+1), and repeat described to carry out judging position number a and the length Isize Magnitude relationship；If the position number a≤Isize, and on a-th of information bit position in the sequence Iindex When information bit has been labeled, the position number a is superimposed (q-i+1), continue to repeat it is described judge position number a and The magnitude relationship of the length Isize；When the position number a be more than Isize, i is incremented by 1；Until i=q.

7. a kind of method of polarization code compiling, which is characterized in that including：

The check bit position is sorted according to reliability, since minimum reliability, picks out x check bit position It sets, the check bit position mark except the x check bit position that will be singled out is the first check bit, and the x is a Check bit position mark is the second check bit；Wherein：First check bit is suitable for decoding, second check bit Suitable for selecting decoding path, and 0 ＜ x≤(quantity of the check bit position)；

Generate the check equations of first check bit and the second check bit；Wherein：Letter on described information bit position Breath bit is added with random chance to the check equations of second check bit；

First check bit is generated according to the check equations of first check bit；

Second check bit is configured at x check bit position, first check bit is configured at the x Check bit position except a check bit position, and source sequence is obtained, the information bit in the source sequence is matched It is placed in described information bit position, and freezes bit position described in configuration, generates polarization code input bit sequence；

8. the method for polarization code compiling as claimed in claim 7, which is characterized in that generate the verification of second check bit Equation, including：

To any one the second check bit, a corresponding random chance P (0 is set<P<1)；

The check equations of second check bit are added with the probability P for described information bit position.

9. the method for polarization code compiling as claimed in claim 7, which is characterized in that any one of first check bit Check equations include the verification relationship of previous first check bit.

10. the method for polarization code compiling as claimed in claim 9, which is characterized in that generate the school of first check bit Proved recipe journey, including：

The sequence that first check bit is constituted is divided into s sections；Wherein：S is non-zero natural number；

The check equations of the first check bit corresponding to each check bit position to any one section, are added previous verification The first check bit corresponding to bit position.

11. the method for polarization code compiling as claimed in claim 9, which is characterized in that previous check bit position is added described After setting the first corresponding check bit, further include：

To any one the first check bit, it is chosen at before the check bit position where first check bit, and The information bit position of the multiple of the interval p is divided between verification with first check bit；

Information bit corresponding to described information bit position is added to the check equations of first check bit.

12. the method for polarization code compiling as claimed in claim 11, which is characterized in that previous check bit position is added described After setting the first corresponding check bit, further include：

Count the information bit position before i-th of check bit position；

Described information bit position is arranged from small to large according to position number, obtains the sequence that information bit is constituted Iindex, and the length of the sequence Iindex is Isize；Wherein：0<i<(q+1)；

13. the method for polarization code as claimed in claim 12 compiling, which is characterized in that it is described according to the position number a with Correspondingly the information bit on the position number a is added to check equations for the magnitude relationship of the length Isize, including：

14. the method for polarization code compiling as claimed in claim 7, which is characterized in that the information bit position determining respectively, Check bit position and freeze bit position, including：

Determine punch position T；

Determine the number Fp of the check bit position；

Judge the size with position the number n and number Fp of minimum row weight dmin, works as n>When Fp, by the sub- sequence of the third The Fp location determination that the row weight of corresponding generator matrix is dmin in row and reliability is best is as the check bit position It sets, as n≤Fp, in the position and the third subsequence for being dmin by (Fp+n)/2 row weight in the third subsequence (Fp-n)/2 row weight be 2dmin location determination as the check bit position；

15. the method for polarization code compiling as claimed in claim 7, which is characterized in that described to offset list decoding using continuous The Soft Inform ation of the bit of polarization code code word described in algorithm process, is decoded as a result, including：According to the position of each bit position The mapping relations of attribute and bit value determine the bit value of each position, form multiple candidate codewords, constitute candidate codewords List；

When the second check bit number is not 0, even-odd check is carried out to each candidate codewords using the second check bit, and Calculate the reliability of all candidate codewords in the candidate codewords list；It picks out reliability maximum and ratio can be verified by second The candidate codewords of spy's verification, as decoding result；When the second check bit number is 0, the maximum Candidate key of reliability is picked out Word, as decoding result.

16. the method for polarization code compiling as claimed in claim 15, which is characterized in that the position of each bit position of basis The mapping relations for setting attribute and bit value determine the bit value of each position, including：It is to freeze in current bit position When bit position, determine that the bit value on the position is 0, when current bit position is information bit position or described second When position corresponding to check bit, the bit value on the position is divided into 0 and 1 two, in current bit position When being the position corresponding to first check bit, described is calculated according to the check equations of first check bit The value of one check bit, as the bit value on the position.

17. a kind of device of polarization code compiling, which is characterized in that including：

First determination unit, suitable for determining information bit position, check bit position respectively and freezing bit position；

First generation unit is suitable for generating the check equations of each check bit；Wherein：The check equations packet of each check bit Verification relationship containing previous check bit；

First generates unit, is suitable for generating check bit according to the check equations；

Second generation unit suitable for the check bit is configured at the check bit position, and obtains source sequence, by institute It states the information bit in source sequence and is configured at described information bit position, and freeze bit position described in configuration, generate polarization Code input bit sequence；

First coding unit is suitable for carrying out polarization code coding to the polarization code input bit sequence, obtains polarization code code word；

First modulation unit suitable for the polarization code code word is mapped to modulated signal, and is transmitted by channel；

First demodulating unit is suitable for demodulating the modulated signal by transmission, obtains the polarization code code word by transmission Bit Soft Inform ation；

First decoding unit, suitable for using the continuous soft letter offset list decoding and handle the bit of the polarization code code word Breath obtains decoding result.

18. the device of polarization code compiling as claimed in claim 17, which is characterized in that first determination unit, suitable for obtaining Take the length K of required information bit, the length N of required polarization code code length M and corresponding polarization code mother code；By N number of bit Channel sorts from low to high according to reliability, obtains sequence Q；Determine punch position T；According to the punch position T, by the sequence Row Q is split as the first subsequence, the second subsequence and third subsequence；Wherein：The length of first subsequence is：(N-M), The length of second subsequence is：(M-K), the length of the third subsequence is：K；Determine that the third subsequence institute is right The minimum value dmin of the row weight for the generator matrix answered, and corresponding generator matrix in the third subsequence has minimum row The position of weight dmin has n；Determine the number Fp of the check bit position；Judge the position with minimum row weight dmin The size of number n and number Fp, work as n>When Fp, by the row weight of generator matrix corresponding in the third subsequence be dmin and Fp best location determination of reliability is as the check bit position；It, will be in the third subsequence as n≤Fp (Fp+n)/2 the location determination that (Fp-n)/2 row weight in row weight is dmin position and the third subsequence is 2dmin As the check bit position；On the sequence Q, according to the sequence of reliability from high to low, and the punching position is skipped over It sets T and has determined as the position of the check bit position, mark K information bit position；By the residue in the sequence Q Position marks to freeze bit position, and freezes to select to have with the check bit position in bit position from described The mutually position of colleague's weight, is marked as the check bit position, the sequence length that all check bit positions are constituted For q.

19. the device of polarization code compiling as claimed in claim 18, which is characterized in that first generation unit, being suitable for will The sequence that check bit on the check bit position is constituted is divided into s sections；Wherein：S is non-zero natural number；To any one section Each check bit position corresponding to check bit check equations, the school corresponding to previous check bit position is added Test bit.

20. the device of polarization code compiling as claimed in claim 19, which is characterized in that first generation unit is further adapted for After the check bit being added corresponding to previous check bit position, interval p is divided between setting information bit position；Its In, the interval p is prime number；To any one check bit, be chosen at check bit position where the check bit it The information bit position of multiple preceding and that the interval p is divided between the verification of the check bit；By described information bit Corresponding information bit is set to be added to the check equations of the check bit.

21. the device of polarization code compiling as claimed in claim 19, which is characterized in that first generation unit is further adapted for After the check bit being added corresponding to previous check bit position, the letter before i-th of check bit position is counted Bit position is ceased, obtains the sequence Iindex that information bit is constituted, and the length of the sequence Iindex is Isize；Wherein： 0<i<(q+1)；Allocation position serial number initial value a is i, judges the magnitude relationship of position number a and the length Isize；According to institute State the magnitude relationship of position number a and the length Isize, correspondingly by the information bit on the position number a be added to Check equations.

22. the device of polarization code compiling as claimed in claim 21, which is characterized in that first generation unit, suitable for working as Position number a≤the Isize, and the information bit on a-th of information bit position in the sequence Iindex is not marked It clocks, a-th of information bit in the sequence Iindex is added to the check equations of i-th of check bit, and is marked, and The position number a is added into (q-i+1) certainly, and repeats the size pass for carrying out judging the position number a and length Isize System；If the position number a≤Isize, and the information bit on a-th of information bit position in the sequence Iindex When being labeled, the position number a is superimposed (q-i+1), continues to repeat described to carry out judging position number a and the length The magnitude relationship of Isize；When the position number a be more than Isize, i is incremented by 1；Until i=q.

23. a kind of device of polarization code compiling, which is characterized in that including：

Second determination unit, suitable for determining information bit position, check bit position respectively and freezing bit position；

Marking unit since minimum reliability, picks out x suitable for sorting according to reliability the check bit position A check bit position, the check bit position mark except the x check bit position that will be singled out are the first verification Bit, the x check bit position mark are the second check bit；Wherein：First check bit is suitable for decoding, described Second check bit is suitable for selecting decoding path, and 0 ＜ x≤(quantity of the check bit position)；

Third generation unit is suitable for generating the check equations of first check bit；

4th generation unit is suitable for generating the check equations of second check bit；Wherein：On described information bit position Information bit is added with random chance to the check equations of second check bit；

Second generates unit, is suitable for generating first check bit according to the check equations of first check bit；

5th generation unit, suitable for second check bit is configured at x check bit position, by first school Check bit position of the bit configuration except x check bit position is tested, and obtains source sequence, by the information source sequence Information bit in row is configured at described information bit position, and freezes bit position described in configuration, generates polarization code and inputs ratio Special sequence；

Second coding unit is suitable for carrying out polarization code coding to the polarization code input bit sequence, obtains polarization code code word；

Second modulation unit suitable for the polarization code code word is mapped to modulated signal, and is transmitted by channel；

Second demodulating unit is suitable for demodulating the modulated signal by transmission, obtains the polarization code code word by transmission Bit Soft Inform ation；

Second decoding unit, suitable for using the continuous soft letter offset list decoding and handle the bit of the polarization code code word Breath obtains decoding result.

24. the device of polarization code as claimed in claim 23 compiling, which is characterized in that the 4th generation unit is suitable for pair A corresponding random chance P (0 is arranged in any one second check bit<P<1)；Described information bit position is with described general The check equations of second check bit are added in rate P.

25. the device of polarization code compiling as claimed in claim 23, which is characterized in that any one of first check bit Check equations include the verification relationship of previous first check bit.

26. the device of polarization code compiling as claimed in claim 25, which is characterized in that the third generation unit, being suitable for will The sequence that first check bit is constituted is divided into s sections；Wherein：S is non-zero natural number；Each verification to any one section The first verification ratio corresponding to previous check bit position is added in the check equations of the first check bit corresponding to bit position It is special.

27. the device of polarization code compiling as claimed in claim 26, which is characterized in that the third generation unit is suitable for It is described to be added after the first check bit corresponding to previous check bit position, interval p is divided between setting information bit position； Wherein, the interval p is prime number；To any one the first check bit, the verification being chosen at where first check bit Before bit position, and it is divided between the verification of first check bit information bit position of the multiple of the interval p； Information bit corresponding to described information bit position is added to the check equations of first check bit.

28. the device of polarization code compiling as claimed in claim 26, which is characterized in that the third generation unit is further adapted for Count the information bit position before i-th of check bit position；By described information bit position according to position number from it is small to Longer spread obtains the sequence Iindex that information bit is constituted, and the length of the sequence Iindex is Isize；Wherein：0<i< (q+1)；Allocation position serial number initial value a is i, judges the magnitude relationship of position number a and the length Isize；According to institute's rheme The magnitude relationship of serial number a and the length Isize are set, correspondingly the information bit on the position number a is added to verification Equation.

29. the device of polarization code compiling as claimed in claim 28, which is characterized in that the third generation unit, suitable for working as Position number a≤the Isize, and the information bit on a-th of information bit position in the sequence Iindex is not marked It clocks, a-th of information bit in the sequence Iindex is added to the check equations of i-th of check bit, and is marked, and The position number a is added into (q-i+1) certainly, and repeats the size pass for carrying out judging the position number a and length Isize System；If the position number a≤Isize, and the information bit on a-th of information bit position in the sequence Iindex When being labeled, the position number a is superimposed (q-i+1), continues to repeat described to carry out judging position number a and the length The magnitude relationship of Isize；When the position number a be more than Isize, i is incremented by 1；Until i=q.

30. the device of polarization code compiling as claimed in claim 23, which is characterized in that second determination unit, suitable for obtaining Take the length K of required information bit, the length N of required polarization code code length M and corresponding polarization code mother code；By N number of bit Channel sorts from low to high according to reliability, obtains sequence Q；Determine punch position T；According to the punch position T, by the sequence Row Q is split as the first subsequence, the second subsequence and third subsequence；Wherein：The length of first subsequence is：(N-M), The length of second subsequence is：(M-K), the length of the third subsequence is：K；Determine that the third subsequence institute is right The minimum value dmin of the row weight for the generator matrix answered, and corresponding generator matrix in the third subsequence has minimum row The position of weight dmin has n；Determine the number Fp of the check bit position；Judge the position with minimum row weight dmin The size of number n and number Fp, work as n>When Fp, by the row weight of generator matrix corresponding in the third subsequence be dmin and Fp best location determination of reliability is as the check bit position, will be in the third subsequence as n≤Fp (Fp+n)/2 the location determination that (Fp-n)/2 row weight in row weight is dmin position and the third subsequence is 2dmin As the check bit position；On the sequence Q, according to the sequence of reliability from high to low, and the punching position is skipped over It sets T and has determined as the position of the check bit position, mark K information bit position；By the residue in the sequence Q Position marks to freeze bit position, and freezes to select to have with the check bit position in bit position from described The mutually position of colleague's weight, is marked as the check bit position, the sequence length that all check bit positions are constituted For q.

31. the device of polarization code compiling as claimed in claim 23, which is characterized in that second decoding unit is suitable for root According to the position attribution of each bit position and the mapping relations of bit value, the bit value of each position is determined, formed multiple Candidate codewords constitute candidate codewords list；When the second check bit number is not 0, using the second check bit to each described Candidate codewords carry out even-odd check, and calculate the reliability of all candidate codewords in the candidate codewords list；It picks out reliable Property the maximum and candidate codewords that can be verified by the second check bit, as decoding result；When the second check bit number is 0, The maximum candidate codewords of reliability are picked out, as decoding result.

32. the device of polarization code compiling as claimed in claim 31, which is characterized in that second decoding unit is suitable for Current bit position is to determine that the bit value on the position is 0, when current bit position is letter when freezing bit position When ceasing the position corresponding to bit position or second check bit, the bit value on the position is divided into 0 and 1 liang It is a, when current bit position is the position corresponding to first check bit, according to the school of first check bit The value of first check bit is calculated in proved recipe journey, as the bit value on the position.