CN110518910A - A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling - Google Patents

A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling Download PDF

Info

Publication number
CN110518910A
CN110518910A CN201910821338.6A CN201910821338A CN110518910A CN 110518910 A CN110518910 A CN 110518910A CN 201910821338 A CN201910821338 A CN 201910821338A CN 110518910 A CN110518910 A CN 110518910A
Authority
CN
China
Prior art keywords
time
channel
quantization
period
interleaved adc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910821338.6A
Other languages
Chinese (zh)
Inventor
李靖
罗建
胡宇峰
宁宁
于奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201910821338.6A priority Critical patent/CN110518910A/en
Publication of CN110518910A publication Critical patent/CN110518910A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10Calibration or testing
    • H03M1/1009Calibration

Abstract

A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling, by reducing the quantization time of current quantisation period corresponding channel or increasing the time span in current quantisation period, so that corresponding channel fulfils quantization ahead of schedule into idle state within the current quantisation period, marking all channels for completing quantization is idle channel, again using task scheduling algorithm in next quantization period come interim, it randomly chooses a channel from all idle channels to be sampled and quantified, to realize channel randomization to optimize interchannel mismatch.The present invention fully utilizes each channel ADC quantized residual time, in the case where additionally not increasing accessory channel, the purpose that random channel can be achieved, is conducive to the spurious-free dynamic range for improving time-interleaved ADC, be also beneficial to improve time-interleaved ADC speed and it is each under the conditions of adaptability.

Description

A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical field, in particular to a kind of time-interleaved ADC of task based access control scheduling Mismatch optimization method.
Background technique
In the interface circuit virtually with real world, analog-digital converter (ADC) is indispensable circuit module, Rapidly and accurately digitized simulation information is particularly important.Therefore, high speed, high-precision ADC become the pass of present information processing Key.In order to improve the operating rate of traditional analog-digital converter, a kind of structure by multiple analog-digital converter parallel operations is mentioned Out, i.e., time-interleaved analog-digital converter (Time-interleaved ADC, TI-ADC), the analog-digital converter of this structure makes The working frequency of each sub-adc converter can be very low, can propose whole speed under time-interleaved working condition It rises.
The structure of one time-interleaved analog-digital converter comprising the channel M is as shown in Figure 1, M is positive integer, time-interleaved mould The single channel of number converter includes that a sampling network and a sub- ADC quantify network, and the working frequency of single channel ADC is Fs/M, it is interleaved come so that entire ADC system is in time-interleaved work by the sampling time for switching each channel sample Working frequency is increased to fs (duty cycle Ts=1/fs) under state, finally by the data in each channel under the sample frequency of fs Sampling, storage and output, to improve the speed of time-interleaved analog-digital converter.Theoretically, time-interleaved analog-digital converter Port number is more, and operating rate can be faster.But between each channel sub-adc converter, there are bandwidth mismatch, sampling time The non-ideal factors such as mismatch, gain mismatch and imbalance mismatch, have seriously affected the dynamic property of entire analog-digital converter.Especially For requiring the occasion of high spurious-free dynamic range (SFDR), if radar uses, the mismatch of interchannel limits the fortune of TI-ADC With.
Many technologies are proposed in existing scheme to solve the various mismatches in TI-ADC, including alignment technique and optimization skill Art.Wherein alignment technique reduces the influence of its bring, such as time mismatch alignment technique etc. by directly reducing amount of mismatch, and Optimisation technique is then that mismatch bring is made to influence to weaken by technological means, and this way does not reduce amount of mismatch, such as random Channel algorithm.For the TI-ADC that a high speed, high linearity require, port number is more, leans on alignment technique only to reach It is highly difficult to requirement, this is because the influence of environmental factor, corrects residual and certainly exist.In order to further decrease residual Mismatch, need optimisation technique cooperation alignment technique be used together.Traditional random channel algorithm, it is desirable that additional channel conduct The selection of random channel, which increase power consumption and areas.
Summary of the invention
For mismatch problems present in time-interleaved ADC, and the method that tradition solves time-interleaved ADC mismatch problems Present in residual mismatch and place the deficiencies of increase additional channels, the present invention propose a kind of the time-interleaved of task based access control scheduling ADC mismatch optimization method, by reduce current quantisation period corresponding channel quantization time or increase the current quantisation period when Between length so that within the current quantisation period corresponding channel fulfil ahead of schedule quantization enter idle state, then using task schedule calculate Method realizes channel randomization to optimize the technology of interchannel mismatch.
The technical solution of the present invention is as follows:
A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling, the time-interleaved ADC includes M channel, M is positive integer, one and only one channel is sampled and quantified within a quantization period of the time-interleaved ADC;
The time-interleaved ADC mismatch optimization method includes the following steps:
Step 1: within each quantization period of the time-interleaved ADC, it is corresponding logical by reducing the current quantisation period The quantization time in road or the time span for increasing the current quantisation period, so that corresponding channel is fulfiled ahead of schedule within the current quantisation period Quantization;
Step 2: all channels for completing quantization of label are idle channel;
Step 3: when time-interleaved ADC next quantization period temporarily, to randomly choose from all idle channels One channel is sampled and is quantified, return step one.
Specifically, reduce the quantization time of current quantisation period corresponding channel in the step 1 method particularly includes: it is logical It crosses prediction algorithm and judges whether corresponding channel is predicted correctly, to predict in the Correct current quantisation period in the current quantisation period Corresponding channel fulfils quantization ahead of schedule.
Specifically, the prediction algorithm method particularly includes: setting voltage window compares when in the time-interleaved ADC The input voltage of device indicates that prediction is correct when being less than voltage window.
Specifically, increase the time span in current quantisation period in the step 1 method particularly includes: keep single channel Operating rate and reduce the sample rate of the time-interleaved ADC.
Specifically, the idle channel in each quantization period internal labeling enters idle channel pond, and in next quantization Period is temporarily randomly choosed a channel from the idle channel pond using randomizer and is sampled and quantified.
The invention has the benefit that by the present invention in that the corresponding channel in the quantization period fulfils quantization ahead of schedule, and One channel of random selection carries out sample quantization from all channels for completing quantization when next quantization period starts, and realizes channel Randomization makes full use of the quantized residual time in each channel, does not increase accessory channel additionally, reduce to optimize interchannel mismatch Power consumption and area improve the spurious-free dynamic range of time-interleaved ADC, additionally improve time-interleaved ADC speed and Adaptability under the conditions of each.
Detailed description of the invention
Time-interleaved ADC principle and various mismatch schematic diagram of the Fig. 1 for the channel M.
Fig. 2 be in embodiment in 7 channel TI-SAR ADC using a kind of task based access control scheduling proposed by the present invention when Between intertexture ADC mismatch optimization method schematic diagram.
Fig. 3 is in embodiment using DAC output voltage schematic diagram before and after prediction algorithm.
Fig. 4 is time-interleaved to use a kind of task based access control proposed by the present invention to dispatch in embodiment in TI-SAR ADC The realization schematic diagram of ADC mismatch optimization method.
Fig. 5 is each logical after time-interleaved ADC mismatch optimization method using a kind of task based access control scheduling proposed by the present invention The working state schematic representation in road.
Specific embodiment
With reference to the accompanying drawing, the present invention is further illustrated by embodiment.
In time-interleaved ADC, usually can by reduce current quantisation period corresponding channel quantization time or increase The time span in current quantisation period is measured currently at this time so that corresponding channel fulfils quantization ahead of schedule within the current quantisation period Change corresponding channel in the remaining time in period and be at wait state, wastes the plenty of time.The present invention is based on task schedules Algorithm, by synchronization completed quantization all channels assign in the group to be sampled such as one, lower a moment sampling when from A channel is randomly choosed in these channels for sampling, then may be implemented random.After single channel fulfils quantization ahead of schedule, by it It is placed in idle channel pond and is used for task scheduling algorithm, this, which does not mean only that, makes channel under the action of task scheduling algorithm Randomization is to optimize interchannel mismatch, also comprising for improving ADC quantization speed and increasing time-interleaved ADC in varying environment Under the conditions of adaptability.
Reduce the quantization time of current quantisation period corresponding channel there are many method, in the present embodiment by taking prediction algorithm as an example It is illustrated.Prediction algorithm and task schedule can combine to realize the reasonable utilization that the time is crushed in ADC quantizing process. After prediction algorithm is added, when the prediction in certain channels is correct, which can fulfil quantization ahead of schedule, then by synchronization All channels for completing quantization are assigned in the group to be sampled such as one, randomly choose one from these channels in the sampling of lower a moment A channel is for sampling.
For prediction algorithm being used in successive approximation analog to digital C (SAR ADC), task scheduling algorithm for prediction when Between intertexture SAR ADC it is highly beneficial.It is very effective especially for bandwidth mismatch, because bandwidth mismatch correction is difficult.It should Algorithm has exchanged excellent linearity performance for part number circuit complexity.Influence single-channel SAR ADC quantization speed because Element, including process corner, supply voltage and temperature have and add under prediction case, also include the type of signal.Task scheduling algorithm has It is used conducive to the time-interleaved SAR ADC high speed for adapting to various conditions.
Below by taking time-interleaved SAR ADC as an example, the feasibility of optimization algorithm is verified.As shown in Fig. 2, in the present embodiment A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling proposed by the present invention is used in 7 channel TI-SAR ADC.In advance Method of determining and calculating makes, and each channel fulfils quantization ahead of schedule and enters random channel pond.Next time, quantization randomly choosed one from random channel pond A channel carries out sample quantization, to realize randomization.The randomization in channel can reduce interchannel mismatch to the shadow of result It rings, to improve the spurious-free dynamic range of ADC.From the aspect of from another, sample rate is can be improved in this method, because each The remaining time in channel is fully utilized.
Prediction algorithm realizes prediction by judging whether signal meets prediction standard, for example makes a decision mark with voltage window Standard, when input enters the window, it is believed that for high-order result it is known that no longer needing to quantify, selection is based on voltage window The concrete mode of prediction mode be for example to take 32 least significant bit LSB as voltage window, when comparator input voltage is small Subsequent quantizing process will be directly skipped in 32 LSB, single-channel SAR ADC, and according to the quantized result of this, is directly negated As non-quantized several below results.As shown in figure 3, the quantization period is reduced to from 7 periods due to the use of prediction algorithm 3 periods.
It is to realize that interchannel loses using prediction algorithm and task schedule in 8 channel time intertexture SAR ADC as shown in Figure 4 Schematic diagram with optimization, wherein single channel precision 12, prediction window are reduced to 1 LSB.The specific work process of the present embodiment As follows: prediction circuit judges whether it meets prediction standard by detecting the predicted detection signal in each channel, if met pre- Mark criterion provides prediction correct signal, notifies channel ADC to complete quantization, while providing the idle marker signal in the channel, The channel is placed in idle channel pond.In task schedule, according to the channel in idle channel pond, by randomizer with Machine selects a channel in idle channel pond as the sampling channel of sampling next time, and more by corresponding clock control signal control Phase clock generation circuit generates the sampling clock for the next sampling channel chosen.Since then, a task schedule process is completed.
It is the channel status in part idle channel pond in quantization process of interception as shown in Figure 5.The longitudinal axis is corresponding each in Fig. 5 The number in channel, each platform length of a curve represent the channel of the reference numeral time existing in idle channel pond, in figure The corresponding curve of lower cycle channel indicates the channel randomly selected in idle channel pond when sampling next time.Intuitively apparently, channel Job order be random.Because the Predicting Technique based on voltage window is related to input signal, idle channel is also believed with input Number relevant, for mismatch, this is inherently a kind of random, in addition the random selection in idle channel so that channel with Machine is stronger.
From task schedule principle it is found that time-interleaved SAR ADC channel number is more, the port number in idle channel pond is more Probability it is bigger.It is fewer when the period of quantization consumption meanwhile because frequency input signal and signal type will affect the quantization period When, the time in idle channel pond later is longer.Idle channel pond quantity is bigger, it is meant that there are more idle channels, so that The randomness in channel is bigger.
To sum up, prediction algorithm is based in the present embodiment to reduce single channel ADC quantization time, in conjunction with task scheduling algorithm benefit The randomization in channel is realized with reduced quantization time to realize the optimization of mismatch.The technology is not required to additional channel, only in list It after the completion of channel ADC quantization, places it in an idle channel pond, when next time quantifies, by task scheduling modules at random from pond In random selection one channel as sampling channel, the random of channel is realized with this and to the optimization of mismatch.
It is worth noting that may be used also in addition to the quantization time for reducing current quantisation period corresponding channel using prediction algorithm With by the time span for increasing the current quantisation period come so that corresponding channel fulfils quantization ahead of schedule within the current quantisation period, than The sample rate of time-interleaved ADC realizes the increase current quantisation period as described in passing through the single pass operating rate of holding and reduce Time span.As long as therefore each channel time-interleaved ADC is enabled to fulfil quantization ahead of schedule, i.e., have before quantization next time certain The mode of free time, for example, other covert lower quantization times or increase time monocycle so that a cycle have it is surplus The mode of remaining time, all within the scope of the present invention.
In conclusion the present invention propose it is a kind of by reduce current quantisation period corresponding channel quantization time or increase work as The time span in preceding quantization period makes it fulfil quantization ahead of schedule and enters idle state, then realizes channel using task scheduling algorithm It is randomized to optimize the technology of interchannel mismatch, in the case where not increasing channel, it can be achieved that the purpose of random channel.The present invention The cycling sequence in channel is changed to pseudorandom mode, so that influence of the mismatch to ADC is also randomized, mismatch is contributed miscellaneous Scattered energy, which is divided, is making an uproar on bottom, is conducive to improve SFDR.
Although a kind of task based access control scheduling of the invention realizes time-interleaved ADC mismatch optimisation technique with the shape of example Formula discloses as above, and however, it is not intended to limit the invention, if those skilled in the art, is done in the spirit for not departing from of the invention Unsubstantiality be altered or modified, all should belong to the claims in the present invention protection range.

Claims (5)

1. a kind of time-interleaved ADC mismatch optimization method of task based access control scheduling, the time-interleaved ADC includes M channel, M For positive integer, one and only one channel is sampled and is quantified within a quantization period of the time-interleaved ADC;
It is characterized in that, the time-interleaved ADC mismatch optimization method includes the following steps:
Step 1: within each quantization period of the time-interleaved ADC, by reducing current quantisation period corresponding channel Quantization time or the time span for increasing the current quantisation period, so that the corresponding channel amount of fulfiling ahead of schedule within the current quantisation period Change;
Step 2: all channels for completing quantization of label are idle channel;
Step 3: when time-interleaved ADC next quantization period carrys out interim, the random selection one from all idle channels Channel is sampled and is quantified, return step one.
2. the time-interleaved ADC mismatch optimization method of task based access control scheduling according to claim 1, which is characterized in that institute State the quantization time for reducing current quantisation period corresponding channel in step 1 method particularly includes: judge by prediction algorithm current Whether corresponding channel is predicted correctly, to predict the corresponding channel amount of fulfiling ahead of schedule in the Correct current quantisation period in the quantization period Change.
3. the time-interleaved ADC mismatch optimization method of task based access control scheduling according to claim 2, which is characterized in that institute State prediction algorithm method particularly includes: setting voltage window, when the input voltage of comparator in the time-interleaved ADC is less than electricity Indicate that prediction is correct when pressing window.
4. the time-interleaved ADC mismatch optimization method of task based access control scheduling according to claim 1, which is characterized in that institute State the time span for increasing the current quantisation period in step 1 method particularly includes: keep single pass operating rate and reduce institute State the sample rate of time-interleaved ADC.
5. the time-interleaved ADC mismatch optimization method of task based access control scheduling according to claim 1-4, feature It is, enters idle channel pond in the idle channel of each quantization period internal labeling, and come temporarily in next quantization period A channel is randomly choosed from the idle channel pond using randomizer to be sampled and quantified.
CN201910821338.6A 2019-09-02 2019-09-02 A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling Pending CN110518910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910821338.6A CN110518910A (en) 2019-09-02 2019-09-02 A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910821338.6A CN110518910A (en) 2019-09-02 2019-09-02 A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling

Publications (1)

Publication Number Publication Date
CN110518910A true CN110518910A (en) 2019-11-29

Family

ID=68630214

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910821338.6A Pending CN110518910A (en) 2019-09-02 2019-09-02 A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling

Country Status (1)

Country Link
CN (1) CN110518910A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111464184A (en) * 2020-04-22 2020-07-28 电子科技大学 Time-interleaved ADC based on compressed sensing

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1358352A (en) * 1999-06-23 2002-07-10 艾利森电话股份有限公司 Parallel analog-to-digital converter
CN102342027A (en) * 2009-03-03 2012-02-01 交互数字专利控股公司 Method for a radio frequency (RF) sampling apparatus with arrays of time interleaved samplers and scenario based dynamic resource allocation
CN102386918A (en) * 2010-08-27 2012-03-21 英特希尔美国公司 Calibration of impairments in a multichannel time-interleaved ADC
CN102420612A (en) * 2011-12-16 2012-04-18 电子科技大学 Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching
CN102668383A (en) * 2009-07-30 2012-09-12 电信教育集团(国家高等电信学校) Correction of analog defects in parallel analog-to-digital converters, in particular for multi-standard, software-defined radio, and/or cognitive radio use
CN102783031A (en) * 2010-03-26 2012-11-14 日本电气株式会社 Time-interleaved method A/D conversion device
CN105282655A (en) * 2014-06-26 2016-01-27 美国思睿逻辑有限公司 Reducing audio artifacts in a system for enhancing dynamic range of audio signal path
CN107819467A (en) * 2016-09-12 2018-03-20 美国亚德诺半导体公司 Time alternation type ADC with programmable phase
CN108141223A (en) * 2015-09-25 2018-06-08 高通股份有限公司 With time-interleaved(TI)Or two step successive approximation register(SAR)The delta-sigma adc of quantizer(ADC)
CN108736892A (en) * 2017-04-18 2018-11-02 美国亚德诺半导体公司 Random time intertexture digital analog converter
CN109756228A (en) * 2018-12-18 2019-05-14 深圳贝特莱电子科技股份有限公司 A kind of channel switching control method of multichannel SAR-ADC circuit

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1358352A (en) * 1999-06-23 2002-07-10 艾利森电话股份有限公司 Parallel analog-to-digital converter
CN102342027A (en) * 2009-03-03 2012-02-01 交互数字专利控股公司 Method for a radio frequency (RF) sampling apparatus with arrays of time interleaved samplers and scenario based dynamic resource allocation
CN102668383A (en) * 2009-07-30 2012-09-12 电信教育集团(国家高等电信学校) Correction of analog defects in parallel analog-to-digital converters, in particular for multi-standard, software-defined radio, and/or cognitive radio use
CN102783031A (en) * 2010-03-26 2012-11-14 日本电气株式会社 Time-interleaved method A/D conversion device
CN102386918A (en) * 2010-08-27 2012-03-21 英特希尔美国公司 Calibration of impairments in a multichannel time-interleaved ADC
CN102420612A (en) * 2011-12-16 2012-04-18 电子科技大学 Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching
CN105282655A (en) * 2014-06-26 2016-01-27 美国思睿逻辑有限公司 Reducing audio artifacts in a system for enhancing dynamic range of audio signal path
CN108141223A (en) * 2015-09-25 2018-06-08 高通股份有限公司 With time-interleaved(TI)Or two step successive approximation register(SAR)The delta-sigma adc of quantizer(ADC)
CN107819467A (en) * 2016-09-12 2018-03-20 美国亚德诺半导体公司 Time alternation type ADC with programmable phase
CN108736892A (en) * 2017-04-18 2018-11-02 美国亚德诺半导体公司 Random time intertexture digital analog converter
CN109756228A (en) * 2018-12-18 2019-05-14 深圳贝特莱电子科技股份有限公司 A kind of channel switching control method of multichannel SAR-ADC circuit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
HEINER LANGE 等: "ADC Topology Based on Compressed Sensing for Low Power Brain Monitoring", 《PROCEDIA ENGINEERING》 *
JING LI 等: "A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS》 *
徐双恒 等: "一种高精度∑-△A/D转换器的数字滤波器设计", 《微电子学与计算机》 *
王亚军 等: "TIADC通道误差自适应修正方法", 《西安电子科技大学学报》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111464184A (en) * 2020-04-22 2020-07-28 电子科技大学 Time-interleaved ADC based on compressed sensing
CN111464184B (en) * 2020-04-22 2022-03-15 电子科技大学 Time-interleaved ADC based on compressed sensing

Similar Documents

Publication Publication Date Title
Jiang et al. A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS
CN104917524B (en) Analog-digital converter
CN103905049B (en) A kind of high-speed flash adds alternately comparison expression gradually-appoximant analog-digital converter
CN103312327A (en) Time sequence correcting circuit and method for time-interleaved analog-digital converter
CN102045067A (en) Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC
CN104604139B (en) Method and apparatus for calibrating the stage in production line analog-digital converter
CN103560783A (en) Digital event generator, comparator, switched mode energy converter and method
CN104660261B (en) A kind of analog-digital commutator of adaptive quantizing
CN110518910A (en) A kind of time-interleaved ADC mismatch optimization method of task based access control scheduling
CN104485957A (en) Pipeline analog-to-digital converter
Hu et al. Closed‐loop charge recycling switching scheme for SAR ADC
Yazdani et al. Low‐power bottom‐plate sampling capacitor‐splitting DAC for SAR ADCs
CN101621294B (en) Control logical circuit and successive approximation analog-to-digital converter
CN106779147B (en) Power load prediction method based on self-adaptive hierarchical time sequence clustering
CN102013894B (en) Low-power pipeline analogue-digital converter (ADC)
CN107682014A (en) A kind of mixed type ADC system and its method for improving resolution ratio and speed
CN111756380A (en) Two-step successive approximation type analog-to-digital converter sharing bridge capacitor array
CN101350621A (en) A/D converter
CN104143983B (en) Continuous Approximation formula analog-digital converter and its method
CN106656190A (en) Continuous approximation type analog-to-digital conversion circuit and method therefor
McDanel et al. Saturation rram leveraging bit-level sparsity resulting from term quantization
CN102790618A (en) Successively-approximating analogue/digital converter with window predicting function and method
CN105071811A (en) Bit circulation method used for improving successive approximation analog to digital converter DNL/INL
CN108039890A (en) A kind of SAR ADC circuit and D conversion method
Saponara et al. Architectural exploration and design of time-interleaved SAR arrays for low-power and high speed A/D converters

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20191129

WD01 Invention patent application deemed withdrawn after publication