CN110517644B - Display device capable of suppressing electromagnetic interference and display driving circuit - Google Patents
Display device capable of suppressing electromagnetic interference and display driving circuit Download PDFInfo
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- CN110517644B CN110517644B CN201810496008.XA CN201810496008A CN110517644B CN 110517644 B CN110517644 B CN 110517644B CN 201810496008 A CN201810496008 A CN 201810496008A CN 110517644 B CN110517644 B CN 110517644B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
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Abstract
The present invention relates to a display device and a display driving circuit capable of suppressing electromagnetic interference. The display device includes a substrate, an active array, a display driver, and a Thin-Film Transistor (TFT) regulator circuit. The active array is arranged on the substrate and comprises a plurality of data lines, a plurality of gate lines and a plurality of pixels, wherein the data lines are criss-cross the gate lines, and the pixels are coupled at the crossing positions of the data lines and the gate lines. The display driver is disposed on the substrate and generates signals for driving the data lines and/or the gate lines in response to the adjusted sequential data clock signal. The thin film transistor regulating circuit is arranged on the substrate and coupled with the display driver. The thin film transistor regulating circuit includes one or more thin film transistors for attenuating the amplitude of a Serial Data Clock (SDCLK) signal in response to a predetermined gate bias voltage to provide a regulated Serial Data Clock signal to the display driver.
Description
Technical Field
The present invention relates to the field of display devices, and more particularly, to a display device and a display driving circuit capable of suppressing Electromagnetic Interference (EMI).
Background
Electromagnetic Interference (EMI) refers to the effect of Electromagnetic energy of an electronic signal on surrounding components, devices, equipment, and biological tissues. Severe electromagnetic interference can cause electronic device malfunction and even harm the user's physical health. At present, the electromagnetic interference phenomenon of electronic products is increasingly emphasized in the world, and the electronic products are required to meet a certain anti-electromagnetic interference standard before being on the market.
For example, a display device is sold only after passing the electromagnetic interference test. However, as the resolution of the display device is required to be higher, the transmission rate of the display driver for transmitting the data signal and the scan signal must be increased, and the electromagnetic interference phenomenon of the display device becomes more serious. Accordingly, there is a need for an improved display technology to reduce the electromagnetic interference of the display device.
Disclosure of Invention
In order to solve the above-mentioned problems, an object of the present invention is to provide a display device and a display driving circuit, which can effectively reduce the emi of the display device by properly attenuating Serial Data Clock (SDCLK) signals provided to a display driver, so that the display device can pass the emi test.
Specifically, the present invention discloses a display device, which includes:
a substrate;
the active array is arranged on the substrate and comprises a plurality of data lines, a plurality of gate lines and a plurality of pixels, the data lines are criss-cross the gate lines, and the pixels are coupled at the crossing positions of the data lines and the gate lines;
a display driver disposed on the substrate, the display driver being configured to generate signals for driving the data lines and/or the gate lines in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a serial data clock signal in response to a predetermined gate bias voltage to provide the adjusted serial data clock signal to the display driver.
The display device, wherein the thin film transistor adjusting circuit comprises a plurality of thin film transistors arranged in parallel, each thin film transistor is connected between the sequence data clock signal and the adjusted sequence data clock signal and is controlled by the preset gate bias voltage.
The display device, wherein the thin film transistor adjusting circuit comprises a plurality of thin film transistors arranged in series to form a thin film transistor string, the thin film transistors are connected in series between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
The display device, wherein the thin film transistor adjusting circuit is realized by a single thin film transistor, and the thin film transistor is connected between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
The display device further includes:
the printed circuit board is coupled with the thin film transistor regulating circuit and used for providing the sequence data clock signal for the thin film transistor regulating circuit.
The display device further includes:
an electronic ink layer is stacked on the active array.
The invention also discloses a display driving circuit for driving an active array of a display device, comprising:
a display driver disposed on the substrate, the display driver for generating a signal for driving the active array in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a serial data clock signal in response to a predetermined gate bias voltage to provide the adjusted serial data clock signal to the display driver.
The display driving circuit, wherein the thin film transistor adjusting circuit comprises a plurality of thin film transistors arranged in parallel, each thin film transistor is connected between the sequence data clock signal and the adjusted sequence data clock signal and is controlled by the preset gate bias voltage.
The display driving circuit, wherein the thin film transistor adjusting circuit comprises a plurality of thin film transistors arranged in series to form a thin film transistor string, and the thin film transistors are connected in series between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
The display driving circuit, wherein the thin film transistor adjusting circuit is implemented by a single thin film transistor, and the thin film transistor is connected between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
Drawings
FIG. 1 is a block diagram of a display device according to an embodiment of the invention;
FIG. 2 is a circuit diagram of a TFT regulator circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a TFT regulator circuit according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of a TFT regulator circuit according to yet another embodiment of the present invention;
fig. 5 is a cross-sectional view of a display device according to an embodiment of the invention.
Description of the symbols:
100. 500: a display device; 102: a substrate;
104: an active array; 106: a display driver;
108. 200, 300, 400: a thin film transistor regulating circuit; 110: a data line;
112: a gate line; 114: a pixel;
116: a printed circuit board; JS: a sequence data clock signal;
JS': adjusting the subsequent data clock signal; 202. 302, 402: a thin film transistor;
PVB: presetting a gate bias voltage; 502: an electronic ink layer;
506: an electronic ink unit.
Detailed Description
In order to make the aforementioned features and effects of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a block diagram of a display device 100 according to an embodiment of the invention. The display device 100 may be any type of display device that generally includes a substrate 102, an active array 104, a display driver 106, and a Thin-Film Transistor (TFT) regulator circuit 108. the display device 100 may also include a printed circuit board 116.
The active array 104 is disposed on the substrate 102 and includes a plurality of data lines 110, a plurality of gate lines 112, and a plurality of pixels 114. The data lines 110 are criss-cross the gate lines 112, wherein the pixels 114 are coupled to the intersections of the data lines 110 and the gate lines 112 to form a pixel array disposed in the display area of the substrate 102.
The display driver 106 is disposed on the substrate 102 and generates a signal for driving the data line 110 and/or the gate line 112 in response to the adjusted sequential data clock signal JS'. The display driver 106 may be a data driver (data driver), a gate driver (gate driver), or a combination thereof. Although fig. 1 shows the display driver 106 coupled to the data line 110 as a data driver, it should be noted that the display driver 106 may also be coupled to the gate line 112 as a gate driver, or coupled to both the data line 110 and the gate line 112 as a common driver. The display driver 106 is disposed in the non-display area of the substrate 102 that is shielded compared to the active array 104.
The adjusted Serial Data Clock signal JS' is a result of attenuation of the Serial Data Clock Signal (SDCLK). The adjusted sequential data clock signal JS' can be generated by the tft adjusting circuit 108. As shown in fig. 1, the tft adjusting circuit 108 is disposed on the substrate 102 and coupled to the display driver 106, such as a non-display region disposed on the substrate 102. The thin film transistor conditioning circuit 108 may include one or more thin film transistors controlled by a predetermined gate bias voltage. The thin film transistor trimming circuit 108 attenuates the amplitude of the sequence data clock signal JS in response to a predetermined gate bias voltage to provide a trimmed sequence data clock signal JS' to the display driver 106. The tfts in the tft conditioning circuit 108 may be fabricated, for example, in the same process as the active array 104. Details of the circuit of the tft conditioning circuit 108 will be described with reference to fig. 2, 3, and 4.
The adjusted serial data clock signal JS'/serial data clock signal JS determines the operation clock of the display driver 106. The display driver 106 generates a data signal for driving the data line 110 and/or a gate signal for driving the gate line 112 according to the adjusted sequential data clock signal JS'.
With the above configuration, the electromagnetic interference effect in the display device 100 can be effectively suppressed. Further, it is found that the sequence data clock signal JS from the display signal source (not shown) is often a high frequency signal (e.g., about 50MHz), and if it is directly provided to the display driver 106 as the working clock, the sequence data clock signal JS becomes one of the main sources of electromagnetic interference. Since the electromagnetic interference has a high positive correlation with the amplitude and frequency of the electronic signal, the amplitude of the sequence data clock signal JS is properly attenuated, and the attenuated result (i.e., the adjusted sequence data clock signal JS') is provided to the display driver 106 for use, so that the electromagnetic interference of the display device 100 can be effectively reduced.
According to an aspect of the invention, the display driver 106 and the TFT adjusting circuit 108 can be considered as a display driving circuit disposed on the substrate 102 of the display device 100. In one embodiment, the display driver 106 may be a chip, and the tft adjusting circuit 108 may be coupled to the chip pin of the display driver 106 for receiving the sequence data clock signal JS.
The printed circuit board 116 is coupled to the tft conditioning circuit 108. The printed circuit board 116 may provide a sequence data clock signal JS to the tft conditioning circuit 108. The printed circuit board may be a Flexible Printed Circuit (FPC) board, which serves as a signal transmission interface between the electronic components on the substrate 102 and external display signal sources.
According to an embodiment of the present invention, the thin film transistor regulating circuit 108 may be implemented by one or more thin film transistors. The gate of the one or more TFTs may exhibit an on-Resistance (RON) in response to a predetermined gate bias voltage, thereby properly attenuating the received sequence data clock signal JS to the conditioned sequence data clock signal JS'.
Different embodiments of the thin film transistor regulating circuit will be described below in conjunction with figures 2, 3 and 4. It is noted that the embodiments are not intended to be exhaustive or limiting, and that in some applications, the embodiments may be suitably modified and/or combined.
Fig. 2 is a circuit diagram of a tft conditioning circuit 200 according to an embodiment of the invention. In this embodiment, the thin film transistor regulator circuit 200 includes a single thin film transistor 202. The thin film transistor 202 is connected between the sequence data clock signal JS and the adjusted sequence data clock signal JS', and is controlled by a predetermined gate bias voltage PVB. For example, one terminal (e.g., drain/source) of the thin film transistor 202 can be coupled to the printed circuit board 116 to receive the sequence data clock signal JS, and the other terminal (e.g., source/drain) can be coupled to the display driver 106 to provide the adjusted sequence data clock signal JS' thereto.
The predetermined gate bias PVB can be sized to cause the TFT 202 to exhibit an on-resistance. Therefore, the amplitude of the adjusted sequential data clock signal JS' is attenuated compared to the sequential data clock signal JS. The degree of amplitude attenuation of the adjusted sequential data clock signal JS' may depend on the chip determination voltage of the display driver 106. For example, the amplitude attenuation of the post-conditioned serial data clock signal JS 'may be required to be such that the attenuated level of the post-conditioned serial data clock signal JS' is still recognizable by the display driver 106 and the level shift characteristic is still consistent with the pre-conditioned serial data clock signal JS. In other words, the tft adjusting circuit 200 does not change the display operation characteristics of the display driver 106.
FIG. 3 is a circuit diagram of a TFT regulator circuit 300 according to another embodiment of the invention. In this embodiment, the tft adjusting circuit 300 includes a plurality of tfts 302 connected in parallel, and each of the tfts 302 is connected between the sequence data clock signal JS and the adjusted sequence data clock signal JS' and controlled by a predetermined gate bias voltage PVB.
For example, one end (e.g., drain/source) of each tft 302 can be coupled to the pcb 116 to receive the sequence data clock signal JS, and the other end (e.g., source/drain) can be coupled to the display driver 106 to provide the adjusted sequence data clock signal JS' to the display driver 106. A predetermined gate bias PVB is applied to the control terminals (e.g., gates) of the tfts 302 to control the equivalent on-resistance of the tft conditioning circuit 300.
Fig. 4 is a circuit diagram of a tft conditioning circuit 400 according to another embodiment of the invention. In this embodiment, the TFT regulator circuit 400 includes a plurality of TFTs 402, the TFTs 402 being arranged in series to form a TFT string 404. The thin film transistor string 404 is connected between the sequence data clock signal JS and the adjusted sequence data clock signal JS', and is controlled by the predetermined gate bias voltage PVB.
For example, the first and last tfts 402 of the tft string 404 can be coupled to the pcb 116 and the display driver 106 respectively to receive the sequence data clock signal JS from the pcb 116 and output the adjusted sequence data clock signal JS' to the display driver 106. A predetermined gate bias PVB can be applied to the control terminals (e.g., gates) of the tfts 402 to control the equivalent on-resistance of the tft string 404.
FIG. 5 is a cross-sectional view of a display device 500 according to an embodiment of the invention. The display device 500 is configured as the display device 100 of FIG. 1, but further includes an electronic ink layer 502 as an electronic paper display. An electronic ink layer 502 may be stacked on the active array 104. The electronic ink layer 502 includes a plurality of electronic ink units 506. Each e-ink unit 506 may have bi-stable/multi-stable characteristics such that the image is preserved after writing. For example, the electronic ink unit 506 may be implemented by a liquid with charged particles. By applying an electric field to the electronic ink unit 506, the charged particles can be moved in the liquid. The charged particles may have different colors, such as black and white. Therefore, by driving the electrodes in the active array 104 to control the floating of the charged particles with the desired color, the electronic ink layer 502 can display the desired image.
According to the embodiments of the present invention, a display device and a display driving circuit capable of suppressing electromagnetic interference can be provided. It has been found that the serial data clock signal conventionally used in display devices is one of the major sources of emi. Therefore, by properly attenuating the serial data clock signal provided to the display driver, the electromagnetic interference can be effectively reduced, and the display device can pass the electromagnetic interference test. In addition, in the embodiment of the invention, the attenuation of the serial data clock signal is realized through a thin film transistor element. The thin film transistor can be disposed on a substrate of the display device and used as a variable resistor to weaken the strength of the serial data clock signal. By this way, when the display device fails the emi test, the developer can improve the emi problem by adjusting the preset gate bias voltage provided to the tft without redesigning the circuit board. And since the signal intensity of the serial data clock signal is properly attenuated, the power consumption of the display device during operation can be reduced.
Claims (8)
1. A display device, comprising:
a substrate;
the active array is arranged on the substrate and comprises a plurality of data lines, a plurality of gate lines and a plurality of pixels, the data lines are criss-cross the gate lines, and the pixels are coupled at the crossing positions of the data lines and the gate lines;
a display driver disposed on the substrate, the display driver being configured to generate signals for driving the data lines and/or the gate lines in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a serial data clock signal in response to a preset gate bias voltage to provide the adjusted serial data clock signal to the display driver;
the thin film transistor regulating circuit comprises a plurality of thin film transistors which are arranged in parallel, wherein each thin film transistor is connected between the sequence data clock signal and the regulated sequence data clock signal and is controlled by the preset gate bias voltage.
2. A display device, comprising:
a substrate;
the active array is arranged on the substrate and comprises a plurality of data lines, a plurality of gate lines and a plurality of pixels, the data lines are criss-cross the gate lines, and the pixels are coupled at the crossing positions of the data lines and the gate lines;
a display driver disposed on the substrate, the display driver being configured to generate signals for driving the data lines and/or the gate lines in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a serial data clock signal in response to a preset gate bias voltage to provide the adjusted serial data clock signal to the display driver;
the thin film transistor regulating circuit comprises a plurality of thin film transistors which are arranged in series to form a thin film transistor string, wherein the thin film transistors are connected in series between the sequence data clock signal and the regulated sequence data clock signal and controlled by the preset gate bias voltage.
3. A display device, comprising:
a substrate;
the active array is arranged on the substrate and comprises a plurality of data lines, a plurality of gate lines and a plurality of pixels, the data lines are criss-cross the gate lines, and the pixels are coupled at the crossing positions of the data lines and the gate lines;
a display driver disposed on the substrate, the display driver being configured to generate signals for driving the data lines and/or the gate lines in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a serial data clock signal in response to a preset gate bias voltage to provide the adjusted serial data clock signal to the display driver;
the thin film transistor adjusting circuit is realized by a single thin film transistor, and the thin film transistor is connected between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
4. A display device as claimed in claim 1, 2 or 3, further comprising:
the printed circuit board is coupled with the thin film transistor regulating circuit and used for providing the sequence data clock signal for the thin film transistor regulating circuit.
5. A display device as claimed in claim 1, 2 or 3, further comprising:
an electronic ink layer is stacked on the active array.
6. A display driver circuit for driving an active array of a display device, comprising:
a display driver disposed on the substrate, the display driver for generating a signal for driving the active array in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a sequence data clock signal in response to a preset gate bias voltage, wherein a drain or a source of one end of the thin film transistor receives the sequence data clock signal, and a drain or a source of the other end of the thin film transistor is coupled to the display driver to provide the adjusted sequence data clock signal to the display driver, the thin film transistor adjusting circuit including a plurality of thin film transistors disposed in parallel, each thin film transistor being connected between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
7. A display driver circuit for driving an active array of a display device, comprising:
a display driver disposed on the substrate, the display driver for generating a signal for driving the active array in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a sequence data clock signal in response to a preset gate bias voltage, wherein a drain or a source of one end of the thin film transistor receives the sequence data clock signal, and a drain or a source of the other end of the thin film transistor is coupled to the display driver to provide the adjusted sequence data clock signal to the display driver, the thin film transistor adjusting circuit including a plurality of thin film transistors disposed in series to form a thin film transistor string, the thin film transistors being connected in series between the sequence data clock signal and the adjusted sequence data clock signal and being controlled by the preset gate bias voltage.
8. A display driver circuit for driving an active array of a display device, comprising:
a display driver disposed on the substrate, the display driver for generating a signal for driving the active array in response to the adjusted sequential data clock signal; and
a thin film transistor adjusting circuit disposed on the substrate and coupled to the display driver, the thin film transistor adjusting circuit including at least one thin film transistor and being configured to attenuate an amplitude of a sequence data clock signal in response to a preset gate bias voltage, wherein a drain or a source of one end of the thin film transistor receives the sequence data clock signal, and a drain or a source of the other end of the thin film transistor is coupled to the display driver to provide the adjusted sequence data clock signal to the display driver, the thin film transistor adjusting circuit is implemented by a single thin film transistor, and the thin film transistor is connected between the sequence data clock signal and the adjusted sequence data clock signal and controlled by the preset gate bias voltage.
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| CN114420064A (en) * | 2022-02-17 | 2022-04-29 | 北京京东方光电科技有限公司 | Electronic paper driving circuit, method, electronic paper display panel and electronic paper display |
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