CN110515869A - More Host CPU level linked methods and system - Google Patents
More Host CPU level linked methods and system Download PDFInfo
- Publication number
- CN110515869A CN110515869A CN201810497465.0A CN201810497465A CN110515869A CN 110515869 A CN110515869 A CN 110515869A CN 201810497465 A CN201810497465 A CN 201810497465A CN 110515869 A CN110515869 A CN 110515869A
- Authority
- CN
- China
- Prior art keywords
- network interface
- interface card
- pcie
- cpu
- host
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
Abstract
The application provides a kind of more Host CPU level linked methods and system, which includes: control chip, CPU, PCIE exchange chip and PCIE network interface card；Wherein: the control chip, for issuing the first configuration-direct to the PCIE network interface card；The PCIE network interface card, for physical port virtually to be turned to multiple VF network interface cards according to first configuration-direct；The control chip is also used to issue the second configuration-direct to the PCIE exchange chip；The PCIE exchange chip, for being that each Host Port distributes VF network interface card according to second configuration-direct；The control chip is also used to control the CPU electrifying startup；The CPU, for carrying out PCI scanning, establishing the virtual PCI bus domain of itself after electrifying startup；The CPU, is also used to identify the VF network interface card in the virtual PCI bus domain for being subordinated to itself, and loads VF trawl performance, realizes internal/external communication by the VF network interface card.This method can satisfy demand of multiple CPU as Host CPU.
Description
Technical field
This application involves the communication technology more particularly to a kind of more Host CPU level linked methods and systems.
Background technique
In traditional PCIE, (Peripheral Component Interconnect Express, peripheral component high speed are mutual
Connection) in transparent bridge (transparent bridging) concatenated schemes, principal and subordinate is strictly distinguished, the CPU (Center of main status is served as
Process Unit, central processing unit) it is referred to as HOST (master) CPU, it serves as and is referred to as from the CPU or PCIE device of status
EP (Endpoint, endpoint), and under this kind of mode, only support 1 CPU as HOST CPU, other CPU or PCIE device are only
It can serve as from equipment.
However, the intelligence of band GPU (Graphics Processing Unit, graphics processing unit) of current some mainstreams
Limitation that chip is designed due to chip or some CPU, i.e., can only conducts since holotype is only supported in the limitation of application scenarios
Host CPU, so that not being available traditional PCIE transparent bridge concatenated schemes carries out multi -CPU/GPU cluster formula design.
Summary of the invention
In view of this, the application provides a kind of more Host CPU level linked methods and system.
Specifically, the application is achieved by the following technical solution:
According to the embodiment of the present application in a first aspect, provide a kind of more Host CPU levels connection system, including control chip,
CPU, PCIE exchange chip and PCIE network interface card, the PCIE exchange chip support MR-IOV function, and the PCIE network interface card is supported
SR-IOV function, the multiple port Host Port are provided on the exchange chip, and the CPU passes through the Host Port and institute
State exchange chip connection, in which:
The control chip, for issuing the first configuration-direct to the PCIE network interface card；
The PCIE network interface card, for physical port virtually to be turned to multiple VF network interface cards according to first configuration-direct；
The control chip is also used to issue the second configuration-direct to the PCIE exchange chip；
The PCIE exchange chip, for being that each Host Port distributes VF network interface card according to second configuration-direct；
The control chip is also used to control the CPU electrifying startup；
The CPU, for carrying out PCI scanning, establishing the virtual PCI bus domain of itself after electrifying startup；
The CPU, is also used to identify the VF network interface card in the virtual PCI bus domain for being subordinated to itself, and loads VF trawl performance,
Internal/external communication is realized by the VF network interface card.
Optionally, the control chip, specifically for identifying that the physical function PF of the PCIE network interface card, load PF drive,
And the first configuration-direct is issued to the PCIE network interface card.
Optionally, the PCIE network interface card includes the first physical port and the second physical port；
The PCIE network interface card, specifically for first physical port is virtually turned to multiple first kind VF network interface cards, and
Second physical port is virtually turned into multiple Second Type VF network interface cards；
The PCIE exchange chip is specifically used for respectively each Host Port distribution first kind VF network interface card and the second class
Type VF network interface card；
The CPU is realized internal specifically for the first kind VF network interface card by being subordinated to the virtual PCI bus domain of itself
Communication, and the Second Type VF network interface card by being subordinated to the virtual PCI bus domain of itself realizes external communication.
Optionally, the PCIE exchange chip is additionally provided with NTB module or/and dma module；
The CPU is also used to realize internal communication by NTB mode or/and dma mode.
Optionally, the CPU is integrated with GPU.
According to the second aspect of the embodiment of the present application, a kind of more Host CPU level linked methods are provided, are applied to include control
More Host CPU levels of chip, CPU, PCIE exchange chip and PCIE network interface card contact system, and the PCIE exchange chip supports MR-
IOV function, the PCIE network interface card supports SR-IOV function, is provided with the multiple port Host Port on the exchange chip, described
CPU is connect by the Host Port with the exchange chip, the method also includes:
The control chip issues the first configuration-direct to the PCIE network interface card；
Physical port is virtually turned to multiple virtual functions VF network interface cards according to first configuration-direct by the PCIE network interface card；
The control chip issues the second configuration-direct to the PCIE exchange chip；
The PCIE exchange chip is that each Host Port distributes VF network interface card according to second configuration-direct；
CPU electrifying startup described in the control chip controls；
After the CPU electrifying startup, peripheral component interconnection PCI scanning is carried out, the virtual PCI bus domain of itself is established；
The CPU identification is subordinated to the VF network interface card in the virtual PCI bus domain of itself, loads VF trawl performance, passes through the VF
Network interface card realizes internal/external communication.
Optionally, the control chip issues the first configuration-direct to the PCIE network interface card, comprising:
The control chip identifies the physical function PF of the PCIE network interface card, load PF driving, and to the PCIE network interface card
Issue the first configuration-direct.
Optionally, the PCIE network interface card includes the first physical port and the second physical port；
Physical port is virtually turned to multiple VF network interface cards according to first configuration-direct by the PCIE network interface card, comprising:
First physical port is virtually turned to multiple first kind VF network interface cards by the PCIE network interface card, and by the second physics
Port virtual turns to multiple Second Type VF network interface cards；
The PCIE exchange chip is that each Host Port distributes VF network interface card according to second configuration-direct, comprising:
The PCIE exchange chip is respectively each Host Port distribution first kind VF network interface card and Second Type VF network interface card；
The CPU realizes internal/external communication by the VF network interface card, comprising:
The CPU realizes internal communication by being subordinated to the first kind VF network interface card in the virtual PCI bus domain of itself, and
Second Type VF network interface card by being subordinated to the virtual PCI bus domain of itself realizes external communication.
Optionally, the PCIE exchange chip is additionally provided with NTB module or/and dma module；
The method also includes:
The CPU realizes internal communication by NTB mode or/and dma mode.
Optionally, the CPU is integrated with GPU.
More Host CPU levels of the embodiment of the present application contact system, by utilizing the PCIE exchange chip for supporting MR-IOV function
A set of more HOST CPU levels connection system based on PCIE is constructed with the PCIE network interface card of support SR-IOV function, controls chip controls
PCIE network interface card virtually turns to multiple VF network interface cards, and gives each Host Port respectively by PCIE exchange chip, so as to be exchanged by PCIE
The CPU for the Host Port access being arranged on chip can establish the virtual PCI bus domain of itself, and utilize distributed VF net
Card realizes internal/external communication, has not only met demand of multiple CPU as Host CPU, but also be well positioned to meet multiple
Host CPU shares the demand that a physical network card realizes internal/external data communication, and directly the network of standard is supported to connect
Mouthful, upper layer code for code compatibility is strong, and extension is convenient.
Detailed description of the invention
Fig. 1 is a kind of configuration diagram of more Host CPU level connection systems shown in one exemplary embodiment of the application；
Fig. 2 is a kind of flow diagram of more Host CPU level linked methods shown in one exemplary embodiment of the application；
Fig. 3 is the configuration diagram that one exemplary embodiment of the application shows a kind of concrete application scene.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended
The example of the consistent device and method of some aspects be described in detail in claims, the application.
It is only to be not intended to be limiting the application merely for for the purpose of describing particular embodiments in term used in this application.
It is also intended in the application and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.
In order to make those skilled in the art more fully understand technical solution provided by the embodiments of the present application, and keep the application real
The above objects, features, and advantages for applying example can be more obvious and easy to understand, with reference to the accompanying drawing to technical side in the embodiment of the present application
Case is described in further detail.
Referring to Figure 1, it is a kind of configuration diagram of more Host CPU level connection systems provided by the embodiments of the present application, such as schemes
Shown in 1, which may include control chip 110, CPU120, PCIE exchange chip 130 and PCIE
Network interface card 140, the CPU120 exchange core with PCIE by the Host Port (port) being arranged on the PCIE exchange chip 130
Piece 130 connects.Wherein:
The control chip 110, for issuing the first configuration-direct to the PCIE network interface card 140；
The PCIE network interface card 140, for physical port virtually to be turned to multiple VF according to first configuration-direct
(Virutal Function, virtual functions) network interface card；
The control chip 110 is also used to issue the second configuration-direct to the PCIE exchange chip 130；
The PCIE exchange chip 130, for being that each Host Port distributes VF network interface card according to second configuration-direct；
The control chip 110, is also used to control the CPU120 electrifying startup；
The CPU120, for after electrifying startup, carrying out peripheral component interconnection PCI scanning, the Virtual PC I for establishing itself is total
Line domain；
The CPU120 is also used to identify that the VF network interface card in the virtual PCI bus domain for being subordinated to itself, load VF network interface card drive
It is dynamic, internal/external communication is realized by the VF network interface card.
It should be noted that in the embodiment of the present application, if non-specified otherwise, mentioned CPU refers both to hand over by PCIE
The CPU of the Host Port access of chip is changed, i.e. Host CPU, the embodiment of the present application is subsequent no longer to be repeated.
In the embodiment of the present application, in order to realize that more Host CPU level connection, PCIE exchange chip 130 need support MR-IOV
(Multi-Root I/O (Input/Output, input/output) Virtualization, more input/output virtualizations) function
Can, so that PCIE exchange chip can virtually turn to multiple pci bus domains with a pci bus domain；PCIE network interface card 140 needs support
SR-IOV (Single-Root I/O Virtualization, single input/output virtualization) function, so that PCIE network interface card can
A PF network interface card is virtually turned to multiple VF network interface cards.
Multiple Host Port can be set on PCIE exchange chip 130, it is thus possible to there are multiple CPU120 by being somebody's turn to do
Multiple Host Port and PCIE exchange chip 130, wherein multiple to be connect by Host Port with PCIE exchange chip 130
CPU120 be used as Host CPU, realize more Host CPU levels connection.
In the embodiment of the present application, control chip 110 can issue configuration-direct (referred to herein as the to PCIE network interface card 140
One configuration-direct), to indicate that PCIE network interface card 140 carries out VF network interface card virtualization operations.
For example, control chip 110 can identify the PF (Physical Function, physical function) of PCIE network interface card 140,
PF driving is loaded, and issues the first configuration-direct to PCIE network interface card 140.
When PCIE network interface card 140 receives the first configuration-direct that control chip 110 is sent, PCIE network interface card 140 can be to enable
SR-IOV function, and physical port is virtually turned to multiple VF network interface cards.
Wherein, the quantity that physical port is virtually turned to VF network interface card by PCIE network interface card 140 can be by control chip 110 by the
One configuration-direct is indicated or is pre-configured in PCIE network interface card 140.
In the embodiment of the present application, after PCIE network interface card 140 completes VF network interface card virtualization operations, control chip 110 can be to
PCIE exchange chip 130 issues configuration-direct (referred to herein as the second configuration-direct), to indicate that PCIE exchange chip 130 is each
Host Port distributes VF network interface card.
When PCIE exchange chip 130 receives the second configuration-direct that control chip 110 is sent, PCIE exchange chip 130
It can be respectively each Host Port distribution VF network interface card.
For example, PCIE exchange chip 130 can be respectively that each Host Port distributes a VF network interface card；Alternatively, PCIE is exchanged
Chip 130 can be respectively some or all of in multiple Host Port Host Port distribute multiple VF network interface cards.
In the embodiment of the present application, after PCIE exchange chip 130 completes the distribution of VF network interface card, control chip 110 be can control
The CPU120 electrifying startup of PCIE exchange chip is accessed by Host Port.
After CPU120 electrifying startup, PCI scanning can be carried out, establishes the virtual PCI bus domain of itself, in turn, CPU120
It can identify and be subordinated to the VF network interface card in the virtual PCI bus domain of itself (PCIE exchange chip 130 distributes to what CPU120 was connected
The VF network interface card of Host Port), and VF trawl performance is loaded, it is realized by being subordinated to the VF network interface card in virtual PCI bus domain of itself
Communication internally (i.e. between Host CPU and Host CPU)/externally (i.e. between Host CPU and outer net).
It should be noted that in the embodiment of the present application, CPU120 establishes the virtual PCI bus domain of itself, and identifies
It is subordinated to the VF network interface card in the virtual PCI bus domain of itself, is loaded with after VF trawl performance, is realized pair by the VF network interface card
Before interior/external communication, it is also necessary to carry out IP address configuration to VF network interface card, specific implementation does not repeat them here herein.
As it can be seen that in the embodiment of the present application, by utilizing the PCIE exchange chip and support SR- for supporting MR-IOV function
The PCIE network interface card of IOV function constructs a set of more HOST CPU levels connection system based on PCIE, has both met multiple CPU conducts
The demand of Host CPU, and be well positioned to meet the shared physical network card of multiple Host CPU and realize internal/external data
The demand of communication, and directly support the network interface of standard, upper layer code for code compatibility is strong, and extension is convenient.
Further, the application in one embodiment, the PCIE network interface card 140 may include the first physical port
With the second physical port；
Correspondingly, the PCIE network interface card 140 can be specifically used for the first physical port virtually turning to multiple first kind
VF network interface card, and the second physical port is virtually turned into multiple Second Type VF network interface cards；
The PCIE exchange chip 130, can be specifically used for be respectively each Host Port distribution first kind VF network interface card and
Second Type VF network interface card；
The CPU120 can be specifically used for the first kind VF network interface card by being subordinated to the virtual PCI bus domain of itself
Realize internal communication, and the Second Type VF network interface card by being subordinated to the virtual PCI bus domain of itself realizes external communication.
In this embodiment, in order to improve the controllability and treatment effeciency of data communication, when there are multiple for PCIE network interface card 140
It, can be by part of physical port (referred to herein as the first physical port) for the number between Host CPU when physical port
According to communication, part physical port (referred to herein as the second physical port) is for the data communication between Host CPU and outer net.
It correspondingly, in this embodiment, can when control chip 110 carries out the virtualization configuration of VF network interface card to PCIE network interface card 140
The VF network interface card (referred to herein as first for being used for internal communication is virtually turned to indicate PCIE network interface card 140 for the first physical port
Type VF network interface card), and the second physical port is virtually turned to VF network interface card (the referred to herein as Second Type for being used for external communication
VF network interface card).
Similarly, when control chip 110 carries out VF network interface card assignment configuration to PCIE exchange chip 130, it can indicate that PCIE is handed over
Changing chip 130 is respectively each Host Port distribution first kind VF network interface card and Second Type VF network interface card.
For example, PCIE exchange chip 130 can be respectively that each Host Port distributes a first kind VF network interface card and one
Second Type VF network interface card, alternatively, PCIE exchange chip 130 can be respectively that each Host Port distributes multiple first kind VF nets
Card and multiple Second Type VF network interface cards.
Wherein, PCIE exchange chip 130 is the quantity and the second class of the first kind VF network interface card of same Host Port distribution
The quantity of type VF network interface card may be the same or different；PCIE exchange chip 130 is the first kind of different Host Port distribution
The quantity of type VF network interface card and the quantity of Second Type VF network interface card may be the same or different.
In this embodiment, CPU120 carries out PCI scanning in the manner described above, establishes the virtual PCI bus domain of itself, knows
It is not subordinated to the VF network interface card in the virtual PCI bus domain of itself, and after loading VF trawl performance, it can be by being subordinated to itself
The first kind VF network interface card in virtual PCI bus domain realizes internal communication, and the virtual PCI bus domain by being subordinated to itself
Second Type VF network interface card realizes external communication.
Further, the application in one embodiment, be also provided with NTB in PCIE exchange chip 130
(Non-transparent bridging, non-transparent bridge) module or/and DMA (Direct Memory Access, direct memory
Access) module；
Correspondingly, the CPU120 can be also used for realizing internal communication by NTB mode or/and dma mode.
In this embodiment, when having NTB module or/and dma module in PCIE exchange chip 130, CPU120 is in addition to can
Realized except internally communication in the manner described above, internal communication can also be realized by NTB mode or/and dma mode.
Wherein, it is existing to realize that the specific implementation of internal communication may refer to by NTB mode or/and dma mode by CPU120
There is associated description in the related technology, this will not be repeated here for the embodiment of the present application.
Further, the application in one embodiment, above-mentioned CPU can integrate GPU.
In this embodiment, for being integrated with the CPU of GPU, more Host GPU cascades can also be realized through the above way,
It implements the associated description that may refer in above method embodiment, and details are not described herein for the embodiment of the present application.
Fig. 2 is referred to, is a kind of flow diagram of more Host CPU level linked methods provided by the embodiments of the present application,
In, which can be applied to include control chip, CPU, PCIE exchange chip and PCIE network interface card
More Host CPU level connection systems, for example, more Host CPU level linked methods can be applied to more Host CPU level connection shown in FIG. 1
System, as shown in Fig. 2, more Host CPU level linked methods may comprise steps of:
Step S200, control chip issues the first configuration-direct to PCIE network interface card.
In the embodiment of the present application, control chip can issue the first configuration-direct to PCIE network interface card, to indicate PCIE network interface card
140 carry out VF network interface card virtualization operations.
For example, control chip 110 can identify the PF of PCIE network interface card, load PF driving, and first is issued to PCIE network interface card
Configuration-direct.
Step S210, physical port is virtually turned to multiple VF network interface cards according to the first configuration-direct by PCIE network interface card.
It, can be to enable SR- when PCIE network interface card receives the first configuration-direct that control chip is sent in the embodiment of the present application
IOV function, and physical port is virtually turned to multiple VF network interface cards.
Wherein, the quantity that physical port is virtually turned to VF network interface card by PCIE network interface card can pass through the first configuration by control chip
Instruction instruction is pre-configured in PCIE network interface card 140.
Step S220, control chip issues the second configuration-direct to PCIE exchange chip.
It, can be under PCIE exchange chip after PCIE network interface card completes VF network interface card virtualization operations in the embodiment of the present application
The second configuration-direct is sent out, to indicate that PCIE exchange chip is that each Host Port distributes VF network interface card.
Step S230, PCIE exchange chip is that each Host Port distributes VF network interface card according to the second configuration-direct.
In the embodiment of the present application, when PCIE exchange chip receives the second configuration-direct that control chip is sent, PCIE is handed over
Changing chip can be respectively each Host Port distribution VF network interface card.
For example, PCIE exchange chip can be respectively that each Host Port distributes a VF network interface card；Alternatively, PCIE exchanges core
Piece can be respectively some or all of in multiple Host Port Host Port distribute multiple VF network interface cards.
Step S240, chip controls CPU electrifying startup is controlled.
Step S250, after CPU electrifying startup, PCI scanning is carried out, the virtual PCI bus domain of itself is established.
Step S260, CPU identification is subordinated to the VF network interface card in the virtual PCI bus domain of itself, loads VF trawl performance, passes through
The VF network interface card realizes internal/external communication.
In the embodiment of the present application, after PCIE exchange chip completes the distribution of VF network interface card, it can control and connect by Host Port
Enter the CPU electrifying startup of PCIE exchange chip.
After CPU electrifying startup, PCI scanning can be carried out, establishes the virtual PCI bus domain of itself, in turn, CPU can know
It is not subordinated to the VF network interface card in the virtual PCI bus domain of itself, and loads VF trawl performance, is realized by the VF network interface card internal/right
Outer communication.
The application in one embodiment, above-mentioned PCIE network interface card may include the first physical port and the second physics end
Mouthful；
Correspondingly, physical port is virtually turned to multiple VF network interface cards according to the first configuration-direct by above-mentioned PCIE network interface card, can be with
Include:
First physical port is virtually turned to multiple first kind VF network interface cards by PCIE network interface card, and the second physical port is virtual
Turn to multiple Second Type VF network interface cards；
PCIE exchange chip is that each Host Port distributes VF network interface card according to the second configuration-direct, may include:
PCIE exchange chip is respectively each Host Port distribution first kind VF network interface card and Second Type VF network interface card；
Above-mentioned CPU realizes internal/external communication by the VF network interface card, may include:
CPU realizes internal communication by being subordinated to the first kind VF network interface card in the virtual PCI bus domain of itself, and passes through
The Second Type VF network interface card for being subordinated to the virtual PCI bus domain of itself realizes external communication.
In this embodiment, in order to improve the controllability and treatment effeciency of data communication, when there are multiple for PCIE network interface card 140
When physical port, the data communication that the first physical port can be used between Host CPU, the second physical port is used for Host
Data communication between CPU and outer net.
Correspondingly, when control chip carries out the virtualization configuration of VF network interface card to PCIE network interface card, PCIE network interface card can be indicated the
One physical port virtually turns to the first kind VF network interface card for internal communication, and the second physical port is virtually turned to and is used for
The Second Type VF network interface card of external communication.
Similarly, when control chip carries out VF network interface card assignment configuration to PCIE exchange chip, PCIE exchange chip can be indicated
Respectively each Host Port distribution first kind VF network interface card and Second Type VF network interface card.
In this embodiment, CPU can be realized by being subordinated to the first kind VF network interface card in the virtual PCI bus domain of itself
Internal communication, and the Second Type VF network interface card by being subordinated to the virtual PCI bus domain of itself realizes external communication.
The application in one embodiment, NTB module or/and DMA mould are also provided in PCIE exchange chip
Block；
Correspondingly, CPU can also realize internal communication by NTB mode or/and dma mode.
The application in one embodiment, above-mentioned CPU can integrate GPU.
In this embodiment, for being integrated with the CPU of GPU, more Host GPU cascades can also be realized through the above way,
It implements the associated description that may refer in above method embodiment, and details are not described herein for the embodiment of the present application.
It should be noted that in the embodiment of the present application, contacting each Host in system when needing to extend more Host CPU levels
When CPU is to interior/external communication bandwidth, the PCIE network interface card of new support SR-IOV function can be accessed in systems again, and pressed
VF network interface card virtualization operations and VF network interface card batch operation are carried out according to aforesaid way, specific implementation repeats no more herein.
In order to make those skilled in the art more fully understand technical solution provided by the embodiments of the present application, below with reference to specific
Application scenarios are illustrated technical solution provided by the embodiments of the present application.
Fig. 3 is referred to, is a kind of schematic diagram of concrete application scene provided by the embodiments of the present application, as shown in figure 3, at this
In embodiment, to control chip as MCPU (Management CPU, CPU management), PCIE exchange chip is set as 16 Host
Port (assuming that respectively Host Port1~Host Port16), and it is provided with NTB module and dma module, PCIE network interface card includes
For two physical ports (assuming that respectively port 1 and port 2)；Wherein, PCIE exchange chip can pass through Management
Port (management mouth) is connect with MCPU, and is connect by Downstream Port (downstream port) with PCIE network interface card.
It should be noted that can be extended by multiple cascade modes of PCIE exchange chip in practical application scene
The quantity of Host Port.
In this embodiment, after MCPU recognizes the PF of PCIE network interface card, PF driving can be loaded, and under PCIE network interface card
Send out the first configuration-direct.
When PCIE network interface card receives first configuration-direct, it is (false that port 1 can be divided into 16 first kind VF network interface cards
If respectively VF a1~VF a16), and port 2 is divided into 16 Second Type VF network interface cards (assuming that respectively VF b1~VF
b16)。
After PCIE network interface card completes VF network interface card virtualization operations, MCPU can issue the second configuration to PCIE exchange chip and refer to
It enables.
It can be respectively that each Host Port distributes a first kind when PCIE exchange chip receives the second configuration-direct
Type VF network interface card and a Second Type VF network interface card.
It is assumed that PCIE exchange chip be Host Port1 distribute VF a1 and VF b1, for Host Port2 distribute VF a2 and
VF b2 ... distributes VF a16 and VF b16 for Host Port16.
After PCIE exchange chip completes the distribution of VF network interface card, MCPU, which can control, accesses PCIE exchange core by Host Port
The CPU electrifying startup of piece.
Hereinafter for accessing the CPU (hereinafter referred to Host CPU1) of PCIE exchange chip by Host Port1
It is illustrated.
After Host CPU1 electrifying startup, PCI scanning can be carried out, establishes the virtual PCI bus domain for being subordinated to itself.
Wherein, the pci bus domain that MCPU is scanned is physics pci bus domain, and the domain PCI belonging to each HOST CPU is
Virtual PCI bus domain based on the subordinate oneself that MR-IOV technology is established.
Host CPU1 recognizes the VF network interface card (i.e. VF a1 and VF b1) for being subordinated to the virtual PCI bus domain of itself, load
VF trawl performance, and respectively to VF a1 and VF b1 configure IP address, in turn, Host CPU1 can by VF a1 with it is other
Host CPU carries out data communication, and carries out data communication by VF b1 and outer net.
In addition, Host CPU1 can also carry out data communication by NTB mode or dma mode and other Host CPU.
Wherein, Host CPU1 can be connected by PCI-PCI bridge (abbreviation P-P) and NTB module, dma module and VF network interface card
It connects.
In the embodiment of the present application, by utilizing the PCIE exchange chip and support SR-IOV function for supporting MR-IOV function
PCIE network interface card constructs a set of more HOST CPU levels connection system based on PCIE, and control chip controls PCIE network interface card virtually turns to more
A VF network interface card, and each Host Port is given respectively by PCIE exchange chip, so as to pass through the Host being arranged on PCIE exchange chip
The CPU of Port access can establish the virtual PCI bus domain of itself, and utilize distributed VF network interface card realize internally/it is external
Communication, had not only met demand of multiple CPU as Host CPU, but also was well positioned to meet multiple Host CPU and shares a physics
Network interface card realizes the demand of internal/external data communication, and directly supports the network interface of standard, and upper layer code for code compatibility is strong,
Extension is convenient.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The foregoing is merely the preferred embodiments of the application, not to limit the application, all essences in the application
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the application protection.
Claims (10)
1. a kind of more main central processing unit Host CPU level connection systems, which is characterized in that including controlling chip, CPU, peripheral hardware group
Part high speed interconnection PCIE exchange chip and PCIE network interface card, the PCIE exchange chip support more input/output virtualization MR-
IOV function, the PCIE network interface card are supported single input/output to virtualize SR-IOV function, are provided on the exchange chip more
A port Host Port, the CPU are connect by the Host Port with the exchange chip, in which:
The control chip, for issuing the first configuration-direct to the PCIE network interface card；
The PCIE network interface card, for physical port virtually to be turned to multiple virtual functions VF nets according to first configuration-direct
Card；
The control chip is also used to issue the second configuration-direct to the PCIE exchange chip；
The PCIE exchange chip, for being that each Host Port distributes VF network interface card according to second configuration-direct；
The control chip is also used to control the CPU electrifying startup；
The CPU establishes the virtual PCI bus domain of itself for after electrifying startup, carrying out peripheral component interconnection PCI scanning；
The CPU, is also used to identify the VF network interface card in the virtual PCI bus domain for being subordinated to itself, and loads VF trawl performance, passes through
The VF network interface card realizes internal/external communication.
2. more Host CPU level connection systems according to claim 1, which is characterized in that
The control chip, specifically for identifying the physical function PF of the PCIE network interface card, load PF driving, and to the PCIE
Network interface card issues the first configuration-direct.
3. more Host CPU level connection systems according to claim 1, which is characterized in that the PCIE network interface card includes the first object
Manage port and the second physical port；
The PCIE network interface card, specifically for first physical port is virtually turned to multiple first kind VF network interface cards, and by
Two physical ports virtually turn to multiple Second Type VF network interface cards；
The PCIE exchange chip is specifically used for respectively each Host Port distribution first kind VF network interface card and Second Type VF
Network interface card；
The CPU realizes internal lead to specifically for the first kind VF network interface card by being subordinated to the virtual PCI bus domain of itself
Letter, and the Second Type VF network interface card by being subordinated to the virtual PCI bus domain of itself realizes external communication.
4. more Host CPU level connection systems according to claim 1, which is characterized in that the PCIE exchange chip is also set up
There are non-transparent bridge NTB module or/and direct memory access dma module；
The CPU is also used to realize internal communication by NTB mode or/and dma mode.
5. more Host CPU level connection systems according to claim 1, which is characterized in that the CPU is integrated with graphics process
Unit GPU.
6. a kind of more main central processing unit Host CPU level linked methods, which is characterized in that be applied to include control chip, CPU,
More Host CPU levels of peripheral component high speed interconnection PCIE exchange chip and PCIE network interface card contact system, the PCIE exchange chip
Support more input/output virtualization MR-IOV functions, the PCIE network interface card supports single input/output to virtualize SR-IOV function
Can, the multiple port Host Port are provided on the exchange chip, the CPU exchanges core with described by the Host Port
Piece connection, the method also includes:
The control chip issues the first configuration-direct to the PCIE network interface card；
Physical port is virtually turned to multiple virtual functions VF network interface cards according to first configuration-direct by the PCIE network interface card；
The control chip issues the second configuration-direct to the PCIE exchange chip；
The PCIE exchange chip is that each Host Port distributes VF network interface card according to second configuration-direct；
CPU electrifying startup described in the control chip controls；
After the CPU electrifying startup, peripheral component interconnection PCI scanning is carried out, the virtual PCI bus domain of itself is established；
The CPU identification is subordinated to the VF network interface card in the virtual PCI bus domain of itself, loads VF trawl performance, passes through the VF network interface card
Realize internal/external communication.
7. according to the method described in claim 6, it is characterized in that, the control chip issues first to the PCIE network interface card matches
Set instruction, comprising:
The control chip identifies the physical function PF of the PCIE network interface card, load PF driving, and issues to the PCIE network interface card
First configuration-direct.
8. according to the method described in claim 6, it is characterized in that, the PCIE network interface card includes the first physical port and the second object
Manage port；
Physical port is virtually turned to multiple VF network interface cards according to first configuration-direct by the PCIE network interface card, comprising:
First physical port is virtually turned to multiple first kind VF network interface cards by the PCIE network interface card, and by the second physical port
Virtually turn to multiple Second Type VF network interface cards；
The PCIE exchange chip is that each Host Port distributes VF network interface card according to second configuration-direct, comprising:
The PCIE exchange chip is respectively each Host Port distribution first kind VF network interface card and Second Type VF network interface card；
The CPU realizes internal/external communication by this VF network interface card, comprising:
The CPU realizes internal communication by being subordinated to the first kind VF network interface card in the virtual PCI bus domain of itself, and passes through
The Second Type VF network interface card for being subordinated to the virtual PCI bus domain of itself realizes external communication.
9. according to the method described in claim 6, it is characterized in that, the PCIE exchange chip is additionally provided with non-transparent bridge NTB
Module or/and direct memory access dma module；
The method also includes:
The CPU realizes internal communication by NTB mode or/and dma mode.
10. according to the method described in claim 6, it is characterized in that, the CPU is integrated with graphics processing unit GPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810497465.0A CN110515869B (en) | 2018-05-22 | 2018-05-22 | Multi-Host CPU cascading method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810497465.0A CN110515869B (en) | 2018-05-22 | 2018-05-22 | Multi-Host CPU cascading method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110515869A true CN110515869A (en) | 2019-11-29 |
| CN110515869B CN110515869B (en) | 2021-09-21 |
Family
ID=68622093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810497465.0A Active CN110515869B (en) | 2018-05-22 | 2018-05-22 | Multi-Host CPU cascading method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110515869B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113630184A (en) * | 2021-08-19 | 2021-11-09 | 北京华智信科技发展有限公司 | Optical fiber communication network system |
| CN115208843A (en) * | 2022-07-13 | 2022-10-18 | 天津津航计算技术研究所 | Cascade implementation system and method for board-level domestic switch |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707991A (en) * | 2012-05-17 | 2012-10-03 | 中国科学院计算技术研究所 | Multi-root I/O (Input/Output) virtualization sharing method and system |
| CN102946366A (en) * | 2012-11-12 | 2013-02-27 | 杭州华为数字技术有限公司 | In-band management method and system |
| CN104601684A (en) * | 2014-12-31 | 2015-05-06 | 曙光云计算技术有限公司 | Cloud server system |
| US9135101B2 (en) * | 2013-03-01 | 2015-09-15 | Avago Technologies General Ip (Singapore) Pte Ltd | Virtual function timeout for single root input/output virtualization controllers |
-
2018
- 2018-05-22 CN CN201810497465.0A patent/CN110515869B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102707991A (en) * | 2012-05-17 | 2012-10-03 | 中国科学院计算技术研究所 | Multi-root I/O (Input/Output) virtualization sharing method and system |
| CN102946366A (en) * | 2012-11-12 | 2013-02-27 | 杭州华为数字技术有限公司 | In-band management method and system |
| US9135101B2 (en) * | 2013-03-01 | 2015-09-15 | Avago Technologies General Ip (Singapore) Pte Ltd | Virtual function timeout for single root input/output virtualization controllers |
| CN104601684A (en) * | 2014-12-31 | 2015-05-06 | 曙光云计算技术有限公司 | Cloud server system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113630184A (en) * | 2021-08-19 | 2021-11-09 | 北京华智信科技发展有限公司 | Optical fiber communication network system |
| CN115208843A (en) * | 2022-07-13 | 2022-10-18 | 天津津航计算技术研究所 | Cascade implementation system and method for board-level domestic switch |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110515869B (en) | 2021-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3629186B1 (en) | Method and apparatus for extending pcie domain | |
| CN106796529B (en) | Method for using PCIe device resources by using commodity type PCI switch using unmodified PCIe device driver on CPU in PCIe fabric | |
| US8683110B2 (en) | I/O system and I/O control method | |
| JP5763873B2 (en) | Method, computer program, and data processing system for initializing shared memory for communication between multiple root complexes of a data processing system | |
| US7660922B2 (en) | Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports | |
| CN105320628B (en) | Enable single I/O equipment more shared adaptive devices, system and methods | |
| CN102707991B (en) | The many virtual shared method and systems of I/O | |
| JP5362980B2 (en) | Method, program, and system for communicating between a first host system and a second host system in a data processing system (for communication between host systems using socket connections and shared memory) System and method) | |
| US9223734B2 (en) | Switch with synthetic device capability | |
| US8972611B2 (en) | Multi-server consolidated input/output (IO) device | |
| CN102650976A (en) | Control device and method supporting single IO (Input/Output) virtual user level interface | |
| US7302512B1 (en) | Interrupt steering in computing devices to effectuate peer-to-peer communications between device controllers and coprocessors | |
| US8725919B1 (en) | Device configuration for multiprocessor systems | |
| JP2008152783A (en) | Method, program, and system for communicating between first host system and second host system in data processing system (system and method for communication between host systems using transaction protocol and shared memory) | |
| EP3159802B1 (en) | Sharing method and device for pcie i/o device and interconnection system | |
| US20170060800A1 (en) | Virtualized I/O Device Sharing Within a Distributed Processing Node System | |
| EP3716084A1 (en) | Apparatus and method for sharing a flash device among multiple masters of a computing platform | |
| US20090006702A1 (en) | Sharing universal serial bus isochronous bandwidth between multiple virtual machines | |
| CN106126460A (en) | Hot-plug equipment reserves resource allocation methods, device and system | |
| CN110515869A (en) | More Host CPU level linked methods and system | |
| US20160124643A1 (en) | Direct non-volatile cache access across devices | |
| CN115023692A (en) | Peripheral component interconnect express peripheral sharing | |
| US20240211425A1 (en) | Id-based transaction routing for pcie endpoint lending | |
| US20240211418A9 (en) | Multi-function flexible computational storage device | |
| US10025736B1 (en) | Exchange message protocol message transmission between two devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |