CN110515815A - The monitoring method of board resetting test - Google Patents
The monitoring method of board resetting test Download PDFInfo
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- CN110515815A CN110515815A CN201910762638.1A CN201910762638A CN110515815A CN 110515815 A CN110515815 A CN 110515815A CN 201910762638 A CN201910762638 A CN 201910762638A CN 110515815 A CN110515815 A CN 110515815A
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- 238000012360 testing method Methods 0.000 title claims abstract description 114
- 238000012544 monitoring process Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000015654 memory Effects 0.000 claims abstract description 28
- 230000002159 abnormal effect Effects 0.000 claims description 3
- 238000013102 re-test Methods 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 3
- 238000012795 verification Methods 0.000 abstract 1
- 230000006870 function Effects 0.000 description 4
- 238000011990 functional testing Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3476—Data logging
Abstract
The present invention provides a kind of monitoring method of board resetting test, include the following steps: S1: reading the memory of chip first, and current reset type respective flag position is written, read the memory repeatedly when failure is written and carries out verification until the flag bit is written successfully；S2: judge reset test of every generation, all current reset type code position is counted and adds one；S3: judge whether the value that flag bit is written is equal compared with resetting setting value, this automatic test the type of the value i.e. veneer of flag bit is written and resets the actual frequency occurred；S4: judging whether the reset total degree counted in output journal is consistent compared with general reset setting number, the reset total degree counted in log i.e. this automation veneer general reset number.This method not only can quickly position whether current type reset test succeeds, it can be determined that epicycle tests whether to produce exceptional reset, to judge whether veneer meets design requirement accurately and in time, makes to test more efficient.
Description
Technical field
Present invention relates particularly to a kind of monitoring methods of board resetting test.
Background technique
System reset has two kinds of situations of normal reset and exceptional reset, and exceptional reset is usually surprisingly gone offline by system, is soft
Caused by part exception or hardware anomalies.In the prior art, after system resets, soft and hardware critical state information quilt
It removes, current reset test scheme can not be told in a wheel automatic test, if there is the generation of exceptional reset, thus
In automatic test course, even if exceptional reset has occurred, maintenance personnel also can not be timely and effectively in multiple reset test
In discern whether the generation of exceptional reset, can not rapidly search guilty culprit, increase the difficulty of reset test.So anxious
Need a kind of monitoring method of board resetting test to solve the problems, such as this.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to a kind of monitoring method of board resetting test is provided, it should
The monitoring method of board resetting test can well solve the above problem.
To reach above-mentioned requirements, the technical solution adopted by the present invention is that: a kind of monitoring method of board resetting test is provided,
The monitoring method of board resetting test includes the following steps:
S1: when automation reset test, the memory of chip is read first, and current reset type respective flag is written
Position is read the memory when failure is written repeatedly and is verified, until the flag bit is written successfully；
S2: judge reset test of every generation, all current reset type code position is counted and adds one；
S3: judge whether the value that flag bit is written is equal compared with resetting setting value, and the value i.e. veneer sheet of flag bit is written
Secondary automatic test the type resets the actual frequency occurred；
S4: judging whether the reset total degree counted in output journal is consistent compared with general reset setting number, log
The reset total degree of middle statistics i.e. this automation veneer general reset number.
The monitoring method of board resetting test has the advantage that as follows:
It, can be according to flag bit count value and state value in memory, no after reset test occurs in automatic test
It only can quickly position whether current type reset test succeeds, and can judge that epicycle is tested according to final output log
Whether exceptional reset is produced, to judge whether veneer meets design requirement accurately and in time, makes to test more efficient.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, at this
The same or similar part, the illustrative embodiments and their description of the application are indicated using identical reference label in a little attached drawings
For explaining the application, do not constitute an undue limitation on the present application.In the accompanying drawings:
Fig. 1 is schematically shown to be shown according to the principle of the monitoring method of the board resetting of the application one embodiment test
It is intended to.
Fig. 2 schematically shows the principles for the monitoring method tested according to the board resetting of the application one embodiment to show
It is intended to.
Fig. 3 is schematically shown to be shown according to the principle of the monitoring method of the board resetting of the application one embodiment test
It is intended to.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with drawings and the specific embodiments, to this
Application is described in further detail.
In the following description, the reference of " one embodiment ", " embodiment ", " example ", " example " etc. is shown
The embodiment or example so described may include special characteristic, structure, characteristic, property, element or limit, but not each reality
Applying example or example all necessarily includes special characteristic, structure, characteristic, property, element or limit.In addition, reuse phrase " according to
Although it is possible to be to refer to identical embodiment, but be not necessarily referring to identical embodiment for one embodiment of the application ".
For the sake of simplicity, some technical features known to those skilled in the art are omitted in being described below.
According to one embodiment of the application, a kind of monitoring method of board resetting test is provided, as shown, including such as
Lower step:
S1: when automation reset test, the memory of chip is read first, and current reset type respective flag is written
Position is read the memory when failure is written repeatedly and is verified, until the flag bit is written successfully；
S2: judge reset test of every generation, all current reset type code position is counted and adds one；
S3: judge whether the value that flag bit is written is equal compared with resetting setting value, and the value i.e. veneer sheet of flag bit is written
Secondary automatic test the type resets the actual frequency occurred；
S4: judging whether the reset total degree counted in output journal is consistent compared with general reset setting number, log
The reset total degree of middle statistics i.e. this automation veneer general reset number.
According to one embodiment of the application, the memory of the monitoring method of board resetting test is non-volatile memories
Device.
According to one embodiment of the application, the S3 of the monitoring method of board resetting test: judgement write-in flag bit
Whether value is equal compared with resetting setting value, this automatic test the type of the value i.e. veneer of flag bit is written and resets generation
The step of actual frequency, is specific further include: has respective type of count value according to different types of reset, does not execute primary reset
The count value of test, corresponding types adds one certainly；When the count value, which initially sets up value with reset test execution, to be consistent, this is indicated
Test the success of the type reset test；When the count value, which initially sets up value with reset test execution, not to be consistent, this survey is indicated
It tries the type reset test to fail, checks that output journal comparison write-in flag bit can quick position reset failure place.
According to one embodiment of the application, the S4 of the monitoring method of board resetting test: judge to unite in output journal
Whether it is consistent compared with the reset total degree of meter and general reset setting number, i.e. this is automatic for the reset total degree counted in log
The step of changing veneer general reset number is specific further include: the value is the total degree that this board resetting executes；The value includes normal
It resets, the number that exceptional reset executes；The value theoretically should be equal to normal reset and execute setting total degree；When the value and setting
When various types reset test execution number is identical, then it represents that there is no exceptional resets for this automation veneer；When the value with
When setting various types reset test execution number difference, then it represents that exceptional reset has occurred in this automation veneer, checks defeated
Log comparison write-in flag bit can quickly position exceptional reset generation place out.
According to one embodiment of the application, the memory of the monitoring method of board resetting test includes erasable
The information area and the not erasable information area, the Blip Counting position are stored in the not erasable information area.
According to one embodiment of the application, the monitoring method of board resetting test further includes following steps:
The configuration information in the register is monitored, and is determined in automatic test course according to monitored results, which deposits
There is no read-write failures for storage unit.
According to one embodiment of the application, the monitoring method of board resetting test further includes following steps:
If the data buffer register read-write is abnormal, inaccuracy is counted, resets the internal mode of the chip again
Block, and retest.
According to one embodiment of the application, the monitoring method of board resetting test
According to one embodiment of the application, the monitoring method of board resetting test
Embodiment one:
As shown in Figure 1, the present embodiment provides veneer watchdog reset test monitoring method, for automatic test course
In, the monitoring of watchdog function test, principle is:
Automatic test starts, and executes watchdog reset test, reads the memory of chip first, and current reset is written
Type respective flag position is read the memory when failure is written repeatedly and is verified, until the flag bit is written to
Function reads again the memory of chip, and read current reset type respective flag after watchdog reset test
Whether position, see consistent with current house dog test-types are written, and unanimously then indicates that current reset is watchdog reset really, different
Then indicate watchdog reset test crash；Every to execute a house dog test, the counting unit of current mark bit is from adding one, originally
After taking turns automatic test, the memory of chip is read again, and read the counting list of current reset type respective flag position
Member, with test start write-in execution number it is whether equal, it is identical, indicate epicycle automatic test watchdog reset test at
Function；It is different then indicate n times house dog test crash, it so far can quickly position watchdog reset test.
Embodiment two:
As shown in Fig. 2, the present embodiment provides veneer warm reset test monitoring method, for in automatic test course,
The monitoring of warm reset functional test, principle are:
Automatic test starts, and executes warm reset test, reads the memory of chip first, and current reset type is written
Respective flag position (different from house dog test) is read the memory when failure is written repeatedly and is verified, until institute
It states flag bit to be written successfully, after a warm reset, reads again the memory of chip, and it is corresponding to read current reset type
Whether flag bit, see consistent with current warm reset type is written, and unanimously then indicates that current reset is warm reset really, different then table
Show warm reset test crash；Warm reset of every execution test, the counting unit of current mark bit from adding one, survey by epicycle automation
After examination, the memory of chip is read again, and reads the counting unit of current reset type respective flag position, is opened with test
Whether the beginning execution number of write-in is equal, identical, indicates that epicycle automatic test warm reset is successfully tested；It is different then indicate n
Secondary warm reset failure, so far can quickly position warm reset test.
Embodiment three:
As shown in figure 3, the present embodiment provides veneer exceptional reset test monitoring method, for automatic test course
In, the monitoring of exceptional reset functional test, principle is:
Automatic test starts, random to execute watchdog reset test and warm reset test, and stipulated that testing time, sees
Door dog, which resets, is referred to as normal reset with warm reset, before each normal reset executes, reads the memory of chip first, and be written
The corresponding flag bit of current reset type reads the memory when failure is written repeatedly and is verified, until the mark
Will position is written successfully；After normal reset test, the memory of chip is read again, and read current reset type pair
Flag bit is answered, whether consistent with write-in current reset test-types sees, unanimously then indicates current reset really and be corresponding types just
Often reset, it is different then indicate normal reset test crash；It is every to execute a normal reset test, the meter of the flag bit of corresponding types
Counting unit from plus one, after epicycle automatic test, read again the memory of chip, and read corresponding normal reset type
The counting unit of respective flag position counts the execution number of each normal reset and sums, and starts the execution number of write-in with test
It is whether equal with comparing, it is identical, indicate that epicycle automatic test is not abnormal reset；It is different then indicate n times exception
It resets and generates, it is extremely multiple so far can quickly to check that current single board produces how many times in a wheel automatic test course altogether
Position, judges whether it meets design requirement.
As it can be seen that present embodiments provide three kinds of different schemes, it can be achieved that the monitoring of normal reset and exceptional reset and
Record need to only check flag bit and final output log in long memory in each round automatic test, can be accurately
The type of reset is recognized, to targetedly debug.
In conclusion above scheme through the invention, according to automated testing log, not only may be used after resetting generation
With quick position reset type, and the generation for whether having exceptional reset can be rapidly found, to survey accurately and in time
Veneer function is tried, understand board resetting execution has message, and reduces the difficulty of system testing, when shortening test investigation
Between, significantly reduce testing cost.
Embodiment described above only indicates several embodiments of the invention, and the description thereof is more specific and detailed, but not
It can be interpreted as limitation of the scope of the invention.It should be pointed out that for those of ordinary skill in the art, not departing from
Under the premise of present inventive concept, various modifications and improvements can be made, these belong to the scope of the present invention.Therefore this hair
Bright protection scope should be subject to the claim.
Claims (7)
1. a kind of monitoring method of board resetting test, which comprises the steps of:
S1: when automation reset test, reading the memory of chip first, and current reset type respective flag position be written, when
The memory is read repeatedly and is verified when write-in failure, until the flag bit is written successfully；
S2: judge reset test of every generation, all current reset type code position is counted and adds one；
S3: judge whether the value that flag bit is written is equal compared with resetting setting value, the value i.e. veneer this oneself of flag bit is written
Dynamicization tests the type and resets the actual frequency occurred；
S4: judging whether the reset total degree counted in output journal is consistent compared with general reset setting number, unites in log
The reset total degree of meter i.e. this automation veneer general reset number.
2. the monitoring method of board resetting test according to claim 1, it is characterised in that: the memory is non-volatile
Property memory.
3. the monitoring method of board resetting test according to claim 1, it is characterised in that: S3: judgement write-in flag bit
Value it is whether equal compared with resetting setting value, be written this automatic test the type of the value i.e. veneer of flag bit reset occur
Actual frequency the step of it is specific further include:
There is respective type of count value according to different types of reset, does not execute a reset test, the count value of corresponding types
From adding one；
When the count value, which initially sets up value with reset test execution, to be consistent, this test the type reset test success is indicated；
When the count value, which initially sets up value with reset test execution, not to be consistent, indicate that this test the type reset test loses
It loses, checks that output journal comparison write-in flag bit can quick position reset failure place.
4. the monitoring method of board resetting test according to claim 1, it is characterised in that: S4: judge in output journal
Whether be consistent compared with the reset total degree of statistics and general reset setting number, the reset total degree counted in log i.e. this from
The step of dynamicization veneer general reset number, is specific further include:
The value is the total degree that this board resetting executes；
The value includes the number of normal reset, exceptional reset execution；
The value theoretically should be equal to normal reset and execute setting total degree；
When the value is identical as setting various types reset test execution number, then it represents that there is no different for this automation veneer
Often reset；
When the value and setting various types reset test execute number difference, then it represents that exception has occurred in this automation veneer
It resets, checks that output journal comparison write-in flag bit can quickly position exceptional reset and place occurs.
5. the monitoring method of board resetting test according to claim 1, it is characterised in that: the memory includes erasable
Write information area and the not erasable information area, the Blip Counting position are stored in the not erasable information area.
6. the monitoring method of board resetting test according to claim 1, it is characterised in that: further include following steps:
The configuration information in the register is monitored, and is determined in automatic test course according to monitored results, piece storage is single
There is no read-write failures for member.
7. the monitoring method of board resetting test according to claim 1, it is characterised in that: further include following steps:
If the data buffer register read-write is abnormal, inaccuracy is counted, resets the internal module of the chip again, and
It retests.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910762638.1A CN110515815A (en) | 2019-08-19 | 2019-08-19 | The monitoring method of board resetting test |
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| CN201910762638.1A CN110515815A (en) | 2019-08-19 | 2019-08-19 | The monitoring method of board resetting test |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023082332A1 (en) * | 2021-11-10 | 2023-05-19 | 锐凌无线有限责任公司 | Fault recovery method and apparatus, device, and computer readable storage medium |
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| JP2003066124A (en) * | 2001-08-24 | 2003-03-05 | Ando Electric Co Ltd | Semiconductor integrated circuit tester |
| CN101110857A (en) * | 2007-08-28 | 2008-01-23 | 中兴通讯股份有限公司 | Veneer reposition monitoring method |
| JP2012108848A (en) * | 2010-11-19 | 2012-06-07 | Of Networks:Kk | Operation log collection system and program |
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Application publication date: 20191129 |