CN110505057B - Digital circuit for generating random password - Google Patents
Digital circuit for generating random password Download PDFInfo
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- CN110505057B CN110505057B CN201910758574.8A CN201910758574A CN110505057B CN 110505057 B CN110505057 B CN 110505057B CN 201910758574 A CN201910758574 A CN 201910758574A CN 110505057 B CN110505057 B CN 110505057B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0863—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving passwords or one-time passwords
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
The invention discloses a digital circuit for generating random passwords, which comprises a timing counting circuit and a password generating latch circuit. The invention provides a method for generating 2-bit true random password and latching the true random password only by enabling and then sending the true random password to a falling edge when the digital circuit is used, and the true random password can be used in parallel to generate any bit true random password. The invention has the advantages of simple manufacture, convenient use, low cost and good effect, and can be used in occasions such as coded locks and the like.
Description
Technical Field
The invention relates to the technical field of digital circuits, in particular to a digital circuit for generating a random password, which can be used in occasions needing to generate random numbers, such as a random delay module, a daily lock and the like.
Background
The generation of the random password can be divided into a hardware mode and a software mode, the random password generated by the software mode is usually a pseudo-random password, namely, the random password is not completely random, the random degree depends on a random number generation algorithm, the human randomness can be added into the hardware mode to generate a true random password, the safety degree is higher, the use is convenient, and the method is suitable for occasions needing to generate random numbers, such as a coded lock and the like.
Disclosure of Invention
The invention aims to provide a true random password generating circuit in an offline lock aiming at a pseudo random password generated by the existing networking lock, which can generate and latch 2-bit 0-9 random passwords, can improve the generation of random passwords to any number of bits by parallel connection, and can improve the stability and the safety of the lock. The invention adopts an off-line digital circuit to generate random passwords, has the characteristics of true random passwords, safety and stability, and has clear and simple circuit use flow.
The specific technical scheme for realizing the purpose of the invention is as follows:
a digital circuit for generating random password is characterized in that the circuit comprises a timing counting circuit and a password generating latch circuit, the timing counting circuit is connected with the password generating latch circuit, wherein:
the timing counting circuit comprises a power supply, a chip IC1, a chip IC2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a diode D1, a diode D2 and a plurality of output pins, wherein a pin VCC of the chip IC1 is connected with the power supply, a pin RST is connected with the power supply after being connected with a resistor R3 in series, a pin DIS is connected with the power supply after being connected with a resistor R1 in series, a pin DIS is connected with a forward diode D2 in series and connected with a resistor R2 and a backward diode D1 in parallel and then connected with a pin THR and a pin TRI, the pin THR and the pin TRI are connected with a capacitor C2 in series and then grounded, a pin CON is connected with a capacitor C1 in series and then grounded, a pin; pin A, pin B, pin C and pin D of the chip IC2 are all grounded, pin END, pin ENT, pin LOAD and pin CLR are all connected with a power supply, and pin QA, pin QB, pin QC and pin QD are respectively connected with output pins U6QA, U6QB, U6QC and U6 QD;
the password generating latch circuit comprises a power supply, a chip IC3, a chip IC4, a chip IC5, a chip IC6, a plurality of NOT gates, an AND gate, an NAND gate and a plurality of external pins;
an external pin SET1 is connected in series with a NOT gate U1E and then connected with a pin G1 of a chip IC3, the external pin SET is connected with a pin CLR of a chip IC3, an external pin NEXT is connected in series with a NOT gate U1A and then connected with a pin CLK of a chip IC3, pins A, B, C, D of the chip IC3 are respectively grounded, and a pin ENP and a pin LOAD of the chip IC3 are respectively connected with a power supply and output pins QA, QB and QC are respectively connected with a pin A, B, C of the chip IC 4; pin C of the chip IC4 is connected to a first input terminal of the nand gate U2 4, pin a is connected to the input terminal of the and gate U3 4 after being connected to the nor gate U1 4 in series, pin B is connected to the input terminal of the and gate U3 4 after being connected to the not gate U1 4 in series, the output terminal of the and gate U3 4 is connected to a second input terminal of the nand gate U2 4, the output terminal of the nand gate U2 4 is connected to pin ENT of the chip IC4, pin G2 4 and pin G2 4 of the chip IC4 are grounded, output pins Y4 and Y4 of the chip IC4 are connected to pins CLK of the not gate U1 4 and U1 4 in series respectively and to the chip IC4 and the chip IC4, pins D, 2D, 3D and 4D of the chip IC4 are connected to pins U6 4, U6, U4, U6 4 and U6 4, U3, CO 3, pin OC 3, pin CO 3, 4 and pin CO 3 of the timing counter circuit are connected respectively to the chip 4, 4 and Q3, pins 1Q, 2Q, 3Q, and 4Q of the chip IC5 are connected to external pins CO21, CO22, CO23, and CO24, respectively.
When the invention is used, the external pin SET1 is connected with high level, the password is reset and is ready to generate random passwords when the external pin SET generates a falling edge, the external pin NEXT can generate 1-bit random passwords and latch the 1-bit random passwords by using the falling edge, the 2-bit random passwords and latch the 2-bit random passwords by adopting two falling edges, and the latched passwords can be led out through the external pins CO11, CO12, CO13, CO14, CO21, CO22, CO23 and CO 24.
When the method is used, two true random passwords with the digits from 0 to 9 can be quickly generated by sending two falling edges, and random password generation with any digit can be improved by parallel connection.
The invention provides a digital circuit-based method, which is characterized in that when in use, only an external pin SET1 is connected with a high level, then the external pin SET is sent to a falling edge to generate a 2-bit true random password and latch the true random password, and the true random password can be used in parallel to generate an arbitrary bit true random password. The invention has the advantages of simple manufacture, convenient use, low cost and good effect, and can be used in occasions such as coded locks and the like.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a timing counter circuit diagram of the present invention;
FIG. 3 is a circuit diagram of the generated cipher latch circuit of the present invention.
Detailed Description
The following describes the embodiments and operation principles of the present invention in further detail with reference to the accompanying drawings.
Referring to fig. 1, the present invention includes a timing counting circuit 1 and a generated password latch circuit 2, wherein the timing counting circuit 1 is connected with the generated password latch circuit 2.
Referring to fig. 2, the timing counting circuit 1 includes a power supply, a chip IC1, a chip IC2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a diode D1, a diode D2, and a plurality of output pins, where a pin VCC of the chip IC1 is connected to the power supply, a pin RST is connected to the power supply after being connected to the resistor R3 in series, a pin DIS is connected to the power supply after being connected to the resistor R1 in series, a pin DIS is connected to the forward diode D2 in series, a pin DIS is connected to the resistor R2 in parallel, a pin THR is connected to the pin TRI after being connected to the capacitor C2 in series, a pin CON is connected to the capacitor C1 in series and then to the ground, a pin GND, and a pin OUT is connected to a pin CLK of the chip; pin A, pin B, pin C and pin D of the chip IC2 are all grounded, pin END, pin ENT, pin LOAD and pin CLR are all connected with a power supply, and pin QA, pin QB, pin QC and pin QD are respectively connected with output pins U6QA, U6QB, U6QC and U6 QD;
referring to fig. 3, the code latch generating circuit 2 includes a power supply, a chip IC3, a chip IC4, a chip IC5, a chip IC6, a plurality of not gates, an and gate, a nand gate, and a plurality of external pins;
an external pin SET1 is connected in series with a NOT gate U1E and then connected with a pin G1 of a chip IC3, the external pin SET is connected with a pin CLR of a chip IC3, an external pin NEXT is connected in series with a NOT gate U1A and then connected with a pin CLK of a chip IC3, pins A, B, C, D of the chip IC3 are respectively grounded, and a pin ENP and a pin LOAD of the chip IC3 are respectively connected with a power supply and output pins QA, QB and QC are respectively connected with a pin A, B, C of the chip IC 4; pin C of the chip IC4 is connected to a first input terminal of the nand gate U2 4, pin a is connected to the input terminal of the and gate U3 4 after being connected to the nor gate U1 4 in series, pin B is connected to the input terminal of the and gate U3 4 after being connected to the not gate U1 4 in series, the output terminal of the and gate U3 4 is connected to a second input terminal of the nand gate U2 4, the output terminal of the nand gate U2 4 is connected to pin ENT of the chip IC4, pin G2 4 and pin G2 4 of the chip IC4 are grounded, output pins Y4 and Y4 of the chip IC4 are connected to pins CLK of the not gate U1 4 and U1 4 in series respectively and to the chip IC4 and the chip IC4, pins D, 2D, 3D and 4D of the chip IC4 are connected to pins U6 4, U6, U4, U6 4 and U6 4, U3, CO 3, pin OC 3, pin CO 3, 4 and pin CO 3 of the timing counter circuit are connected respectively to the chip 4, 4 and Q3, pins 1Q, 2Q, 3Q, and 4Q of the chip IC5 are connected to external pins CO21, CO22, CO23, and CO24, respectively.
Examples
The present embodiment employs the following devices: the chip IC1 is NE555, the chip IC2 and the IC3 are all 74LS160N, the chip IC4 is 74LS138N, and the chip IC5 and the IC6 are all 74LS 374N; and gate is 74LS 08N; the NOT gate is 74LS 04N; the nand gate is 74LS 00N.
The invention is applied as follows: the invention is suitable for electronic circuits which need to generate random password functions, such as a password lock which generates passwords randomly.
The circuit has clear and simple signal flow, and specific working conditions are as follows, when in use, the external pin SET1 is connected with high level to enable the function of generating the password, when the external pin SET generates a falling edge, the password is reset and is ready to generate a random password, when the external pin NEXT uses the falling edge, a 1-bit random password can be generated and latched, when two falling edges are adopted, a 2-bit random password can be generated and latched, and the latched random password can be led out through the external pins CO11, CO12, CO13, CO14, CO21, CO22, CO23 and CO 24.
The invention works as follows:
after power-on, the timing counting area starts to work, and the OUT pin of the NE555 chip IC1 can generate 10ms pulse, so that the 74LS160N chip IC2 performs the counting back and forth from 0 to 9 for random selection in the random password generation. In the code generation area, the SET1 pin is connected with low level, the SET pin is connected with a falling edge, then the 74LS160N chip IC3 is reset, counting is started from 0, a two-bit code is prepared to be generated, the count of the 74LS160N chip IC3 is increased by connecting the falling edge with the NEXT pin, meanwhile, the output signal of the 74LS160N chip IC3 is gated by the 74LS138N chip IC4, so that the 74LS374 chip IC5 and the IC6 are controlled to latch the random code, the two-bit random code is further generated, and the random code can be led out in a binary number form through an external pin.
Claims (1)
1. A digital circuit for generating a random cipher, comprising a timing counter circuit (1) and a cipher generation latch circuit (2), said timing counter circuit (1) being connected to the cipher generation latch circuit (2), wherein:
the timing counting circuit (1) comprises a power supply, a chip IC1, a chip IC2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a diode D1, a diode D2 and a plurality of output pins, wherein a pin VCC of the chip IC1 is connected with the power supply, a pin RST is connected with the power supply after being connected with the resistor R3 in series, a pin DIS is connected with the power supply after being connected with the resistor R1 in series, a pin DIS is connected with a forward diode D2 in series and is connected with a resistor R2 and a backward diode D1 in parallel and is connected with a pin THR and a pin TRI, the pin THR and the pin TRI are connected with the capacitor C2 in series and then are grounded, a pin CON is connected with the capacitor C1 in series and then is grounded; pin A, pin B, pin C and pin D of the chip IC2 are all grounded, pin END, pin ENT, pin LOAD and pin CLR are all connected with a power supply, and pin QA, pin QB, pin QC and pin QD are respectively connected with output pins U6QA, U6QB, U6QC and U6 QD;
the password generating latch circuit (2) comprises a power supply, a chip IC3, a chip IC4, a chip IC5, a chip IC6, a plurality of NOT gates, an AND gate, a NAND gate and a plurality of external pins;
an external pin SET1 is connected in series with a NOT gate U1E and then connected with a pin G1 of a chip IC3, the external pin SET is connected with a pin CLR of a chip IC3, an external pin NEXT is connected in series with a NOT gate U1A and then connected with a pin CLK of a chip IC3, pins A, B, C, D of the chip IC3 are respectively grounded, and a pin ENP and a pin LOAD of the chip IC3 are respectively connected with a power supply and output pins QA, QB and QC are respectively connected with a pin A, B, C of the chip IC 4; pin C of the chip IC4 is connected to a first input terminal of the nand gate U2 4, pin a is connected to the input terminal of the and gate U3 4 after being connected to the nor gate U1 4 in series, pin B is connected to the input terminal of the and gate U3 4 after being connected to the not gate U1 4 in series, the output terminal of the and gate U3 4 is connected to a second input terminal of the nand gate U2 4, the output terminal of the nand gate U2 4 is connected to pin ENT of the chip IC4, pin G2 4 and pin G2 4 of the chip IC4 are grounded, output pins Y4 and Y4 of the chip IC4 are connected to pins CLK of the not gate U1 4 and U1 4 in series respectively and to the chip IC4 and the chip IC4, pins D, 2D, 3D and 4D of the chip IC4 are connected to pins U6 4, U6, U4, U6 4 and U6 4, U3, CO 3, pin OC 3, pin CO 3, 4 and pin CO 3 of the timing counter circuit are connected respectively to the chip 4, 4 and Q3, pins 1Q, 2Q, 3Q, and 4Q of the chip IC5 are connected to external pins CO21, CO22, CO23, and CO24, respectively;
when the password lock is used, the external pin SET1 is connected with a high level, the password is reset and is ready to generate a random password when the external pin SET generates a falling edge, the external pin NEXT generates a 1-bit random password and latches the 1-bit random password by using the falling edge, a 2-bit random password is generated and latched by adopting two falling edges, and the latched password is led out through the external pins CO11, CO12, CO13, CO14, CO21, CO22, CO23 and CO 24;
after power-on, the timing counting area starts to work, and an OUT pin of the chip IC1 generates 10ms pulse, so that the chip IC2 performs reciprocating counting from 0 to 9 for random selection during random password generation; in the code generation area, the SET1 pin is connected with low level, the SET pin is connected with a falling edge, the chip IC3 is reset, counting is started from 0, a two-bit code is prepared to be generated, the falling edge is connected with the NEXT pin, so that the counting of the chip IC3 is increased, meanwhile, an output signal of the chip IC3 is gated by the chip IC4, the chip ICs 5 and the IC6 are controlled to latch the random code, the two-bit random code is generated, and the two-bit random code is led out in a binary number form through an external pin.
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| CN201910758574.8A CN110505057B (en) | 2019-08-16 | 2019-08-16 | Digital circuit for generating random password |
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| CN201910758574.8A CN110505057B (en) | 2019-08-16 | 2019-08-16 | Digital circuit for generating random password |
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| CN110084933A (en) * | 2019-04-24 | 2019-08-02 | 华东师范大学 | A kind of steganography coded lock |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10103071A1 (en) * | 2001-01-24 | 2002-08-08 | Infineon Technologies Ag | Random number generator and method for generating a random number |
| US9485094B1 (en) * | 2014-04-21 | 2016-11-01 | Maxim Integrated Products, Inc. | Systems and methods for stable physically unclonable functions |
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| US7412053B1 (en) * | 2002-10-10 | 2008-08-12 | Silicon Image, Inc. | Cryptographic device with stored key data and method for using stored key data to perform an authentication exchange or self test |
| CN1633058A (en) * | 2004-12-21 | 2005-06-29 | 陈嘉农 | Vehicle locating alarm device with random cipher theft proof capability and based on network function |
| CN102304994A (en) * | 2011-06-14 | 2012-01-04 | 佛山市顺德区安能保险柜制造有限公司 | Electronic lock with function of automatically generating password and control method thereof |
| CN102642664A (en) * | 2012-05-02 | 2012-08-22 | 王明辉 | Anti-counterfeiting bottle with random coded lock and anti-counterfeiting method |
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