CN110504213B - Wafer processing method - Google Patents

Wafer processing method Download PDF

Info

Publication number
CN110504213B
CN110504213B CN201910393174.1A CN201910393174A CN110504213B CN 110504213 B CN110504213 B CN 110504213B CN 201910393174 A CN201910393174 A CN 201910393174A CN 110504213 B CN110504213 B CN 110504213B
Authority
CN
China
Prior art keywords
wafer
laser beam
processing
irradiated
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910393174.1A
Other languages
Chinese (zh)
Other versions
CN110504213A (en
Inventor
吉川敏行
北村宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of CN110504213A publication Critical patent/CN110504213A/en
Application granted granted Critical
Publication of CN110504213B publication Critical patent/CN110504213B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/38Removing material by boring or cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67092Apparatus for mechanical treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]

Abstract

Provided is a wafer processing method capable of suppressing the occurrence of processing failure in wafer dicing. The wafer processing method comprises the following steps: a calculation step of determining the size of a region to be secured on both sides of a planned dividing line of an irradiated laser beam based on the influence of the deviation of heat conduction generated on a wafer due to the irradiation of the laser beam, and calculating a value satisfying N < 2 when the number of columns of devices included in the region is N n 2 minimum of (2) n ;2 n A processing step of dividing the predetermined line by the minimum 2 n The interval of the strips irradiates laser beams on the preset lines to form processing marks on the wafer; and a halving step of repeating the step of forming a processing mark on the wafer by irradiating a laser beam on a dividing line which halves the number of columns of devices included in a plurality of areas divided by the processing mark until the number of columns of devices included in the area divided by the processing mark is 1.

Description

Wafer processing method
Technical Field
The present invention relates to a method for processing a wafer by irradiating a laser beam.
Background
The wafer on which the plurality of devices are formed is divided along the dividing lines (streets), thereby obtaining a plurality of device chips each including the device. The wafer is divided, for example, using a cutting device having a spindle as a rotation axis. The cutting tool attached to the front end portion of the spindle of the cutting device is rotated and the cutting tool is cut into the wafer along the line to cut, thereby cutting the wafer along the line to cut.
In the dicing of wafers using a dicing apparatus, various proposals have been made for preventing defective processing of device chips and breakage of a dicing tool. For example, patent document 1 discloses the following method: the wafer is first divided into two wafer pieces having substantially the same area, and then the wafer pieces are further divided into two wafer pieces having substantially the same area, and the above steps are repeated to divide the wafer into a plurality of device chips.
According to the above method, the areas of the wafer on both sides separated by the line to be cut by the cutting tool are substantially the same, and the load applied to the cutting tool during cutting is equal on the front side and the back side. Thus, occurrence of processing failure such as chipping and cracking of the device chip can be suppressed.
On the other hand, a method of using a laser processing apparatus for dividing a wafer instead of a cutting apparatus has been proposed. In this method, a laser beam having a wavelength that is absorptive to a wafer is irradiated along a predetermined dividing line to divide the wafer. Patent document 2 discloses a wafer processing method in which a pulse-oscillated laser beam is irradiated to a line to divide a wafer to form a processing mark (groove), and the wafer is divided along the processing mark.
Patent document 1: japanese patent laid-open No. 4-245663
Patent document 2: japanese patent laid-open No. 10-305420
When a wafer is processed using a laser processing apparatus as described above, a processing failure such as a defect or a crack called chipping may occur in the wafer for some reason, resulting in a reduction in the yield of device chips.
Disclosure of Invention
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a wafer processing method capable of suppressing occurrence of processing failure when dividing a wafer by irradiation of a laser beam.
According to the present invention, there is provided a wafer processing method for processing a wafer having devices formed in a plurality of regions defined by a plurality of predetermined dividing lines by irradiating a laser beam along the predetermined dividing lines, the wafer processing method comprising: a calculation step of determining the size of a region to be secured on both sides of the line to be divided to which the laser beam is irradiated, based on the influence of the deviation of heat conduction generated on the wafer due to the irradiation of the laser beam, and calculating a value satisfying N < 2 when the number of columns of the devices included in the region is N n 2 minimum of (2) n Wherein N is a natural number and N is a natural number; 2 n A processing step of dividing the predetermined line by the minimum 2 n The spacing of the strips is opposite to the divisionIrradiating the laser beam with a predetermined line to form a processing mark on the wafer; and halving the processing procedure, repeating the procedure of forming the processing trace on the wafer by irradiating the laser beam on the dividing line which halves the number of columns of the devices respectively contained in the plurality of areas divided by the processing trace until the number of columns of the devices contained in the areas divided by the processing trace is 1.
In addition, the method may be as defined in the above item 2 n In the processing step, after the laser beam is irradiated along the predetermined dividing line closest to the end of the wafer to form the processing mark having a depth for cutting the wafer, the laser beam is irradiated along the minimum 2 of the predetermined dividing line n The laser beam is irradiated to the other predetermined dividing line at intervals of the bars.
In addition, in the present invention, the wafer may be a GaAs wafer.
In the wafer processing method of the present invention, the wafer is processed by repeating the following steps: first, processing marks are formed on a wafer at predetermined intervals by irradiation of a laser beam, and then, the processing marks are further formed by irradiation of the laser beam so as to halve the number of columns of devices included in a plurality of regions divided by the processing marks. Accordingly, variations in heat conduction due to irradiation of the laser beam can be suppressed, and thus processing defects due to variations in heat conduction can be suppressed, and the yield of device chips can be improved.
Drawings
Fig. 1 is a perspective view showing a structural example of a wafer.
Fig. 2 is a perspective view of a wafer in a state of being supported by a frame.
Fig. 3 is a perspective view schematically showing a state in which a wafer is supported by a laser processing apparatus.
Fig. 4 is a plan view showing a case where a wafer is divided into a 1 st area and a 2 nd area.
Fig. 5 is a plan view showing a case where the 2 nd region is divided into the 3 rd region and a plurality of 4 th regions.
Fig. 6 is a plan view showing a case where the 4 th area is divided into two 5 th areas.
Fig. 7 is a plan view showing a case where the 5 th area is divided into two 6 th areas.
Description of the reference numerals
11: a wafer; 11a: a front face; 11b: a back surface; 13a: 1 st division of a predetermined line; 13b: dividing the preset line; 15: a device; 17: dicing tape; 19: a frame; 21: a wafer; 21a: region 1; 21b: region 2; 21c: region 3; 21d: region 4; 21e: region 5; 21f: region 6; 23a: 1 st division of a predetermined line; 23b: dividing the preset line; 2: a laser processing device; 4: a chuck table; 6: a laser processing unit; 8: a housing; 10: a condenser; 12: and a photographing member.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a perspective view showing a structural example of a wafer according to the present embodiment. As shown in fig. 1, the wafer 11 is formed in a disk shape having a front surface 11a and a rear surface 11 b. As the wafer 11, for example, a GaAs wafer can be used.
The wafer 11 is divided into a plurality of areas by a plurality of dividing predetermined lines. For example, as shown in fig. 1, the wafer 11 is divided into a plurality of regions by a plurality of 1 st division scheduled lines 13a and a plurality of 2 nd division scheduled lines 13B, wherein the plurality of 1 st division scheduled lines 13a are arranged in the 1 st direction (direction indicated by an arrow a) and are arranged in the 2 nd direction (direction indicated by an arrow B) intersecting the 1 st direction, and the plurality of 2 nd division scheduled lines 13B are arranged in the 2 nd direction and are arranged in the 1 st direction. In fig. 1, a wafer 11 is shown with the 1 st direction substantially perpendicular to the 2 nd direction.
Devices 15 each including an IC (Integrated Circuit: integrated circuit) and the like are formed on the front surface 11a side of the plurality of regions divided by the 1 st division line 13a and the 2 nd division line 13 b.
The material, shape, structure, size, and the like of the wafer 11 are not limited. For example, as the wafer 11, a wafer made of a material other than GaAs (silicon, inP, gaN, siC, etc.), ceramic, resin, metal, or the like may be used in addition to a GaAs wafer. In addition, the kind, number, shape, structure, size, arrangement, and the like of the devices 15 are not limited.
When laser beams are irradiated along the 1 st division scheduled lines 13a and the 2 nd division scheduled lines 13b, processing marks are formed due to ablation in the area of the wafer 11 where the laser beams are irradiated. When the wafer 11 is cut along the processing trace, the wafer 11 is divided into a plurality of device chips each having a device 15 formed on the front surface. The irradiation of the laser beam on the wafer 11 is performed using a laser processing apparatus.
When processing the wafer 11 by irradiation of a laser beam, the wafer 11 is first supported by a frame in order to hold the wafer 11 by a chuck table of a laser processing apparatus. Fig. 2 is a perspective view of the wafer 11 supported by the annular frame 19. The back surface 11b side of the wafer 11 is attached to the dicing tape 17 along the frame 19 having the ring shape of the outer side Zhou Niantie of the dicing tape 17, so that the front surface 11a side of the wafer 11 is exposed upward. Thereby, the wafer 11 is supported by the frame 19.
Next, the wafer 11 supported by the frame 19 is supported by a laser processing apparatus. Fig. 3 is a perspective view schematically showing a state in which the wafer 11 is supported by the laser processing apparatus 2. The laser processing device 2 includes: a chuck table 4 for holding a wafer 11; and a laser processing unit 6 that irradiates the wafer 11 held by the chuck table 4 with a laser beam having a wavelength that is absorptive to the wafer 11.
The chuck table 4 holds the wafer 11 by suction through the dicing tape 17. Specifically, the upper surface of the chuck table 4 is a holding surface for holding the wafer 11, and the holding surface is connected to a suction source (not shown) through a suction path (not shown) formed in the chuck table 4.
The wafer 11 is sucked and held in contact with the holding surface by applying a negative pressure of a suction source to the holding surface while the frame 19 is fixed by a jig (not shown) provided in the laser processing apparatus 2 and the wafer 11 is supported by the holding surface of the chuck table 4. The chuck table 4 is moved in the machining feed direction (X-axis direction) and the indexing feed direction (Y-axis direction) by a moving mechanism (not shown).
The wafer 11 is sucked and held by the chuck table 4 so that the front surface 11a is exposed upward. Fig. 3 shows a case where the wafer 11 is held so that the 1 st direction of the wafer 11 substantially coincides with the X-axis direction and the 2 nd direction of the wafer 11 substantially coincides with the Y-axis direction. In this state, laser beams are irradiated from the laser processing unit 6 along the plurality of 1 st division lines 13a, and a linear processing mark is formed on the wafer 11.
The laser processing unit 6 has a cylindrical housing 8. A YAG laser oscillator or YVO provided in the laser processing device 2 is attached to the front end of the case 8 4 A condenser 10 for condensing a pulse laser beam oscillated by a pulse laser beam oscillator (not shown) such as a laser oscillator.
Further, an imaging member 12 for imaging a processing region (irradiation region of the laser beam) of the wafer 11 is mounted on the housing 8. The image obtained by the imaging means 12 is used for image processing such as pattern matching in which the condenser 10 is aligned with the 1 st division line 13a or the 2 nd division line 13 b. Thereby, the irradiation position of the laser beam can be adjusted.
When irradiating the wafer 11 with a laser beam, the chuck table 4 is moved to a position below the condenser 10, and the laser beam having a wavelength that is absorptive to the wafer 11 is converged by the condenser 10 and irradiated toward the 1 st division line 13a, while the chuck table 4 is moved in the processing feed direction (X-axis direction). Thus, a laser beam is irradiated along the 1 st line 13a to form a processing mark composed of a linear groove on the wafer 11.
When the wafer 11 is divided by irradiation with the laser beam, a processing trace having a depth at which the wafer 11 is cut is formed along the 1 st line 13 a. For example, by irradiating the laser beam a plurality of times along the same 1 st division line 13a, a processing trace of a depth at which the wafer 11 is cut can be formed. In this case, the number of times of irradiation of the laser beam is appropriately set so that the wafer 11 can be cut.
Irradiation of the laser beam on the 2 nd division scheduled line 13b is also performed in the same manner as the 1 st division scheduled line 13 a. Specifically, the chuck table 4 is rotated 90 ° in the horizontal direction (XY plane direction) so that the 1 st direction of the wafer 11 substantially coincides with the Y axis direction, and the 2 nd direction of the wafer 11 substantially coincides with the X axis direction, and then the same operation is performed. In this way, when all the 1 st division scheduled line 13a and the 2 nd division scheduled line 13b are cut, the wafer 11 is divided into a plurality of device chips each including the device 15.
Here, the order of irradiating the laser beam to the predetermined lines of division is considered. For example, when laser beams are sequentially irradiated from one end portion toward the other end portion in the 2 nd direction of the wafer 11 to the 1 st division scheduled lines 13a arranged along the 2 nd direction, variations occur in the volumes of the regions on both sides separated by the 1 st division scheduled lines 13a to which the laser beams are irradiated.
Specifically, a laser beam is first irradiated along a 1 st division line 13a (hereinafter, the outermost 1 st division line 13 a) closest to one end portion of the wafer 11 in the 2 nd direction. At this time, the volume of the region including the one end portion out of the two regions of the wafer 11 divided by the 1 st division line 13a on the outermost side is smaller than the volume of the other region.
Such a variation in volume causes variation in heat conduction due to irradiation of the laser beam. That is, when the 1 st division scheduled line 13a is irradiated with a laser beam, heat is generated, and the heat is conducted inside the wafer 11. Here, when there is a variation in volume in the two regions of the wafer 11 divided by the 1 st division line 13a of the laser beam to be irradiated, the conduction path of heat is further limited in the region where the volume is small, and therefore the heat cannot be sufficiently diffused and the temperature is easily raised.
In addition, when the wafer 11 on which the processing marks (grooves) have been formed along the plurality of 1 st division lines 13a is irradiated with a laser beam, the processing marks prevent heat conduction, and a variation in heat conduction occurs. Specifically, when the laser beam is irradiated along the 1 st division scheduled line 13a located in the region between the two processing marks of the wafer 11, the region is further divided into two small regions. Here, when the volumes of the two small areas are different, the conduction path of heat may be further limited in the small-sized area.
When dividing the wafer 11 by irradiation with a laser beam, a processing failure such as chipping or cracking may occur in the wafer 11, and it is assumed that one of the reasons for this is that there is a deviation in heat conduction on both sides of the region where the laser beam is irradiated, and a temperature difference occurs. Therefore, it is preferable to irradiate the laser beam on the wafer 11 under the condition that the deviation of the heat conduction on both sides of the region to which the laser beam is irradiated is small.
In the present embodiment, the order of irradiating the laser beam to the planned dividing line is set so that the volumes of the regions located on both sides of the planned dividing line to which the laser beam is irradiated do not differ significantly. This can suppress variations in heat conduction due to volume differences, and thus can suppress processing defects when processing the wafer 11 with the laser beam.
In the wafer processing method according to the present embodiment, first, the interval of irradiation of the laser beam is set according to the influence of the deviation of heat conduction due to irradiation of the laser beam. Then, laser beams are irradiated along the 1 st division line 13a of the wafer 11 at this interval, and a linear processing mark is formed on the wafer 11. Then, the 1 st division line 13a which bisects the number of columns of devices included in the plurality of regions divided by the processing mark is irradiated with a laser beam to further form the processing mark, and the processing mark is formed along all the 1 st division lines 13 a.
By using the above-described wafer processing method, the volume difference between the two regions separated by the region to which the laser beam is irradiated can be reduced, and processing failure can be suppressed. The irradiation of the laser beam on the 2 nd division line 13b is also performed by the same method.
The wafer processing method according to the present embodiment will be described in detail below. In the following, the following will be described by way of example: the wafer 21 having the devices 15 formed in the regions divided by the 25 1 st division lines 23a and the 25 2 nd division lines 23b is irradiated with laser beams to form processing marks (see fig. 4, 5, 6, and 7). 24 columns of devices 15 are formed on the wafer 21 in the 1 st direction (the direction indicated by the arrow a) and the 2 nd direction (the direction indicated by the arrow B), respectively.
< calculation procedure >)
In the wafer processing method according to the present embodiment, a calculation step is first performed, and a subsequent step (2 n A processing step) is performed at intervals at which the 1 st division line 23a is irradiated with a laser beam.
The interval of irradiation of the laser beam is set based on the influence of the deviation of heat conduction generated on the wafer 21 due to the irradiation of the laser beam. For example, the interval between the irradiation laser beams is set so that processing defects (chipping, cracking, etc.) due to variations in heat conduction occurring in the two regions of the wafer 21 divided by the 1 st division line 23a of the irradiated laser beams do not occur, or the frequency of occurrence is set to be equal to or less than a predetermined value.
Even if there is a difference in volume between two regions located on both sides of the irradiation region of the laser beam, if the volumes of these regions are each ensured to be equal to or greater than a certain value, the heat conduction due to the irradiation of the laser beam is substantially equal in the two regions, and processing failure due to variation in heat conduction is less likely to occur. Therefore, in the calculation step, the interval of the irradiation of the laser beam is calculated so that regions having a volume equal to or greater than a predetermined volume are secured on both sides of the irradiation region of the laser beam.
Specifically, the size of the region to be secured on both sides of the 1 st division line 23a of the irradiated laser beam is first determined based on the influence of the deviation of heat conduction generated on the wafer 21 due to the irradiation of the laser beam. For example, the size of the region is determined so that machining defects (chipping, cracking, and the like) due to variations in heat conduction are not generated or the frequency of occurrence is not higher than a predetermined value. The size of the region may be determined so that the temperature difference between the two regions located on both sides of the 1 st division line 23a to which the laser beam is irradiated is equal to or less than a predetermined value.
The size of the above-mentioned region may be determined based on one or more factors selected from the material (particularly, thermal conductivity) of the wafer 21, the thickness of the wafer 21, the size of the devices 15, the intervals of the devices 15, the wavelength of the laser beam, the intensity of the laser beam, and the like, for example. In this case, the relationship between the influence of the deviation of the heat conduction (such as the frequency of the machining failure and the degree of the temperature difference) and the respective elements may be grasped in advance by experiments, and the size of the region to be secured on both sides of the irradiation region of the laser beam may be determined from the respective elements.
Next, the number of columns N (N is a natural number) of the devices 15 (the number of the devices 15 in the 2 nd direction) included in the region to be secured on both sides of the 1 st division line 23a is determined. Then, based on the value of N, a value satisfying N < 2 is calculated n (n is a natural number) minimum 2 n Is a value of (2). The smallest 2 n Is the value to be calculated in the calculation process.
For example, in the case where the regions of 3 or more columns of devices 15 are to be secured on both sides of the 1 st division line 23a to which the laser beam is irradiated, n=3, 2 to be calculated in the calculation step n The value of (2) is 3 < 2 n 2 minimum of (2) n The value of (2) is 4. And, the 1 st division scheduled line 23a is the smallest 2 n The spacing of the strips is equal to 2 n The interval of laser beam irradiation in the processing step corresponds to that.
<2 n Processing procedure >
Next, embodiment 2 n A processing step of calculating 2 based on the minimum calculated in the calculating step n The smallest value 2 of the predetermined dividing line 23a according to the 1 st n The spaces of the bars irradiate the wafer 21 with a laser beam. For example, at a minimum of 2 n When the value of (2) is 4, the laser beams are irradiated to the 1 st division scheduled lines 23a at 4 intervals. In the following description, the term "2" is abbreviated as "2 n In the case of (2), the minimum value calculated in the calculation step is represented by 2 n
Using FIGS. 4, 5 to 2 n An example of the processing step is described. At 2 n In the processing step, first, a laser beam is irradiated along a 1 st division line 23a (an outermost 1 st division line 23 a) closest to one end portion of the wafer 21 in the 2 nd direction.
By irradiation with the laser beam, a linear processing mark L1 is formed on the 1 st division line 23a on the outermost side, and the wafer 21 is divided into a 1 st region 21a including the one end portion and a 2 nd region 21b in which the plurality of devices 15 are formed. Fig. 4 is a plan view showing a case where the wafer 21 is divided into the 1 st region 21a and the 2 nd region 21b.
Then, the 1 st division line 23a at the outermost distance is 2 n The other 1 st division line 23a is irradiated with a laser beam at the interval of the bars. For example at 2 n When the value of (2) is 4, the laser beams are irradiated to the 1 st division scheduled lines 23a at 4 intervals. As a result, every 2 th division line 23a in the plurality of 1 st division lines n Linear processing marks L2 are formed at the intervals of the strips.
By the formation of the processing mark L2, the 2 nd region 21b is divided into a 3 rd region 21c located on the opposite side of the 1 st region 21a in the 2 nd direction and 2 nd regions arranged in the 2 nd direction n A plurality of 4 th regions 21d of the column device 15. Fig. 5 is a plan view showing a case where the 2 nd region 21b is divided into the 3 rd region 21c and the 4 th regions 21d.
For example, when laser beams are irradiated to a plurality of 1 st division lines 23a at 4 intervals, 6 processing marks L2 are formed in the 2 nd region 21b as shown in fig. 5. Thereby, the 2 nd region 21b is divided into the 3 rd region 21c and six 4 th regions 21d in which 4 columns of devices 15 are arranged in the 2 nd direction.
Through the above 2 n And a processing step of dividing the wafer 21 into a plurality of regions. At 2 n In the processing step, N or more rows of regions of the device 15 are ensured between the 1 st division lines 23a on which the laser beam is irradiated. Therefore, even if heat conduction is hindered by the processing marks L1 and L2, heat generated when the laser beam is irradiated to the 1 st division line 23a can be sufficiently diffused, and occurrence of processing failure due to deviation of heat conduction can be suppressed.
In addition, at 2 n In the processing step, the same 1 st division line 23a may be irradiated with a laser beam a plurality of times to form a processing mark L1 and a processing mark L2 having a depth at which the wafer 21 is cut. In this case, the order of irradiation of the laser beams can be freely set.
For example, after the laser beam is irradiated a plurality of times to the 1 st division scheduled line 23a on the outermost side to form the processing mark L1 of the depth at which the wafer 21 is cut, the laser beam is irradiated a plurality of times to the other 1 st division scheduled lines 23a to form the processing mark L2 of the depth at which the wafer 21 is cut. Further, the process of irradiating the outermost 1 st line 23a and the other 1 st line 23a with a laser beam may be repeated to form the processing mark L1 and the processing mark L2 at the depth of cutting the wafer 21.
< halving procedure >)
Then, a halving process is performed, and the process of passing 2 is repeated n And irradiating the laser beam on the dividing lines which are approximately halved in the plurality of 4 th regions 21d obtained in the processing step.
First, a 1 st division line 23a is selected which bisects the number of columns in the 2 nd direction of the devices 15 included in the 4 th region 21d, and a laser beam is irradiated along the 1 st division line 23 a.
By irradiation with the laser beam, linear processing marks L3 each halving the number of columns in the 2 nd direction of the device 15 are formed in the 4 th region 21d, and the 4 th region 21d is divided into two regions each having 2 in the 2 nd direction n-1 Two 5 th regions 21e of the column of devices 15. Fig. 6 is a plan view showing a case where the 4 th region 21d is divided into two 5 th regions 21e, respectively.
When the laser beam is irradiated to the 4 th region 21d, the laser beam is irradiated so as to halve the number of columns in the 2 nd direction of the devices included in the 4 th region 21d, and therefore the volumes of the 4 th regions 21d located on both sides of the region to which the laser beam is irradiated are substantially equal. Therefore, the deviation of heat conduction when the laser beam is irradiated is small, and processing failure due to the deviation of heat conduction is not easily generated.
In the halving process, the same 1 st division line 23a may be irradiated with a laser beam a plurality of times to form a processing mark L3 having a depth at which the 4 th region 21d is cut. In this case, the order of irradiation of the laser beams can be freely set.
For example, after one 1 st division line 23a is irradiated with a laser beam a plurality of times to form one processing trace L3, another 1 st division line 23a may be irradiated with a laser beam to form another processing trace L3. Further, the step of irradiating each of the plurality of 1 st division lines 23a, which substantially halve the 4 th region 21d, with a laser beam once may be repeated to form a plurality of processing marks L3.
In addition, the device 15 may be included in the 3 rd region 21c according to the number of columns of the device 15. In this case, the 1 st division line 23a is selected to bisect the number of columns in the 2 nd direction of the devices 15 included in the 3 rd region 21c, and a laser beam is irradiated. When the number of columns of devices included in the 3 rd region 21c is an odd number, the 1 st division line 23a may be selected so that the volume difference between regions located on both sides of the 1 st division line 23a to which the laser beam is irradiated is minimized.
Next, the 5 th region 21e is irradiated with a laser beam in the same manner, and the 5 th region 21e is further approximately halved. That is, a linear processing mark L4 is formed in the 5 th region 21e so as to halve the number of columns of the device 15 in the 2 nd direction. Thereby dividing the 5 th region 21e into having 2 in the 2 nd direction n-2 Two 6 th regions 21f of the column of devices 15. Fig. 7 is a plan view showing a case where the 5 th region 21e is divided into two 6 th regions 21f, respectively.
When the 5 th region 21e is irradiated with a laser beam, the volumes of the 5 th regions 21e located on both sides of the region to which the laser beam is irradiated are substantially equal to each other, as in the case of irradiating the 4 th region 21d with a laser beam (see fig. 6). Therefore, the deviation of heat conduction when the laser beam is irradiated is small, and processing failure due to the deviation of heat conduction is not easily generated.
In the halving process, the same 1 st division line 23a may be irradiated with a laser beam a plurality of times to form a processing mark L4 having a depth at which the 5 th region 21e is cut. In this case, the order of irradiation of the laser beams can be freely set.
For example, after one processing trace L4 is formed by irradiating a laser beam a plurality of times to one 1 st division scheduled line 23a, the laser beam may be irradiated to another 1 st division scheduled line 23 a. Further, the step of irradiating each of the plurality of 1 st division lines 23a, which substantially halve the 5 th region 21e, with a laser beam once may be repeated to form a plurality of processing marks L4.
As described above, the step of forming the processing mark by irradiating the 1 st division line 23a which bisects the number of columns of the devices 15 included in the plurality of regions divided by the processing mark with a laser beam is repeated, and the wafer 21 is divided into a plurality of regions including 1 column of the devices 15.
In addition, at 2 n In the processing step, the wafer 21 is divided into the sections 2 by the processing marks L1 and L2 n A plurality of 4 th regions 21d (see fig. 5) of the devices 15 of the column. Therefore, if the step of halving the number of columns of the device 15 is repeated, the laser beam can be irradiated to all the 1 st division lines 23a included in the 4 th region 21d.
After the irradiation of the laser beams on all the 1 st division scheduled lines 23a is completed, the irradiation of the laser beams on the 2 nd division scheduled lines 23b is performed by the same process. Specifically, the chuck table 4 shown in fig. 3 is first rotated by 90 ° in the horizontal direction so that the 1 st direction of the wafer 21 and the Y-axis direction substantially coincide, and the 2 nd direction of the wafer 21 and the X-axis direction substantially coincide.
Then, the calculation step 2 is performed on the 2 nd division line 23b n And (3) a processing procedure and a halving processing procedure. In addition, 2 when the laser beam is irradiated to the 2 nd division line 23b n The value of (2) is equal to 2 when the laser beam is irradiated to the 1 st division line 23a n The values of (2) may be the same or different.
Through the above-described steps, processing marks are formed on all of the 1 st division scheduled line and the 2 nd division scheduled line 23 b. In the case where these processing marks are processing marks of a depth at which the wafer 21 is cut, the wafer 21 is divided into a plurality of device chips each having the device 15.
As described above, in the wafer processing method according to the present embodiment, the step of irradiating the laser beam on the dividing line which substantially bisects the 4 th region 21d formed by dividing the processing mark L1 and the processing mark L2 is repeated. Thus, the volumes of both sides of the region to which the laser beam is irradiated are substantially the same, and variation in heat conduction due to irradiation of the laser beam can be suppressed. Therefore, processing defects due to variations in heat conduction can be suppressed, and the yield of device chips can be improved.
In addition, when the same 1 st line 23a is irradiated with the laser beam a plurality of times to form a processing mark having a depth at which the wafer 21 is cut, the pass 2 can be appropriately set n A machining process and a halving the machining process to irradiate the laser beam. For example, it can be at 2 n In the machining step, the wafer 21 is irradiated with the laser beam a plurality of times to divide the wafer 21 into a plurality of 4 th regions 21d, and then in the halving machining step, the 4 th regions 21d are irradiated with the laser beam.
In addition, the wafer 21 may be divided by irradiating each of the 1 st division lines 23a with a laser beam once in the order shown in fig. 4 to 7, and then repeating the same operation.
In the above-described embodiment, the example of irradiating the laser beam to the 2 nd division target line 23b was described in the same manner after the step of irradiating the laser beam to all the 1 st division target lines 23a was completed, but the order of irradiating the laser beam is not limited thereto. For example, irradiation of the laser beam to the 1 st division scheduled line 23a and irradiation of the laser beam to the 2 nd division scheduled line 23b may be alternately performed. In this case, each time the laser beam is irradiated to the predetermined line of division, an operation of rotating the chuck table 4 shown in fig. 3 by 90 ° in the horizontal direction is performed.
In addition, the structure, method, and the like of the above embodiment can be modified and implemented as appropriate without departing from the scope of the object of the present invention.

Claims (3)

1. A method for processing a wafer by irradiating a laser beam along a line to divide the wafer, the method comprising the steps of:
a calculation step of determining the laser beam to be irradiated on the wafer based on the influence of the deviation of heat conduction generated on the wafer due to the irradiation of the laser beamThe size of the region to be secured on both sides of the dividing line is calculated to satisfy N < 2 when the number of columns of the device included in the region is N n 2 minimum of (2) n Wherein N is a natural number and N is a natural number;
2 n a processing step of dividing the predetermined line by the minimum 2 n The interval of the strips irradiates the laser beam on the preset dividing line to form a processing trace on the wafer; and
and halving the processing step, and repeating the step of forming the processing mark on the wafer by irradiating the laser beam on the dividing line which halves the number of columns of the devices respectively included in the plurality of areas divided by the processing mark until the number of columns of the devices included in the area divided by the processing mark is 1.
2. The method for processing a wafer according to claim 1, wherein,
at 2 n In the processing step, after the laser beam is irradiated along the predetermined dividing line closest to the end of the wafer to form the processing mark having a depth for cutting the wafer, the laser beam is irradiated along the minimum 2 of the predetermined dividing line n The laser beam is irradiated to the other predetermined dividing line at intervals of the bars.
3. A method for processing a wafer according to claim 1 or 2, characterized in that,
the wafer is a GaAs wafer.
CN201910393174.1A 2018-05-15 2019-05-13 Wafer processing method Active CN110504213B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-093695 2018-05-15
JP2018093695A JP7043135B2 (en) 2018-05-15 2018-05-15 Wafer processing method

Publications (2)

Publication Number Publication Date
CN110504213A CN110504213A (en) 2019-11-26
CN110504213B true CN110504213B (en) 2023-10-03

Family

ID=68585728

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910393174.1A Active CN110504213B (en) 2018-05-15 2019-05-13 Wafer processing method

Country Status (4)

Country Link
JP (1) JP7043135B2 (en)
KR (1) KR20190130961A (en)
CN (1) CN110504213B (en)
TW (1) TWI788562B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112234029B (en) * 2020-09-14 2023-06-02 佛山市国星半导体技术有限公司 Cutting method of mini LED chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010274630A (en) * 2009-06-01 2010-12-09 Daitron Technology Co Ltd Method and apparatus for dividing substrate
JP2011151186A (en) * 2010-01-21 2011-08-04 Toshiba Corp Method of dividing semiconductor wafer
CN102881782A (en) * 2011-07-11 2013-01-16 株式会社迪思科 Segmenting method of optical device substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04245663A (en) * 1991-01-31 1992-09-02 Fujitsu Ltd Semiconductor wafer dicing method and dicing blade cooling mechanism
US5750277A (en) 1996-04-10 1998-05-12 Texas Instruments Incorporated Current interrupter for electrochemical cells
JPH10305420A (en) 1997-03-04 1998-11-17 Ngk Insulators Ltd Method for fabricating matrix made up of oxide single crystal and method for manufacturing functional device
TWI237322B (en) * 2004-12-14 2005-08-01 Cleavage Entpr Co Ltd Method and device by using a laser beam to cut Gallium arsenide (GaAs) epitaxy wafer
JP2008229682A (en) 2007-03-22 2008-10-02 Epson Toyocom Corp Manufacturing method of package component
JP5515679B2 (en) 2009-11-25 2014-06-11 株式会社村田製作所 Substrate dicing method
JP5657302B2 (en) * 2010-08-04 2015-01-21 株式会社ディスコ Cutting method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010274630A (en) * 2009-06-01 2010-12-09 Daitron Technology Co Ltd Method and apparatus for dividing substrate
JP2011151186A (en) * 2010-01-21 2011-08-04 Toshiba Corp Method of dividing semiconductor wafer
CN102881782A (en) * 2011-07-11 2013-01-16 株式会社迪思科 Segmenting method of optical device substrate

Also Published As

Publication number Publication date
KR20190130961A (en) 2019-11-25
CN110504213A (en) 2019-11-26
TW201947672A (en) 2019-12-16
JP2019201067A (en) 2019-11-21
JP7043135B2 (en) 2022-03-29
TWI788562B (en) 2023-01-01

Similar Documents

Publication Publication Date Title
KR101977126B1 (en) Method of laser-machining wafer
JP5090897B2 (en) Wafer dividing method
CN109848577B (en) Laser processing method for wafer
CN106340490B (en) Method for processing wafer
JP2020178123A (en) Board processing method
KR20160088808A (en) Wafer processing method
CN108735666B (en) Method for processing object to be processed
JP5946308B2 (en) Wafer division method
CN110504213B (en) Wafer processing method
TWI736760B (en) Wafer processing method
JP5453123B2 (en) Cutting method
JP5946307B2 (en) Wafer division method
KR102445075B1 (en) Laser machining method for wafer
JP7210292B2 (en) Wafer generation method
CN110491834B (en) Method for processing object to be processed
JP2015107491A (en) Laser processing method
JP6957091B2 (en) Wafer processing method
TWI834663B (en) Processing methods of processed objects
JP6529414B2 (en) Wafer processing method
JP6710465B2 (en) Wafer processing method
JP6837712B2 (en) Wafer processing method
CN117583724A (en) Laser processing apparatus and method for manufacturing wafer
JP4280056B2 (en) Semiconductor wafer dicing method
KR20230065895A (en) Processing method
JP2022064088A (en) Wafer processing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant