CN110491862A - The manufacturing method of MIP capacitor - Google Patents
The manufacturing method of MIP capacitor Download PDFInfo
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- CN110491862A CN110491862A CN201910679659.7A CN201910679659A CN110491862A CN 110491862 A CN110491862 A CN 110491862A CN 201910679659 A CN201910679659 A CN 201910679659A CN 110491862 A CN110491862 A CN 110491862A
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- manufacturing
- mip
- layer
- mip capacitor
- capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention discloses a kind of manufacturing methods of MIP capacitor, comprising steps of forming the first polysilicon layer；Form second insulating layer；Form third metal layer；Form the forming region that the first photoetching offset plate figure defines the first electrode plate of MIP capacitor；Third metal layer is performed etching to form first electrode plate；Remove the first photoetching offset plate figure；The forming region that the second photoetching offset plate figure defines the second electrode plate of MIP capacitor is formed, on vertical view face, the edge of first electrode plate is all located inside the forming region of second electrode plate；Successively second insulating layer and first polysilicon layer are performed etching and are respectively formed dielectric layer and second electrode plate between electrode；Later, the second photoetching offset plate figure is removed.The situation that the present invention can prevent dielectric layer between the electrode plate of the edge of first electrode plate thinning and puncture MIP capacitor in advance in edge occurs, and can make the stable breakdown voltage of MIP capacitor, improve product yield.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of manufacturing method of MIP capacitor.
Background technique
It is the device architecture schematic diagram in each step of the manufacturing method of existing MIP capacitor as shown in Figure 1A to Fig. 1 E；It is existing
There is the manufacturing method of MIP capacitor to include the following steps:
Step 1: as shown in Figure 1A, forming the first polysilicon layer in the semiconductor substrate for being formed with field oxide 101
102；The forming region of the MIP capacitor is located on the field oxide 101.
In general, the semiconductor substrate is silicon substrate.
It further include forming first on 102 surface of the first polysilicon layer after forming first polysilicon layer 102
The step of metal silicide 103.
The material of first metal silicide 103 generallys use tungsten silicide.
The field oxide 101 is formed using shallow ditch groove separation process；Alternatively, the field oxide 101 uses local field
Oxygen isolation technology is formed.
The field oxide 101 isolates active area, is formed with MOS transistor in the active area.
Step 2: as shown in Figure 1A, forming second insulating layer 104.
In general, the material of the second insulating layer 104 is oxide layer.
Step 3: as shown in Figure 1A, forming third metal layer 105 on 104 surface of second insulating layer.
In general, the material of the third metal layer 105 is tungsten silicide.
Step 4: as shown in Figure 1B, carrying out being lithographically formed the first photoetching offset plate figure 106, first photoresist for the first time
Figure 106 defines the forming region of the first electrode plate 105a of the MIP capacitor.
Step 5: as shown in Figure 1 C, with first photoetching offset plate figure 106 be mask to the third metal layer 105 into
Etching forms the first electrode plate 105a to row for the first time.First time etching technics is the etching to the third metal layer 105
Technique generally corresponds to DRP technique.
Step 6: being mask then to the second insulating layer with first photoetching offset plate figure 106 as shown in figure iD
104, which carry out second, etches dielectric layer 104a between the electrode for forming the MIP capacitor.Second of etching technics is i.e. to described second
The etching technics of insulating layer 104 generally corresponds to DRE technique.
Later, first photoetching offset plate figure 106 is removed.
Step 7: being lithographically formed the second photoetching offset plate figure for the second time, second photoetching offset plate figure defines described
The forming region of the second electrode plate of MIP capacitor.
Second photoetching offset plate figure defines the forming region of the gate structure of the MOS transistor simultaneously.
Step 8: being mask to first metal silicide 103 using second photoetching offset plate figure as referring to figure 1E
Third time etching is carried out with the first polysilicon layer 102 to be formed by the first polysilicon layer 102a and first gold medal after etching
Belong to silicide 103a and is superimposed the second electrode plate to be formed；Later, second photoetching offset plate figure is removed.
The third time etching technics is formed simultaneously the gate structure of the MOS transistor.
In existing method, in the first time etching for completing step 5, second of step 6 etching and described the is removed
After one photoetching offset plate figure 106, it is thick to be easy the dielectric layer 104a between the edge of MIP capacitor is easy to happen insulating layer i.e. electrode
Degree not enough, as shown in the virtual coil 107 in Fig. 1 E, is easy first to puncture at edge 107, to will lead to hitting for MIP capacitor
It is relatively low to wear voltage (BV), reduces product yield.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of MIP capacitor, can make the breakdown of MIP capacitor
Voltage stabilization improves product yield.
In order to solve the above technical problems, the manufacturing method of MIP capacitor provided by the invention includes the following steps:
Step 1: forming the first polysilicon layer in the semiconductor substrate for be formed with field oxide；The shape of the MIP capacitor
It is located on the field oxide at region.
Step 2: forming second insulating layer.
Step 3: forming third metal layer on the second insulating layer surface.
Step 4: carrying out being lithographically formed the first photoetching offset plate figure for the first time, first photoetching offset plate figure defines described
The forming region of the first electrode plate of MIP capacitor.
Step 5: performing etching to form described first to the third metal layer using first photoetching offset plate figure as mask
Electrode plate.
Step 6: removal first photoetching offset plate figure.
Step 7: being lithographically formed the second photoetching offset plate figure for the second time, second photoetching offset plate figure defines described
The forming region of the second electrode plate of MIP capacitor, on vertical view face, the edge of the first electrode plate is all located at second electricity
Inside the forming region of pole plate.
Step 8: being mask successively to the second insulating layer and first polysilicon using second photoetching offset plate figure
Layer performs etching, and dielectric layer between the electrode of the MIP capacitor is made of the second insulating layer after etching, by the institute after etching
It states the first polysilicon layer and forms the second electrode plate；Later, second photoetching offset plate figure is removed.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the field oxide is formed using shallow ditch groove separation process；Alternatively, the field oxide is adopted
It is formed with local field oxygen isolation technology.
A further improvement is that further including in first polycrystalline after forming first polysilicon layer in step 1
Silicon surface forms the step of the first metal silicide.
A further improvement is that the material of first metal silicide is tungsten silicide.
A further improvement is that the material of the third metal layer is tungsten silicide.
A further improvement is that first metal silicide with a thickness of
A further improvement is that the third metal layer with a thickness of
A further improvement is that the material of the second insulating layer is oxide layer.
A further improvement is that the second insulating layer with a thickness of
A further improvement is that field oxide described in step 1 isolates active area, it is formed in the active area
MOS transistor.
A further improvement is that second photoetching offset plate figure in step 7 defines the MOS transistor simultaneously
The forming region of gate structure, step 8 look for that etching technics to be formed simultaneously the gate structure of the MOS transistor.
A further improvement is that the gate structure of the MOS transistor includes the gate dielectric layer that is sequentially overlapped and more
Crystal silicon grid, the polysilicon gate are made of first polysilicon layer after etching.
A further improvement is that the material of the gate dielectric layer includes oxide, nitrogen oxides or high dielectric constant material.
A further improvement is that the MOS transistor includes LDMOS.
The present invention is sequentially forming the first polysilicon layer, second insulating layer and third metal layer and is using the first photoresist
Graphic definition goes out after the forming region of first electrode plate, after finishing to the etching of third metal layer, and in the prior art
Difference then is performed etching to second insulating layer with the first photoetching offset plate figure, present invention employs removing the first photoetching offset plate figure,
It directly forms the second photoetching offset plate figure for defining the forming region of second electrode plate again later, and guarantees the first electricity on vertical view face
The edge of pole plate is all located inside the forming region of second electrode plate, is later mask successively to second using the second photoetching offset plate figure
Insulating layer and the first polysilicon layer perform etching and are respectively formed dielectric layer and second electrode plate between electrode, due to electric contrasted between solid dielectric
The edge of layer is located at the outside edges of first electrode plate, therefore the thickness of dielectric layers energy between the electrode plate of the edge of first electrode plate
Guaranteed well, so the present invention can prevent between the electrode plate of the edge of first electrode plate dielectric layer thinning and make MIP
Capacitor occurs in the situation that edge punctures in advance, can make the stable breakdown voltage of MIP capacitor, improves product yield.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 E is the device architecture schematic diagram in each step of the manufacturing method of existing MIP capacitor；
Fig. 2 is the flow chart of the manufacturing method of MIP capacitor of the embodiment of the present invention；
Fig. 3 A- Fig. 3 F is the device architecture schematic diagram in each step of the manufacturing method of MIP capacitor of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, being the flow chart of the manufacturing method of MIP capacitor of the embodiment of the present invention；As shown in Fig. 3 A to Fig. 3 F, it is
Device architecture schematic diagram in each step of the manufacturing method of MIP capacitor of the embodiment of the present invention；MIP capacitor of the embodiment of the present invention
Manufacturing method includes the following steps:
Step 1: as shown in Figure 3A, forming the first polysilicon layer 2 in the semiconductor substrate for being formed with field oxide 1；Institute
The forming region for stating MIP capacitor is located on the field oxide 1.
In the embodiment of the present invention, the semiconductor substrate is silicon substrate.
It further include forming the first metal on 2 surface of the first polysilicon layer after forming first polysilicon layer 2
The step of silicide 3.
The material of first metal silicide 3 is tungsten silicide.First metal silicide 3 with a thickness ofIn
In other embodiments, the thickness of first metal silicide 3 can be also configured according to actual needs.
The field oxide 1 is formed using shallow ditch groove separation process；Alternatively, the field oxide 1 using local field oxygen every
Separating process is formed.
The field oxide 1 isolates active area, is formed with MOS transistor in the active area.
Step 2: as shown in Figure 3A, forming second insulating layer 4.
In the embodiment of the present invention, the material of the second insulating layer 4 is oxide layer.The second insulating layer 4 with a thickness ofIn other embodiments, the thickness of the second insulating layer 4 can be also configured according to actual needs.
Step 3: as shown in Figure 3A, forming third metal layer 5 on 4 surface of second insulating layer.
In the embodiment of the present invention, the material of the third metal layer 5 is tungsten silicide.
The third metal layer 5 with a thickness ofIn other embodiments, the thickness of the third metal layer 5
It can be configured according to actual needs.
Step 4: as shown in Figure 3B, carrying out being lithographically formed the first photoetching offset plate figure 6, the first photoresist figure for the first time
Shape 6 defines the forming region of the first electrode plate 5a of the MIP capacitor.
Step 5: being that mask carries out the to the third metal layer 5 with first photoetching offset plate figure 6 as shown in Figure 3 C
Primary etching forms the first electrode plate 5a.
Step 6: as shown in Figure 3D, removing first photoetching offset plate figure 6.
Step 7: as shown in FIGURE 3 E, being lithographically formed the second photoetching offset plate figure 7, the second photoresist figure for the second time
Shape 7 defines the forming region of the second electrode plate of the MIP capacitor, on vertical view face, the edge of the first electrode plate 5a
It is all located inside the forming region of the second electrode plate.
Second photoetching offset plate figure 7 defines the forming region of the gate structure of the MOS transistor simultaneously.
Step 8: being mask successively to the second insulating layer 4, institute with second photoetching offset plate figure 7 as illustrated in Figure 3 F
It states the first metal silicide 3 and the first polysilicon layer 2 performs etching, the MIP is formed by the second insulating layer 4 after etching
Dielectric layer 4a between the electrode of capacitor, by the first metal silicide 3a and the first polysilicon layer 2a superposition shape after etching
At the second electrode plate；Later, second photoetching offset plate figure 7 is removed.
The gate structure of the MOS transistor includes the gate dielectric layer and polysilicon gate being sequentially overlapped, the polycrystalline
Si-gate is made of first polysilicon layer 2 after etching.
The material of the gate dielectric layer includes oxide, nitrogen oxides or high dielectric constant material.The MOS transistor packet
Include LDMOS.
The embodiment of the present invention is sequentially forming the first polysilicon layer 2, second insulating layer 4 and third metal layer 5 and is using
After first photoetching offset plate figure 6 defines the forming region of first electrode plate 5a, finish to the etching of third metal layer 5 it
Afterwards, and in the prior art difference is then performed etching to second insulating layer 4 with the first photoetching offset plate figure 6, the embodiment of the present invention is adopted
With the first photoetching offset plate figure 6 of removal, the second photoresist figure for defining the forming region of second electrode plate is directly formed again later
Shape 7, and guarantee that the edge of first electrode plate 5a is all located inside the forming region of second electrode plate on vertical view face, later with the
Two photoetching offset plate figures 7, which are successively performed etching and are respectively formed between electrode to second insulating layer 4 and the first polysilicon layer 2 for mask, to be situated between
Matter layer and second electrode plate, since the edge of dielectric layer between electrode is located at the outside edges of first electrode plate 5a, therefore in the first electricity
Thickness of dielectric layers can be guaranteed well between the electrode plate of the edge of pole plate 5a, so the embodiment of the present invention can prevent first
Dielectric layer is thinning between the electrode plate of the edge of electrode plate 5a and the situation that punctures MIP capacitor in advance in edge occurs, energy
Make the stable breakdown voltage of MIP capacitor, improves product yield.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of MIP capacitor, which comprises the steps of:
Step 1: forming the first polysilicon layer in the semiconductor substrate for be formed with field oxide；The formation area of the MIP capacitor
Domain is located on the field oxide；
Step 2: forming second insulating layer；
Step 3: forming third metal layer on the second insulating layer surface；
Step 4: carrying out being lithographically formed the first photoetching offset plate figure for the first time, first photoetching offset plate figure defines the MIP electricity
The forming region of the first electrode plate of appearance；
Step 5: performing etching to form the first electrode to the third metal layer using first photoetching offset plate figure as mask
Plate；
Step 6: removal first photoetching offset plate figure；
Step 7: being lithographically formed the second photoetching offset plate figure for the second time, second photoetching offset plate figure defines the MIP electricity
The forming region of the second electrode plate of appearance, on vertical view face, the edge of the first electrode plate is all located at the second electrode plate
Forming region inside；
Step 8: using second photoetching offset plate figure as mask successively to the second insulating layer and first polysilicon layer into
Row etching, dielectric layer between the electrode of the MIP capacitor is made of the second insulating layer after etching, by described the after etching
One polysilicon layer forms the second electrode plate；Later, second photoetching offset plate figure is removed.
2. the manufacturing method of MIP capacitor as described in claim 1, it is characterised in that: the semiconductor substrate is silicon substrate.
3. the manufacturing method of MIP capacitor as claimed in claim 2, it is characterised in that: the field oxide using shallow trench every
Separating process is formed；Alternatively, the field oxide is formed using local field oxygen isolation technology.
4. the manufacturing method of MIP capacitor as described in claim 1, it is characterised in that: forming described more than first in step 1
Further include the steps that forming the first metal silicide on first polysilicon layer surface after crystal silicon layer.
5. the manufacturing method of MIP capacitor as claimed in claim 4, it is characterised in that: the material of first metal silicide
For tungsten silicide.
6. the manufacturing method of MIP capacitor as claimed in claim 5, it is characterised in that: the material of the third metal layer is silicon
Change tungsten.
7. the manufacturing method of MIP capacitor as claimed in claim 5, it is characterised in that: the thickness of first metal silicide
For
8. the manufacturing method of MIP capacitor as claimed in claim 6, it is characterised in that: the third metal layer with a thickness of
9. the manufacturing method of MIP capacitor as claimed in claim 2, it is characterised in that: the material of the second insulating layer is oxygen
Change layer.
10. the manufacturing method of MIP capacitor as claimed in claim 9, it is characterised in that: the second insulating layer with a thickness of
11. the manufacturing method of MIP capacitor as described in claim 1, it is characterised in that: the isolation of field oxide described in step 1
Active area out is formed with MOS transistor in the active area.
12. the manufacturing method of MIP capacitor as claimed in claim 11, it is characterised in that: second photoetching in step 7
Glue pattern defines the forming region of the gate structure of the MOS transistor simultaneously, and step 8 looks for that etching technics shape simultaneously
At the gate structure of the MOS transistor.
13. the manufacturing method of MIP capacitor as claimed in claim 12, it is characterised in that: the grid of the MOS transistor
Structure includes the gate dielectric layer and polysilicon gate being sequentially overlapped, and the polysilicon gate is by the first polysilicon layer group after etching
At.
14. the manufacturing method of MIP capacitor as claimed in claim 13, it is characterised in that: the material of the gate dielectric layer includes
Oxide, nitrogen oxides or high dielectric constant material.
15. the manufacturing method of MIP capacitor as claimed in claim 13, it is characterised in that: the MOS transistor includes LDMOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910679659.7A CN110491862A (en) | 2019-07-26 | 2019-07-26 | The manufacturing method of MIP capacitor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910679659.7A CN110491862A (en) | 2019-07-26 | 2019-07-26 | The manufacturing method of MIP capacitor |
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| CN110491862A true CN110491862A (en) | 2019-11-22 |
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| CN201910679659.7A Pending CN110491862A (en) | 2019-07-26 | 2019-07-26 | The manufacturing method of MIP capacitor |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701136A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Capacitor, semiconductor device and production method of capacitor |
| CN108417565A (en) * | 2018-02-05 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | The process of MIM capacitor |
| CN109638155A (en) * | 2018-12-10 | 2019-04-16 | 中国电子科技集团公司第二十四研究所 | Mim capacitor structure and preparation method thereof |
-
2019
- 2019-07-26 CN CN201910679659.7A patent/CN110491862A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701136A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Capacitor, semiconductor device and production method of capacitor |
| CN108417565A (en) * | 2018-02-05 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | The process of MIM capacitor |
| CN109638155A (en) * | 2018-12-10 | 2019-04-16 | 中国电子科技集团公司第二十四研究所 | Mim capacitor structure and preparation method thereof |
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Application publication date: 20191122 |
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