CN110489812A - Multilayer level netlist processing method, device, computer equipment and storage medium - Google Patents
Multilayer level netlist processing method, device, computer equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a kind of multilayer level netlist processing method, device, equipment and media.This method comprises: obtaining hardware circuit design, multilayer level netlist is generated based on the hardware circuit design；The multilayer level netlist is analyzed, generate corresponding module call relation tree, the module call relation tree includes upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation, and each upper layer hierarchy module includes at least one module instance object；According to the intermodule call relation, each module instance object is successively replaced with into lower layer's hierarchy module, and have the dummy node of module information in the insertion storage of the link position of lower layer's hierarchy module and upper layer hierarchy module, obtain target single layer netlist.It is designed this method solve current multilayer structure and carries out the problem of processing complexity of netlist present in netlist building process is high or netlist information is lost.
Description
Technical field
The present invention relates to eda software development technique field more particularly to a kind of multilayer level netlist processing method, device,
Computer equipment and storage medium.
Background technique
During hardware circuit design, to meet the reusability of design code and improving maintainability, generally require by
Certain specific functions are written as individually designing module and carry out instantiation operation to these design modules in other logics.Its
In, the hardware circuit that hardware circuit design generates is the important component of circuit system, and hardware circuit is designed by each section
The circuit of module composition, wherein design module includes but is not limited to voltage-stabilized power supply circuit, operation amplifier circuit, comparator electricity
Road, single-chip minimum system, H bridge motor-drive circuit, RC/LC filtering and field-effect tube/triode composition electronic switch etc..
For fairly large hardware circuit design, often define and using a large amount of design modules, these design modules
Between there is complicated call relation so that forming multilayered structure based on call relation between these design modules.In hardware electricity
In the design process of road, netlist building need to be carried out based on multi-layer structure design, so that the progress of netlist constructed by later use is subsequent
Operation.Currently there is following two ways to carry out netlist building multi-layer structure design: right one is hierarchical structure is fully retained
Each design module establishes independent netlist, and this mode can retain hierarchical structure, but will cause the more of same design module
Independence is lost between a module instance object, considerably increases the complexity for carrying out subsequent operation to constructed netlist.
Another kind is to be fully deployed all instantiations, constructs unique single layer netlist, this mode will lead to intermodule link information
(such as call relation) is lost, and may result in the netlist finally constructed can not be corresponding with user's design.Therefore, how reduced netlist
Processing complexity simultaneously guarantees that netlist information integrity is urgent problem to be solved during current multilayer structure design construction netlist.
Summary of the invention
The embodiment of the present invention provides a kind of multilayer level netlist processing method, device, computer equipment and storage medium, with
It solves current multilayer structure and designs what netlist processing complexity height or netlist information present in progress netlist building process were lost
Problem.
A kind of multilayer level netlist processing method, comprising:
Hardware circuit design is obtained, multilayer level netlist is generated based on the hardware circuit design；
The multilayer level netlist is analyzed, corresponding module call relation tree, the module call relation are generated
Tree includes upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation, and each upper layer hierarchy module includes at least
One module instance object；
According to the intermodule call relation, each module instance object is successively replaced with into lower layer's level mould
Block has the dummy node of module information in the insertion storage of the link position of lower layer's hierarchy module and upper layer hierarchy module, obtains mesh
Mark single layer netlist.
A kind of multilayer level netlist processing unit, comprising:
Multilayer level netlist generation module is generated more for obtaining hardware circuit design based on the hardware circuit design
Grade netlist layer by layer；
Module call relation tree generation module generates corresponding module for analyzing the multilayer level netlist
Call relation tree, the module call relation tree include upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation, often
The one upper layer hierarchy module includes at least one module instance object；
Target single layer netlist obtains module, is used for according to the intermodule call relation, successively that each module is real
Exampleization object replaces with lower layer's hierarchy module, has mould in the insertion storage of the link position of lower layer's hierarchy module and upper layer hierarchy module
The dummy node of block message obtains target single layer netlist.
A kind of computer equipment, including memory, processor and storage are in the memory and can be in the processing
The computer program run on device, the processor realize above-mentioned multilayer level netlist processing side when executing the computer program
The step of method.
A kind of computer readable storage medium, the computer-readable recording medium storage have computer program, the meter
Calculation machine program realizes the step of above-mentioned multilayer level netlist processing method when being executed by processor.
Above-mentioned multilayer level netlist processing method, device, computer equipment and storage medium obtain hardware circuit design,
Multilayer level netlist is generated based on the hardware circuit design, the multilayer level netlist is analyzed, corresponding mould is generated
Block call relation tree, the module call relation tree include upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation,
Each upper layer hierarchy module includes at least one module instance object, so as to subsequent according to the module call relation tree pair
Multilayer level netlist is handled, to reduce difficulty when user operates multilayer hierarchy module.According to the intermodule
Each module instance object is successively replaced with lower layer's hierarchy module by call relation, to eliminate the same upper layer level
The strong logical relation of multiple module instance objects of module, so as to subsequent lower layer's level mould to the same upper layer hierarchy module
When block is called, different processing logics can be used and do not interfere with each other, reduce operation difficulty, accelerates working efficiency.Under
The insertion storage of the link position of layer hierarchy module and upper layer hierarchy module has the dummy node of module information, obtains target monolayer net
Table avoids after replacing under the device and other of lower layer's hierarchy module so that upper layer hierarchy module and lower layer's hierarchy module is isolated
Layer hierarchy module is obscured.Since each dummy node in target single layer netlist is stored with corresponding module information, Ke Yiyou
Effect guarantees the integrality of netlist information, and avoiding netlist from being unfolded in treatment process, there are module information loss.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below by institute in the description to the embodiment of the present invention
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without any creative labor, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a flow chart of multilayer level netlist processing method in one embodiment of the invention；
Fig. 2 is another flow chart of multilayer level netlist processing method in one embodiment of the invention；
Fig. 3 is another flow chart of multilayer level netlist processing method in one embodiment of the invention；
Fig. 4 is another flow chart of multilayer level netlist processing method in one embodiment of the invention；
Fig. 5 is a schematic diagram of multilayer level netlist processing unit in one embodiment of the invention；
Fig. 6 is a schematic diagram of computer equipment in one embodiment of the invention；
Fig. 7 is a schematic diagram for module call relation tree in one embodiment of the invention；
Fig. 8 is insertion one schematic diagram of dummy node in one embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of multilayer level netlist processing method, which applies
In multilayer level netlist processing system (hereinafter referred to as " system "), according to module call relation tree by the mould of upper layer hierarchy module
Block instance object replaces with complete lower layer's hierarchy module, and multilayer level netlist is expanded into target single layer netlist to realize,
Target single layer netlist is operated convenient for subsequent, and is deposited in lower layer's hierarchy module and the link position insertion of upper layer hierarchy module
It is placed with the dummy node of module information, upper layer hierarchy module and lower layer's hierarchy module is isolated, to ensure that eda software is stable
Property, simplify operation logic, effectively improves the operational efficiency of eda software；It, can be effective since dummy node storage has module information
Avoid the problem that expanding into multilayer level netlist into target single layer netlist process that there are netlist information loss, to guarantee netlist information
Integrality.
In one embodiment, as shown in Figure 1, the present embodiment provides a kind of multilayer level netlist processing method, including multilayer
The following steps that level netlist processing system executes:
S101: obtaining hardware circuit design, generates multilayer level netlist based on the hardware circuit design.
Wherein, hardware circuit design refers to the circuit design of the hardware circuit for the achievable specific function that system receives.
Hardware circuit by the circuit that forms of each section design module, the design module include but is not limited to regulated power supply design module,
Design of Amplifiers module, comparator design module, single-chip minimum system module, H bridge motor driven design module, RC/
LC filter module and field-effect tube/triode composition electronic switch module etc..In electric design automation, netlist
(netlist), i.e. connection table refers to the logic gate on basis and describes the describing mode of data circuit connection.Netlist is used
Aspect information is connected in transfer circuit, netlist generally includes module instance, intermodule calling, gauze and association attributes, if netlist
It needs comprising more hardware informations, it will usually use hardware description language.Multilayer level netlist is for reflecting comprising multilayer
The corresponding netlist of design module of structure.
Specifically, system converts corresponding multilayer level net for hardware circuit design automatically using automation tools reading
Table accelerates the speed for generating multilayer level netlist to reduce the fussy degree for handling ultra-large hardware circuit design.At this
In embodiment, automation tools refer to synthesis tool gwSyn resolver.
S102: analyzing the multilayer level netlist, generates corresponding module call relation tree, and the module is called
Relational tree includes upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation, and each upper layer hierarchy module includes
At least one module instance object.
Wherein, module call relation tree refers to the call relation between each design module formed according to multilayer level netlist
Dendrogram.It include the corresponding top layer hierarchy module of root node, the corresponding intermediate level of intermediate node on module call relation tree
The bottom hierarchy module of module and leaf node.The bottom hierarchy module refers to the minimum module that can complete specific function.Its
In, root node is that there was only child node and the node without father node on module call relation tree；Leaf node is module call relation
There was only father node and the node without child node on tree；Intermediate node is that the upper existing child node of module call relation tree has father node again
Node.
In the present embodiment, server determines there is the upper layer level mould for the relationship that calls directly according to intermodule call relation
Block and lower layer's hierarchy module.There is the upper layer hierarchy module and lower layer's level of the relationship that calls directly generally, for any group
For module, lower layer's hierarchy module is the module instance object of upper layer hierarchy module.For example, for there are the moulds of three-decker
For block call relation, first layer is top layer hierarchy module, and the second layer is intermediate level module, and third layer is bottom level mould
Block then exists between first layer and the second layer and calls directly relationship, at this point, top layer hierarchy module is upper layer hierarchy module, it is intermediate
Hierarchy module is lower layer's hierarchy module；Exist between the second layer and third layer and call directly relationship, at this point, intermediate level module is
Upper layer hierarchy module, bottom hierarchy module are lower layer's hierarchy module.It is to be appreciated that upper layer hierarchy module herein and under layer by layer
Grade module is oppositely arranged, and is determined according to its intermodule call relation.
For example, it is assumed that user's original design pseudocode is as follows:
The module of original design pseudo code definition three-decker is called, and first layer is top layer hierarchy module, i.e.,
module top；The second layer is intermediate level module, i.e. module a and module b；Third layer is bottom hierarchy module, i.e. module c；
Then exist between first layer and the second layer and call directly relationship, at this point, module top is upper layer hierarchy module, module a and mould
Block b is lower layer's hierarchy module；Exist between the second layer and third layer and call directly relationship, at this point, module a and module b is upper layer
Hierarchy module, module c are lower layer's hierarchy module.
It is analyzed according to above-mentioned original design pseudocode, the module call relation tree of acquisition is as shown in Figure 7.It was analyzed
Journey is specific as follows: firstly, the top layer hierarchy module of the multilayer level netlist is obtained, for example, can according to the multilayer level netlist
To obtain top layer hierarchy module according to the keyword module top of module definition in the multilayer level netlist, or can root
The top layer hierarchy module in multilayer level netlist is determined according to the root node in hardware circuit design.Then, according to the top layer layer
Grade module obtains the different levels module in multilayer level netlist from the downward bed-by-bed analysis multilayer level netlist of top layer hierarchy module
Relationship multilayer level netlist is handled so as to subsequent with generating the corresponding module call relation tree of multilayer level netlist.
In general, the corresponding module call relation tree of a multilayer level netlist, any of module call relation tree lower layer
Hierarchy module can be called by least one upper layer hierarchy module simultaneously, and such as above-mentioned module c can be simultaneously by module a and module
B is called.
S103: according to the intermodule call relation, successively each module instance object is replaced with down layer by layer
Grade module has the dummy node of module information in the insertion storage of the link position of lower layer's hierarchy module and upper layer hierarchy module, obtains
Take target single layer netlist.
Wherein, dummy node refers to the node for upper layer hierarchy module and lower layer's hierarchy module to be isolated, and dummy node is not
Attended Operation.In the present embodiment, deposited on the dummy node of the link position of lower layer's hierarchy module and upper layer hierarchy module insertion
It is placed with module information, which is that multilayer level netlist needs to save during expansion the information to avoid loss, will
Module information is stored in dummy node, helps to ensure that the netlist that multilayer level netlist expands into during target single layer netlist
The integrality of information.
Target single layer netlist refers to that the module instance object to multilayer level netlist hierarchy module at the middle and upper levels is replaced
Multilayer level netlist is converted target single layer netlist by netlist afterwards, can simplify the complexity of subsequent operation, accelerates work effect
Rate.
Since in multilayer level netlist, same lower layer's hierarchy module may be instantiated repeatedly, and be instantiated every time
It is not directly dependent upon between calling, if not to the processing of multilayer level netlist, subsequent when being operated to multilayer level netlist, operation
Difficulty is big, and working efficiency is lower.In the present embodiment, according to intermodule call relation, layer by layer by the bottom of module call relation tree
Grade module is determined as first lower layer's hierarchy module analyzed, and successively finds example upwards from lower layer's hierarchy module
Change the upper layer hierarchy module of lower layer's hierarchy module, successively replaces with down the corresponding module instance object of upper layer hierarchy module
Layer hierarchy module, and be stored with module information in the link position insertion of lower layer's hierarchy module and upper layer hierarchy module and virtually save
Point generates target single layer netlist.In the present embodiment, dummy node both plays the upper layer level mould that isolation has the relationship that calls directly
The effect of block and lower layer's hierarchy module, and the module information that may lose during netlist expansion, the shape to guarantee can be stored in
At target single layer netlist in netlist information integrality, can effectively avoid and multilayer level netlist is expanded into target single layer netlist
There is netlist information loss in process.
For example, the module of original design pseudo code definition in step S102 three-decker is called, as shown in fig. 7, the
One layer is top layer hierarchy module, i.e. module top；The second layer is intermediate level module, i.e. module a and module b；Third layer is
Bottom hierarchy module, i.e. module c successively find upwards then with module c for first lower layer's hierarchy module and instantiate the lower layer
The upper layer hierarchy module of hierarchy module, can find module a and module b, be inserted into virtual section in the link position of module c and module a
Point is inserted into dummy node in the link position of module c and module b；Similarly, in the link position of module a and module top
It is inserted into dummy node, dummy node is inserted into the link position of module b and module module top, to be formed as shown in Figure 8
Target single layer netlist is virtually being saved with realizing using the purpose of dummy node isolation upper layer hierarchy module and lower layer's hierarchy module
Storage module information in point, it is ensured that the integrality of information during netlist expansion.
It is to be appreciated that hierarchy module corresponding module instance object in upper layer is replaced with into lower layer's hierarchy module, so that
Replaced lower layer's hierarchy module has independence, patrolling by force between multiple module instance objects to eliminate same module
The relationship of collecting, so that different disposal logic can be used in subsequent lower layer's hierarchy module to same upper layer hierarchy module and does not do mutually
It disturbs, reduces the subsequent difficulty operated to netlist, improve working efficiency；In the company of lower layer's hierarchy module and upper layer hierarchy module
It connects position insertion dummy node and avoids the device of disparate modules from obscuring so that upper layer hierarchy module and lower layer's hierarchy module is isolated.
In multilayer level netlist processing method provided by the present embodiment, hardware circuit design is obtained, is based on the hardware
Circuit design generates multilayer level netlist, analyzes the multilayer level netlist, generates corresponding module call relation tree,
The module call relation tree includes upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation, each upper layer
Hierarchy module includes at least one module instance object, subsequent to be carried out according to the module call relation tree to multilayer level netlist
Processing, to reduce difficulty when user operates multilayer hierarchy module.It, successively will be every according to the intermodule call relation
The one module instance object replaces with lower layer's hierarchy module, to eliminate multiple module instances of the same upper layer hierarchy module
The strong logical relation for changing object can be with when being called so as to subsequent lower layer's hierarchy module to the same upper layer hierarchy module
It is not interfere with each other using different processing logics, reduces operation difficulty, accelerate working efficiency.Lower layer's hierarchy module and it is upper layer by layer
The link position of grade module is inserted into dummy node, target single layer netlist is obtained, so that upper layer hierarchy module and lower layer's level is isolated
Module avoids the device of the device and other lower layer's hierarchy modules of lower layer's hierarchy module after replacing from obscuring.Due to target single layer
Each dummy node in netlist is stored with corresponding module information, and the integrality of netlist information can be effectively ensured, avoid
There are module information loss in netlist expansion treatment process.
In one embodiment, step S102 is inserted into empty in the link position of lower layer's hierarchy module and upper layer hierarchy module
Quasi- node, comprising: dummy node is inserted into using container technique in the link position of lower layer's hierarchy module and upper layer hierarchy module, and
The corresponding module information of lower layer's hierarchy module is stored in the dummy node.
Wherein, container technique is a kind of virtualization technology, and virtualization technology is such as to take the various actual resources of computer
Business device, network, memory and storage etc., are abstracted and are showed after converting, break the not cleavable barrier between actual resource
Hinder, allows user than the configuration better way of script to apply these resources.In the present embodiment, module information refers to lower layer
Information in the corresponding module instance object of hierarchy module, the module information include but is not limited to port information, attribute letter
Breath and constraint information.
It is virtual using container technique insertion in the link position of lower layer's hierarchy module and upper layer hierarchy module in the present embodiment
Node, to realize the corresponding inside modules device of isolation upper layer hierarchy module and the corresponding inside modules device of lower layer's hierarchy module
Part.I.e. in the primary instantiation replacement operation of every progress, the corresponding inside modules device of hierarchy module and lower layer's level on upper layer
The link position of the corresponding inside modules device of module is inserted into the dummy node of a specific type, which can belong to
For an inside modules device in lower layer's hierarchy module, but it is not involved in any operation, only in insertion as container storage
Essential information, port information, attribute information and the constraint information of link position where lower layer's hierarchy module.Lower layer's hierarchy module
Corresponding inside modules device refers to the specific function for realizing lower layer's hierarchy module used in hardware circuit design
Device.The corresponding inside modules device of upper layer hierarchy module refer to used in hardware circuit design for realizing upper layer level
The device of the specific function of module.
Specifically, system can be with quick obtaining module instance object, to module instance by module call relation tree
After change object replaces with corresponding lower layer's hierarchy module, since module instance object is replaced with lower layer's hierarchy module, in order to
The module information for the device for avoiding replaced lower layer's hierarchy module from connecting with upper layer hierarchy module is lost or is capped, and causes
There is mistake in the netlist of generation, inconsistent with user's design, therefore, in the connection position of lower layer's hierarchy module and upper layer hierarchy module
It sets and dummy node is inserted into using container technique, the inside modules device of upper layer hierarchy module and the mould of lower layer's hierarchy module is isolated
Block internal components, to can avoid avoiding the device of disparate modules to obscure, while by the corresponding module information of lower layer's hierarchy module
It is stored in the dummy node, it is ensured that module information is complete, and module information is avoided to lose.
In one embodiment, as shown in Fig. 2, step S101, obtains hardware circuit design, it is based on the hardware circuit design
Generate multilayer level netlist, comprising:
S201: reading the RLT file of the hardware circuit design using reading tool, according to RLT file foundation pair
The RLT structure tree answered.
Wherein, RLT (Register Transfer Level) file, refers to register transfer level circuit file, passes through description
Logic function between register and register describes the HDL level of circuit, is a kind of high-level abstractions hierarchical file.Reading tool
Refer to the tool for reading RLT file in hardware circuit design, which is a kind of automation synthesis tool, using reading work
Tool, which reads RLT file, can reduce the workload of user, accelerate working efficiency.RLT structure tree refers in RLT file between register
Connection relationship dendrogram, the RLT structure tree be specifically using top layer hierarchy module as root node, using other hierarchy modules as leaf
The dendrogram of node.
Specifically, the RLT file of the hardware circuit design is read using reading tool, quickly from the code of RLT file
In find top layer hierarchy module, and using the top layer hierarchy module as the root node of RLT structure tree, according to the generation in RLT file
The hierarchical structure of code establishes RLT structure tree corresponding with the RLT code, to be subsequently generated multilayer level netlist.
S202: converting the RLT structure tree, generates corresponding multilayer level netlist.
Specifically, according to the RLT structure tree, RLT code is detected with the presence or absence of mistake by compiler and is checked just
Logic function is walked, then, RLT file conversion is integrated according to the RLT structure tree using synthesis tool, with conversion
For multilayer level netlist, multilayer level netlist is handled so as to subsequent.
In multilayer level netlist processing method provided by the present embodiment, the hardware circuit is read using reading tool and is set
RTL file is read in the RLT file of meter, automation, simplifies the step of reading RTL, accelerates working efficiency, according to the RLT file
Corresponding RLT structure tree is established, the RLT structure tree is converted, corresponding multilayer level netlist is generated, so as to subsequent right
Multilayer level netlist is handled, to reduce the difficulty that user operates netlist.
In one embodiment, it as shown in figure 3, step S102, i.e., analyze the multilayer level netlist, generates and corresponds to
Module call relation tree, comprising:
S301: the root node based on the RLT structure tree obtains the corresponding top layer level mould of the multilayer level netlist
Block.
Specifically, the RLT file that the hardware circuit design is read using reading tool, is looked for from the code of RLT file
To register top-level module, and using the register top-level module as root node, since multilayer level netlist is turned from RLT file
Generation is changed, then the structure of multilayer level netlist is corresponding with the structure of RLT structure tree, therefore, based on RLT structure tree
Root node, the corresponding top layer hierarchy module of multilayer level netlist described in quick obtaining.
S302: the corresponding intermediate node of root node and leaf of the RLT structure tree are traversed using depth-first traversal algorithm
Child node, obtains intermediate level module and bottom hierarchy module respectively, and call relation between determining module generates the multilayer level
The corresponding module call relation tree of netlist.
Wherein, the level that depth-first traversal algorithm is similar to binary tree traverses, and is according to priority traversed from high to low
Code, depth-first traversal algorithm are to traverse the RLT structure tree using the root node of RLT structure tree as top layer hierarchy module
Intermediate node, leaf node is then determined according to the intermediate node, with call relation between determining module, using depth-first
Ergodic algorithm is with call relation between quick determining module.Intermediate node refers to that the existing father node in RLT structure tree has sub- section again
The node of point, leaf node refers to the endpoint node of RLT structure tree, is that only father node does not have the node of child node.Leaf section
Bottom hierarchy module in the corresponding multilayer level netlist of point.Intermediate level module pair in intermediate node and multilayer level netlist
It answers, the different levels module corresponding to multilayer level netlist.
Specifically, after getting the corresponding top layer hierarchy module of multilayer level netlist, using depth-first traversal algorithm
The multilayer level netlist is analyzed, depth-first traversal specifically is carried out to RLT structure tree, with determining and RLT structure
The corresponding intermediate node of the root node of tree and leaf node, to obtain intermediate level module and bottom hierarchy module, i.e., it is described in
Intermediate node corresponds to intermediate level module, and leaf node corresponds to bottom hierarchy module, thus according to depth-first traversal algorithm time
RLT structure tree is gone through, with call relation between accurate determining module, generates the corresponding module call relation of the multilayer level netlist
Tree, so as to subsequent according to the module call relation tree, being by multilayer level netlist rapid deployment can reduced netlist processing complexity
Spend and guarantee the target single layer netlist of netlist information integrity.
In multilayer level netlist processing method provided by the present embodiment, based on the root node of the RLT structure tree, obtain
Then the corresponding top layer hierarchy module of the multilayer level netlist traverses the RLT structure tree using depth-first traversal algorithm
The corresponding intermediate node of root node and leaf node, it is accurate respectively to obtain intermediate level module and bottom hierarchy module, with standard
Call relation between true determining module, generates the corresponding module call relation tree of the multilayer level netlist, so as to subsequent according to institute
State module call relation tree, by multilayer level netlist rapid deployment be can reduced netlist handle and complexity and guarantee that netlist information is complete
The target single layer netlist of whole property.
In one embodiment, the intermodule call relation includes calling serial number, as shown in figure 4, step S103, i.e., described
According to the intermodule call relation, each module instance object is successively replaced with into lower layer's hierarchy module, comprising:
S401: being ranked up the corresponding calling serial number of intermodule call relation in the multilayered structure netlist, obtains
Calling sequence.
Wherein, it calls serial number to refer to each hierarchy module corresponding serial number when intermodule calls, specifically can be understood as pushing up
The sequencing called between layer hierarchy module, intermediate level module and bottom hierarchy module.The calling sequence of same level module
It is number identical, as long as guaranteeing the complete of each hierarchy module in module call relation tree, same level module is not emphasized
Call sequencing.For example, as shown in figure 8, first layer is top layer hierarchy module, that is, module in intermodule call relation tree
top；The second layer is intermediate level module, that is, module a and module b, and third layer is bottom hierarchy module, that is, module c, then module
The calling serial number 010 of the calling serial number 001 of top, module a and module b, the calling serial number 011 of module c.Further,
The calling serial number can successively progressively increase, until bottom hierarchy module；Or call serial number that can successively successively decrease, until bottom layer
Grade module, it is not limited here.The corresponding calling serial number of top layer hierarchy module does not need mould to be carried out in module call relation tree
The replacement of block instance object；It is real that the corresponding calling serial number of module call relation tree indsole layer hierarchy module does not need module to be carried out
The replacement of exampleization object.
Specifically, it is ranked up according to the corresponding calling serial number of intermodule call relation in the multilayered structure netlist,
The calling sequence of intermodule is obtained, module instance object is replaced according to the calling sequence so as to subsequent.For example, right
Serial number is called to be ranked up and can be ranked up according to positive sequence sequence, it can also be according to descending order to calling serial number to be ranked up
It is ranked up.
S402: based on the calling sequence, each module instance object is successively replaced with into lower layer's hierarchy module.
Specifically, according to by the calling sequence after arriving first, each module instance object is successively replaced with into lower layer
Hierarchy module is from bottom to top successively replaced module instance object from intermodule call relation tree, realize multilayer
Level netlist expands into target single layer netlist, to lower the subsequent difficulty operated to target single layer netlist.
In multilayer level netlist processing method provided by the present embodiment, to the intermodule tune in the multilayered structure netlist
Be ranked up with the corresponding calling serial number of relationship, obtain calling sequence, according to calling sequence by the sequence after arriving first successively
Each module instance object is replaced with into lower layer's hierarchy module, realizes and multilayer level netlist is expanded into target single layer
Netlist, to lower the subsequent difficulty operated to target single layer netlist.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
In one embodiment, a kind of multilayer level netlist processing unit is provided, the multilayer level netlist processing unit with it is upper
Multilayer level netlist processing method in embodiment is stated to correspond.As shown in figure 5, the multilayer level netlist processing unit includes more
Grade netlist generation module 501, module call relation tree generation module 502 and target single layer netlist obtain module 503 layer by layer.Respectively
Detailed description are as follows for functional module:
Multilayer level netlist generation module 501 is generated for obtaining hardware circuit design based on the hardware circuit design
Multilayer level netlist.
Module call relation tree generation module 502 generates corresponding mould for analyzing the multilayer level netlist
Block call relation tree, the module call relation tree include upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation,
Each upper layer hierarchy module includes at least one module instance object.
Target single layer netlist obtains module 503, is used for according to the intermodule call relation, successively by each module
Instance object replaces with lower layer's hierarchy module, and virtual in the insertion of the link position of lower layer's hierarchy module and upper layer hierarchy module
Node obtains target single layer netlist.
Preferably, target single layer netlist obtains module 503, comprising: dummy node is inserted into unit.
Dummy node is inserted into unit, uses container skill for the link position in lower layer's hierarchy module and upper layer hierarchy module
Art is inserted into dummy node, and the corresponding module information of lower layer's hierarchy module is stored in the dummy node.
Preferably, multilayer level netlist generation module 501, comprising: RLT structure tree establishes unit and the conversion of RLT structure tree
Unit.
RLT structure tree establishes unit, for reading the RLT file of the hardware circuit design using reading tool, according to
The RLT file establishes corresponding RLT structure tree.
RLT structure tree converting unit converts the RLT structure tree for unit, generates corresponding multilayer level
Netlist.
Preferably, module call relation tree generation module 502, comprising: top layer hierarchy module acquiring unit and intermodule tune
Use relation determination unit.
Top layer hierarchy module acquiring unit obtains the multilayer level net for the root node based on the RLT structure tree
The corresponding top layer hierarchy module of table.
Intermodule call relation determination unit, for traversing the root of the RLT structure tree using depth-first traversal algorithm
The corresponding intermediate node of node and leaf node obtain intermediate level module and bottom hierarchy module respectively, adjust between determining module
With relationship, the corresponding module call relation tree of the multilayer level netlist is generated.
Preferably, the intermodule call relation includes calling serial number, which is characterized in that target single layer netlist obtains module
503, comprising: calling sequence acquiring unit and replacement unit
Calling sequence acquiring unit, for the corresponding calling sequence of intermodule call relation in the multilayered structure netlist
It number is ranked up, obtains calling sequence.
Replacement unit, for each module instance object successively to be replaced with lower layer based on the calling sequence
Hierarchy module.
Specific restriction about multilayer level netlist processing unit may refer to above for the processing of multilayer level netlist
The restriction of method, details are not described herein.Modules in above-mentioned multilayer level netlist processing unit can be fully or partially through
Software, hardware and combinations thereof are realized.Above-mentioned each module can be embedded in the form of hardware or independently of the place in computer equipment
It manages in device, can also be stored in a software form in the memory in computer equipment, in order to which processor calls execution or more
The corresponding operation of modules.
In one embodiment, which can be stand-alone device, it can be internal structure
Computer equipment as shown in FIG. 6, the computer equipment include that the processor, memory, network connected by system bus connects
Mouth and database.Wherein, the processor of the computer equipment is for providing calculating and control ability.The storage of the computer equipment
Device includes non-volatile memory medium, built-in storage.The non-volatile memory medium be stored with operating system, computer program and
Database.The built-in storage provides environment for the operation of operating system and computer program in non-volatile memory medium.It should
The database of computer equipment, which is used to store, executes the number that above-mentioned multilayer level netlist processing method is used or generated in the process
According to such as target single layer netlist.The network interface of the computer equipment is used to communicate with external terminal by network connection.The meter
To realize a kind of multilayer level netlist processing method when calculation machine program is executed by processor.
In one embodiment, which may include client terminal and passes through net with client terminal
The connected server of network communication, which can be computer equipment as shown in FIG. 6.Wherein, client terminal is also known as used
Family end, refers to corresponding with server, provides the program of local service for client.Client it is mountable but be not limited to various
On people's computer and laptop.
In one embodiment, a kind of computer equipment is provided, including memory, processor and storage are on a memory
And the computer program that can be run on a processor, processor realize multilayer level in above-described embodiment when executing computer program
Netlist processing method, such as step shown in step S101-S103 or Fig. 2 to Fig. 4 shown in FIG. 1, to avoid repeating,
Which is not described herein again.Alternatively, each in this embodiment of multilayer level netlist processing method when processor executes computer program
Module/unit function, such as multilayer level netlist generation module 501 shown in fig. 5, module call relation tree generation module
502 and target single layer netlist obtain module 503 function, to avoid repeating, which is not described herein again.
In one embodiment, a computer readable storage medium is provided, meter is stored on the computer readable storage medium
Calculation machine program, the computer program realize multilayer level netlist processing method in above-described embodiment when being executed by processor, such as
Step shown in step S101-S103 or Fig. 2 to Fig. 4 shown in FIG. 1, to avoid repeating, which is not described herein again.Alternatively,
The function of each module/unit when processor executes computer program in this embodiment of multilayer level netlist processing method, example
Multilayer level netlist generation module 501, module call relation tree generation module 502 and target single layer netlist as shown in Figure 5 obtains
The function of modulus block 503, to avoid repeating, which is not described herein again.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, it is readable which can be stored in a non-volatile computer
It takes in storage medium, the computer program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, this Shen
Please provided by any reference used in each embodiment to memory, storage, database or other media, may each comprise
Non-volatile and/or volatile memory.Nonvolatile memory may include read-only memory (ROM), programming ROM
(PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM) or flash memory.Volatile memory may include
Random access memory (RAM) or external cache.By way of illustration and not limitation, RAM is available in many forms,
Such as static state RAM (SRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate sdram (DDRSDRAM), enhancing
Type SDRAM (ESDRAM), synchronization link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM
(RDRAM), direct memory bus dynamic ram (DRDRAM) and memory bus dynamic ram (RDRAM) etc..
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of device are divided into different functional unit or module, to complete above description
All or part of function.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of multilayer level netlist processing method characterized by comprising
Hardware circuit design is obtained, multilayer level netlist is generated based on the hardware circuit design；
The multilayer level netlist is analyzed, corresponding module call relation tree, the module call relation tree packet are generated
Upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation are included, each upper layer hierarchy module includes at least one
Module instance object；
According to the intermodule call relation, each module instance object is successively replaced with into lower layer's hierarchy module, In
The insertion storage of the link position of lower layer's hierarchy module and upper layer hierarchy module has the dummy node of module information, obtains target single layer
Netlist.
2. multilayer level netlist processing method as described in claim 1, which is characterized in that it is described lower layer's hierarchy module with it is upper
The link position insertion storage of layer hierarchy module has the dummy node of module information, comprising:
Dummy node is inserted into using container technique in the link position of lower layer's hierarchy module and upper layer hierarchy module, and will be described under
The corresponding module information of layer hierarchy module is stored in the dummy node.
3. multilayer level netlist processing method as described in claim 1, which is characterized in that the acquisition hardware circuit design,
Multilayer level netlist is generated based on the hardware circuit design, comprising:
The RLT file that the hardware circuit design is read using reading tool is established corresponding RLT according to the RLT file and tied
Paper mulberry；
The RLT structure tree is converted, corresponding multilayer level netlist is generated.
4. multilayer level netlist processing method as described in claim 1, which is characterized in that described to the multilayer level netlist
It is analyzed, generates corresponding module call relation tree, comprising:
Based on the root node of the RLT structure tree, the corresponding top layer hierarchy module of the multilayer level netlist is obtained；
The corresponding intermediate node of root node and leaf node of the RLT structure tree are traversed using depth-first traversal algorithm, point
Not Huo Qu intermediate level module and bottom hierarchy module, it is corresponding to generate the multilayer level netlist call relation between determining module
Module call relation tree.
5. multilayer level netlist processing method as described in claim 1, the intermodule call relation includes calling serial number,
It is characterized in that, it is described according to the intermodule call relation, successively each module instance object is replaced with down layer by layer
Grade module, comprising:
The corresponding calling serial number of intermodule call relation in the multilayered structure netlist is ranked up, calling sequence is obtained；
Based on the calling sequence, each module instance object is successively replaced with into lower layer's hierarchy module.
6. a kind of multilayer level netlist processing unit, which is characterized in that including
Multilayer level netlist generation module generates multilayer layer based on the hardware circuit design for obtaining hardware circuit design
Grade netlist；
Module call relation tree generation module generates corresponding module and calls for analyzing the multilayer level netlist
Relational tree, the module call relation tree include upper layer hierarchy module, lower layer's hierarchy module and intermodule call relation, Mei Yisuo
Stating upper layer hierarchy module includes at least one module instance object；
Target single layer netlist obtains module, is used for according to the intermodule call relation, successively by each module instance
Object replaces with lower layer's hierarchy module, has module letter in the insertion storage of the link position of lower layer's hierarchy module and upper layer hierarchy module
The dummy node of breath obtains target single layer netlist.
7. multilayer level netlist processing unit as claimed in claim 6, which is characterized in that target single layer netlist obtains module,
Include:
Dummy node is inserted into unit, is inserted for the link position in lower layer's hierarchy module and upper layer hierarchy module using container technique
Enter dummy node, the corresponding module information of lower layer's hierarchy module is stored in the dummy node.
8. multilayer level netlist processing unit as claimed in claim 6, which is characterized in that multilayer level netlist generation module,
Include:
RLT structure tree establishes unit, for reading the RLT file of the hardware circuit design using reading tool, according to described
RLT file establishes corresponding RLT structure tree；
RLT structure tree converting unit converts the RLT structure tree for unit, generates corresponding multilayer level netlist.
9. a kind of computer equipment, including memory, processor and storage are in the memory and can be in the processor
The computer program of upper operation, which is characterized in that the processor realized when executing the computer program as claim 1 to
The step of any one of 5 multilayer level netlist processing method.
10. a kind of computer readable storage medium, the computer-readable recording medium storage has computer program, and feature exists
In realization multilayer level netlist processing side as described in any one of claim 1 to 5 when the computer program is executed by processor
The step of method.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111079362A (en) * | 2019-12-18 | 2020-04-28 | 京微齐力(北京)科技有限公司 | Parallel comprehensive algorithm utilizing hierarchical information |
| CN111580912A (en) * | 2020-05-09 | 2020-08-25 | 北京飞讯数码科技有限公司 | Display method and storage medium for multi-level structure resource group |
| CN112464591A (en) * | 2020-11-19 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Multi-port nested model connection analysis method and medium |
| CN113032401A (en) * | 2021-03-31 | 2021-06-25 | 合安科技技术有限公司 | Big data processing method and device based on special-shaped structure tree and related equipment |
| CN113255262A (en) * | 2021-06-07 | 2021-08-13 | 上海国微思尔芯技术股份有限公司 | Object allocation method and device, computer equipment and storage medium |
| CN117217147A (en) * | 2023-09-21 | 2023-12-12 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and medium for FPGA |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101833590A (en) * | 2009-03-11 | 2010-09-15 | 新思科技有限公司 | Method and apparatus for generating a floorplan using a reduced netlist |
| CN103678745A (en) * | 2012-09-18 | 2014-03-26 | 中国科学院微电子研究所 | Cross-platform multilevel integrated design system for FPGA (field programmable gate array) |
| US9984195B1 (en) * | 2010-06-11 | 2018-05-29 | Worldwide Pro Ltd. | Hierarchical visualization-based analysis of integrated circuits |
| CN108924215A (en) * | 2018-06-28 | 2018-11-30 | 北京顺丰同城科技有限公司 | A kind of service discovery processing method and processing device based on tree structure |
| US20180365359A1 (en) * | 2017-06-14 | 2018-12-20 | Excellicon Corporation | Method to automatically generate and promote timing constraints in a synopsys design constraint format |
| CN109388875A (en) * | 2018-09-05 | 2019-02-26 | 重庆创速工业有限公司 | A kind of design implementation method of elastic element module |
| CN110046394A (en) * | 2019-03-20 | 2019-07-23 | 广东高云半导体科技股份有限公司 | Integrated circuit netlist generation method, device, computer equipment and storage medium |
-
2019
- 2019-07-25 CN CN201910677435.2A patent/CN110489812B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101833590A (en) * | 2009-03-11 | 2010-09-15 | 新思科技有限公司 | Method and apparatus for generating a floorplan using a reduced netlist |
| US9984195B1 (en) * | 2010-06-11 | 2018-05-29 | Worldwide Pro Ltd. | Hierarchical visualization-based analysis of integrated circuits |
| CN103678745A (en) * | 2012-09-18 | 2014-03-26 | 中国科学院微电子研究所 | Cross-platform multilevel integrated design system for FPGA (field programmable gate array) |
| US20180365359A1 (en) * | 2017-06-14 | 2018-12-20 | Excellicon Corporation | Method to automatically generate and promote timing constraints in a synopsys design constraint format |
| CN108924215A (en) * | 2018-06-28 | 2018-11-30 | 北京顺丰同城科技有限公司 | A kind of service discovery processing method and processing device based on tree structure |
| CN109388875A (en) * | 2018-09-05 | 2019-02-26 | 重庆创速工业有限公司 | A kind of design implementation method of elastic element module |
| CN110046394A (en) * | 2019-03-20 | 2019-07-23 | 广东高云半导体科技股份有限公司 | Integrated circuit netlist generation method, device, computer equipment and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| N. BOMBIERI ET AL: "SMAC: Smart Systems Co-Design", 《2013 16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN》 * |
| 张松等: "容器微云监控系统的设计和实现", 《中国科学技术大学学报》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111079362A (en) * | 2019-12-18 | 2020-04-28 | 京微齐力(北京)科技有限公司 | Parallel comprehensive algorithm utilizing hierarchical information |
| CN111580912A (en) * | 2020-05-09 | 2020-08-25 | 北京飞讯数码科技有限公司 | Display method and storage medium for multi-level structure resource group |
| CN112464591A (en) * | 2020-11-19 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Multi-port nested model connection analysis method and medium |
| US11829696B2 (en) | 2020-11-19 | 2023-11-28 | Inspur Suzhou Intelligent Technology Co., Ltd. | Connection analysis method for multi-port nesting model and storage medium |
| CN113032401A (en) * | 2021-03-31 | 2021-06-25 | 合安科技技术有限公司 | Big data processing method and device based on special-shaped structure tree and related equipment |
| CN113032401B (en) * | 2021-03-31 | 2023-09-08 | 合安科技技术有限公司 | Big data processing method and device based on special-shaped structure tree and related equipment |
| CN113255262A (en) * | 2021-06-07 | 2021-08-13 | 上海国微思尔芯技术股份有限公司 | Object allocation method and device, computer equipment and storage medium |
| CN117217147A (en) * | 2023-09-21 | 2023-12-12 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and medium for FPGA |
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