CN110489370B

CN110489370B - Hardware filling method for preprocessing SHA256 message of hash algorithm

Info

Publication number: CN110489370B
Application number: CN201910635665.2A
Authority: CN
Inventors: 饶博; 刘元; 熊晓明
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2019-07-15
Filing date: 2019-07-15
Publication date: 2023-05-23
Anticipated expiration: 2039-07-15
Also published as: CN110489370A

Abstract

The invention discloses a hardware filling method for preprocessing hash algorithm SHA256 messages, which utilizes two state machines to respectively calculate message length and filling messages, and can be divided into different states according to different outputs, at the moment, filled data can be transferred by only one 32-bit register, and the area of a chip is reduced. Meanwhile, on the framework, the processing of the filling module is easy, and the period required for inputting a message block is equal to the period for processing a message block, so that the processing speed of a chip is synchronous with an interface, a signal for handshaking with a filling part is reduced, and a gating clock unit is added in front of filling. The operation clock is turned off at the time of data stuffing according to the running state, and the stuffed clock is turned off at the time of processing operation. The design of low power consumption can greatly reduce the power consumption of the processing algorithm during hardware operation.

Description

Hardware filling method for preprocessing SHA256 message of hash algorithm

Technical Field

The invention relates to the field of hardware filling, in particular to a hardware filling method for preprocessing a hash algorithm SHA256 message.

Background

In the big data age, the development of social informatization and networking has led to explosive growth of data, and the global data volume is doubled about every two years, which means that the volume of data generated in the last two years by human beings is equivalent to the total volume of data generated before. Big data technology, which is silently permeated into various industry fields, gradually becomes a production element to play an important role. However, while big data technology has resulted in increased productivity and lifestyle changes, the attendant security challenges have not been ignored. At present, most of information security solutions are focused on a software level, and information security solutions based on a hardware level are also proposed, but means and methods for solving the problems are relatively single. With the continuous breakthrough of quantum computation, the existing information security identity authentication algorithm for information encryption and decryption is severely challenged.

The application of the Hash algorithm in the aspect of information security mainly comprises the following points:

(1) File verification

The more familiar check algorithms include parity check and CRC check, which do not have the ability to resist data tampering, and which detect and correct channel errors in data transmission to some extent, but do not prevent malicious corruption of the data.

(2) Digital signature

The Hash algorithm is also an important component in modern cryptography. Since the operation speed of the asymmetric algorithm is slow, the one-way hash function plays an important role in the digital signature protocol. Digitally signing the Hash value, also known as "digital digest", may be considered statistically equivalent to digitally signing the file itself.

(3) Authentication protocol

The following authentication protocol is also called challenge-authentication mode: in case the transmission channel is interception but not tampered with, this is a simple and secure way.

In order to solve the social problem caused by information security, in the design of integrated circuits such as embedded and analog front-end and back-end circuits, power consumption is increasingly in an important position, and often the power consumption of equipment can determine the service life of a product and the trend of the market.

Disclosure of Invention

The invention provides a hardware filling method for preprocessing hash algorithm SHA256 messages, which greatly improves the data processing speed.

In order to solve the technical problems, the technical scheme of the invention is as follows:

a hardware filling method for preprocessing a hash algorithm SHA256 message comprises the following steps:

s1: the message block is input into a computing state machine, the data length of the computing state machine is 32 bits each time the message block is input, and the computing state machine outputs the data length of the message block according to the input data times and the valid bytes of the data;

s2: inputting the output of the computing state machine and the message block into a filling state machine, wherein the filling state machine adds the output of the computing state machine to the tail of the message block to obtain a filled message block and outputs the filled message block;

s3: and transmitting the output of the filling state machine to an operation module, wherein the operation module outputs 32-bit data of the filled message block each time as the input of a data path.

Preferably, the output of the counting state machine is 64 bits, divided into four parts:

a 0 of 3 bits represents the smallest unit of measure of the message;

2 bits represent a valid byte of data;

4 bits represent the number of times of data input;

and a 55-bit counter, wherein after the number of times of input data is 16, the 55-bit counter is added with 1, and the 4 bits representing the number of times of input data are simultaneously cleared.

Preferably, the smallest unit of measure of the message is a byte.

Preferably, the operation module outputs 32-bit data of the padded message block in the next cycle every time data is input by stream processing.

Preferably, a 32-bit register is used to transfer the filled data.

Preferably, the method further comprises the step of controlling a gating clock unit, wherein the gating clock unit is added before filling, and the gating clock unit turns off an operation clock when data is filled according to the running state and turns off the filled clock when operation is processed.

Compared with the prior art, the technical scheme of the invention has the beneficial effects that:

the preprocessing in SHA256 algorithm is to supplement the required information after the message that wants to Hash, so that the whole message meets the specified structure. The preprocessing of the information is divided into two steps: additional padding bits and additional length. The two state machines are used for respectively calculating the message length and the filling message, and the two state machines can be divided into different states according to different outputs, at this time, the filled data can be transferred by only one 32-bit register, and the area of a chip is reduced. Meanwhile, on the framework, the processing of the filling module is easy, and the period required for inputting a message block is equal to the period for processing a message block, so that the processing speed of a chip is synchronous with an interface, a signal for handshaking with a filling part is reduced, and a gating clock unit is added in front of filling. The operation clock is turned off at the time of data stuffing according to the running state, and the stuffed clock is turned off at the time of processing operation. The design of low power consumption can greatly reduce the power consumption of the processing algorithm during hardware operation.

Drawings

FIG. 1 is a schematic flow chart of the present invention.

Fig. 2 is a clock control unit in the present invention.

Detailed Description

The drawings are for illustrative purposes only and are not to be construed as limiting the present patent;

for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions;

it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The technical scheme of the invention is further described below with reference to the accompanying drawings and examples.

Example 1

The embodiment provides a hardware filling method for preprocessing a hash algorithm SHA256 message, as shown in fig. 1, comprising the following steps:

The output of the counting state machine is 64 bits and is divided into four parts:

a 0 of 3 bits represents the smallest unit of measure of the message;

2 bits represent a valid byte of data;

4 bits represent the number of times of data input;

The smallest unit of measure of the message is a byte.

The operation module outputs 32-bit data of the filled message block in the next period every time data is input by stream processing. Since 16 cycles are required to input a message block (512 bits), and 16 cycles are also required to process a message block, the processing speed of the chip is synchronized with the interface, reducing a signal to handshake with the stuffing portion.

The 32-bit register is used to transfer the filled data.

The system also comprises a gating clock unit control, as shown in fig. 2, wherein a gating clock unit is added in front of the filling, and the gating clock unit turns off an operation clock when data is filled according to the running state and turns off the filled clock when the operation is processed.

The same or similar reference numerals correspond to the same or similar components;

the terms describing the positional relationship in the drawings are merely illustrative, and are not to be construed as limiting the present patent;

it is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.

Claims

1. A hardware population method for preprocessing a hash algorithm SHA256 message, comprising the steps of:

s3: transmitting the output of the filling state machine to an operation module, wherein the operation module outputs 32-bit data of the filled message block each time as the input of a data path;

the system also comprises a gating clock unit control, wherein a gating clock unit is added in front of the filling, the gating clock unit turns off an operation clock when data is filled according to the running state, and turns off the filled clock when the operation is processed.

2. The hardware population method of hash algorithm SHA256 message preprocessing according to claim 1, wherein the output of the computing state machine is 64 bits, divided into four parts: a 0 of 3 bits represents the smallest unit of measure of the message;

2 bits represent a valid byte of data;

4 bits represent the number of times of data input;

3. The hardware population method of hash algorithm SHA256 message preprocessing of claim 2, wherein the smallest unit of measure of the message is a byte.

4. A hardware padding method for hash algorithm SHA256 message preprocessing according to claim 3, wherein the operation module outputs 32-bit data of the padded message block in the next cycle with stream processing every time data is input.

5. The hardware population method for hash algorithm SHA256 message preprocessing of claim 4, wherein the packed data is transferred using a 32-bit register.