CN110489370A - A kind of pretreated hardware fill method of hash algorithm SHA256 message - Google Patents

A kind of pretreated hardware fill method of hash algorithm SHA256 message Download PDF

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Publication number
CN110489370A
CN110489370A CN201910635665.2A CN201910635665A CN110489370A CN 110489370 A CN110489370 A CN 110489370A CN 201910635665 A CN201910635665 A CN 201910635665A CN 110489370 A CN110489370 A CN 110489370A
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message
data
state machine
input
pretreated
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CN110489370B (en
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饶博
刘元
熊晓明
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Guangdong University of Technology
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Guangdong University of Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses a kind of pretreated hardware fill methods of hash algorithm SHA256 message, message-length and filling message are calculated separately using two state machines, different states is segmented into according to output difference, at this moment, it only needs one 32 registers that can transmit filled data, reduces the area of chip.Simultaneously on the framework, the processing of filling module becomes easy, since the period that one message blocks of input need is equal with the processing period of one message blocks, therefore, the processing speed of chip is with interface synchronization, reduce the signal shaken hands with fill part, while face adds a gate controlled clock unit before filling.State according to operation turns off operation clock when data are filled, and turns off the clock of filling when handling operation.The design of low-power consumption in this way is capable of handling algorithm when hardware computation, also can greatly reduce the consumption of power.

Description

A kind of pretreated hardware fill method of hash algorithm SHA256 message
Technical field
The present invention relates to hardware padding fields, pretreated hard more particularly, to a kind of hash algorithm SHA256 message Part fill method.
Background technique
The development of big data era, social informatization and networking causes data explosion formula to increase, and global metadata amount is about Double about every two years, it means that the total data amount that the data volume that the mankind generated at nearest 2 years generates before being equivalent to.Greatly Data technique quietly penetrates into various industries field, is increasingly becoming a kind of production factors and plays an important role.However, big number While according to technology yield being improved with lifestyle change, the following security challenge can not be ignored.It is directed at present The solution of information security mostly concentrates on software view, also has and proposes the information security solution based on hardware view, But its means for solving the problems, such as and method are all relatively simple.And it is existing about information with the continuous breakthrough of quantum calculation Safety identification authentication, the algorithm of information encryption and decryption is all by serious challenge.
Application of the hash algorithm in terms of information security is mainly reflected in the following:
(1) file verification
We have parity check sum CRC check by familiar checking algorithm, and there is no anti-data tamperings for both verifications Ability, they can detect to a certain extent and correct the channel error code in data transmission, but cannot prevent the evil to data Meaning is destroyed.
(2) digital signature
Hash algorithm is also an important component in modern password system.Due to the arithmetic speed of asymmetric arithmetic It is relatively slow, so one-way hash function plays an important role in digital signature protocol.It is to hash value, also known as " digital Abstract " is digitally signed, statistically it is considered that being equivalent with being digitally signed to file itself.
(3) authentication protocol
Following authentication protocol is also referred to as challenge -- and certification mode: being that can be listened, but can not be usurped in transmission channel In the case where changing, this is a kind of simple and safety method.
In order to solve information security bring social concern, the IC design such as terminal circuit before and after embedded, simulation In, power consumption increasingly occupys an important position, and often the power consumption of equipment can determine the service life of product and the trend in market.
Summary of the invention
The present invention provides a kind of pretreated hardware fill method of hash algorithm SHA256 message, significantly promotes data Processing speed.
In order to solve the above technical problems, technical scheme is as follows:
A kind of pretreated hardware fill method of hash algorithm SHA256 message, comprising the following steps:
S1: message blocks input calculates in state machine, and the data length that each message blocks input calculates state machine is 32 bits, Calculate state machine according to the input data the effective byte of number and data output message blocks data length；
S2: the output for calculating state machine is input in occupied state machine together with message blocks, and the occupied state machine will The end that the output of calculating state machine is added to message blocks obtains filled message blocks and exports；
S3: the output of the occupied state machine is transferred to computing module, after the computing module exports filling each time Message blocks input of 32 bit datas as data path.
Preferably, the output of the count state machine is 64 bits, is divided into four parts:
The 0 of 3 bits indicates the smallest linear module of message；
The effective byte of 2 bits expression data；
4 bits indicate the data times of input；
The counter of 55 bits, after the data times of input are 16 full, the counter of 55 bit adds 1, the table Show 4 bits of the data times of input while resetting.
Preferably, the smallest linear module of the message is byte.
Preferably, the computing module utilizes stream process, and data of every input export filled disappear in next period Cease 32 bit datas of block.
Preferably, filled data are transmitted using 32 registers.
It preferably, further include gate controlled clock unit control, face adds a gate controlled clock unit before filling, when the gate Clock unit turns off operation clock when data are filled according to the state of operation, and by filling when handling operation Clock is turned off.
Compared with prior art, the beneficial effect of technical solution of the present invention is:
Pretreatment in SHA256 algorithm is exactly that the information of needs is supplemented behind the message for wanting Hash, makes entire message Meet specified structure.The pretreatment of information is divided into two steps: additional padding bits and additional length.Utilize two state machines Message-length and filling message are calculated separately, different states is segmented into according to output difference, at this moment, it is only necessary to one 32 The register of position can transmit filled data, reduce the area of chip.Simultaneously on the framework, the place of module is filled Reason becomes easy, since the period that one message blocks of input need is equal with the processing period of one message blocks, chip Processing speed reduces one and signal that fill part is shaken hands with interface synchronization, while when face adds a gate before filling Clock unit.State according to operation turns off operation clock when data are filled, and will filling when handling operation Clock turn off.The design of low-power consumption in this way is capable of handling algorithm when hardware computation, also can greatly reduce power Consumption.
Detailed description of the invention
Fig. 1 is flow diagram of the invention.
Fig. 2 is the clock control cell in the present invention.
Specific embodiment
The attached figures are only used for illustrative purposes and cannot be understood as limitating the patent；
In order to better illustrate this embodiment, the certain components of attached drawing have omission, zoom in or out, and do not represent actual product Size；
To those skilled in the art, it is to be understood that certain known features and its explanation, which may be omitted, in attached drawing 's.
The following further describes the technical solution of the present invention with reference to the accompanying drawings and examples.
Embodiment 1
The present embodiment provides a kind of pretreated hardware fill method of hash algorithm SHA256 message, such as Fig. 1, including it is following Step:
S1: message blocks input calculates in state machine, and the data length that each message blocks input calculates state machine is 32 bits, Calculate state machine according to the input data the effective byte of number and data output message blocks data length；
S2: the output for calculating state machine is input in occupied state machine together with message blocks, and the occupied state machine will The end that the output of calculating state machine is added to message blocks obtains filled message blocks and exports；
S3: the output of the occupied state machine is transferred to computing module, after the computing module exports filling each time Message blocks input of 32 bit datas as data path.
The output of the count state machine is 64 bits, is divided into four parts:
The 0 of 3 bits indicates the smallest linear module of message；
The effective byte of 2 bits expression data；
4 bits indicate the data times of input；
The counter of 55 bits, after the data times of input are 16 full, the counter of 55 bit adds 1, the table Show 4 bits of the data times of input while resetting.
The smallest linear module of message is byte.
The computing module utilizes stream process, and data of every input export filled message blocks in next period 32 bit datas.Since one message blocks (512 bit) of input needs 16 periods, handling a message blocks was also 16 week Phase, therefore, the processing speed of chip reduce the signal shaken hands with fill part with interface synchronization.
Filled data are transmitted using 32 registers.
It further include gate controlled clock unit control, such as Fig. 2, face adds a gate controlled clock unit before filling, when the gate Clock unit turns off operation clock when data are filled according to the state of operation, and by filling when handling operation Clock is turned off.
The same or similar label correspond to the same or similar components；
The terms describing the positional relationship in the drawings are only for illustration, should not be understood as the limitation to this patent；
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this Made any modifications, equivalent replacements, and improvements etc., should be included in the claims in the present invention within the spirit and principle of invention Protection scope within.

Claims (6)

1. a kind of pretreated hardware fill method of hash algorithm SHA256 message, which comprises the following steps:
S1: message blocks input calculates in state machine, and the data length that each message blocks input calculates state machine is 32 bits, calculates State machine according to the input data the effective byte of number and data output message blocks data length；
S2: the output for calculating state machine is input in occupied state machine together with message blocks, and the occupied state machine will calculate The end that the output of state machine is added to message blocks obtains filled message blocks and exports；
S3: the output of the occupied state machine is transferred to computing module, the computing module exports filled disappear each time Cease input of 32 bit datas of block as data path.
2. the pretreated hardware fill method of hash algorithm SHA256 message according to claim 1, which is characterized in that institute The output for stating count state machine is 64 bits, is divided into four parts:
The 0 of 3 bits indicates the smallest linear module of message；
The effective byte of 2 bits expression data；
4 bits indicate the data times of input；
The counter of 55 bits, after the data times of input are 16 full, the counter of 55 bit adds 1, and the expression is defeated It 4 bits of the data times entered while resetting.
3. the pretreated hardware fill method of hash algorithm SHA256 message according to claim 2, which is characterized in that institute Stating the smallest linear module of message is byte.
4. the pretreated hardware fill method of hash algorithm SHA256 message according to claim 3, which is characterized in that institute Computing module is stated using stream process, data of every input export 32 bit datas of filled message blocks in next period.
5. the pretreated hardware fill method of hash algorithm SHA256 message according to claim 4, which is characterized in that make Filled data are transmitted with 32 registers.
6. existing according to claim 1 to the pretreated hardware fill method of hash algorithm SHA256 message, feature described in 5 In further including gate controlled clock unit control, face adds a gate controlled clock unit before filling, and the gate controlled clock unit is according to fortune Capable state turns off operation clock when data are filled, and turns off the clock of filling when handling operation.
CN201910635665.2A 2019-07-15 2019-07-15 Hardware filling method for preprocessing SHA256 message of hash algorithm Active CN110489370B (en)

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Cited By (4)

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CN111612622A (en) * 2020-05-20 2020-09-01 深圳比特微电子科技有限公司 Circuit and method for implementing a hashing algorithm
CN112104449A (en) * 2020-08-20 2020-12-18 郑州信大捷安信息技术股份有限公司 SDK for Hash algorithm
CN113794567A (en) * 2021-09-13 2021-12-14 上海致居信息科技有限公司 Synthesis acceleration method and device of SHA256 Hash algorithm zero-knowledge proof circuit
CN115834027A (en) * 2023-01-06 2023-03-21 浪潮电子信息产业股份有限公司 Message filling method, device, equipment and computer readable storage medium

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CN113794567A (en) * 2021-09-13 2021-12-14 上海致居信息科技有限公司 Synthesis acceleration method and device of SHA256 Hash algorithm zero-knowledge proof circuit
CN113794567B (en) * 2021-09-13 2024-04-05 上海致居信息科技有限公司 Synthetic acceleration method and device for SHA256 hash algorithm zero knowledge proof circuit
CN115834027A (en) * 2023-01-06 2023-03-21 浪潮电子信息产业股份有限公司 Message filling method, device, equipment and computer readable storage medium

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