CN110489362B - eMMC correction output/input effective window automatic adjustment method, device and storage medium - Google Patents
eMMC correction output/input effective window automatic adjustment method, device and storage medium Download PDFInfo
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- CN110489362B CN110489362B CN201910778526.5A CN201910778526A CN110489362B CN 110489362 B CN110489362 B CN 110489362B CN 201910778526 A CN201910778526 A CN 201910778526A CN 110489362 B CN110489362 B CN 110489362B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses an automatic adjusting method, a device and a storage medium for an eMMC (enhanced multimedia card) correction input/output valid window, which comprise the following units: the clock control unit can control and adjust the position of the reference clock; the delay unit can be used for micro-correcting and adjusting the position of the reference clock through the adjusting delay unit; the IO PAD can be looped back, and a loop can be set to enable output data to be fed back; the feedback mode data is the output data when the present invention is applied, and can be compared with the loop back data. The invention adjusts the emmc device to correct the effective output window of the corresponding clock and corrects the difference of the output port of the emmc device.
Description
Technical Field
The invention relates to the technical field of storage devices, in particular to eMMC input/output timing control, and specifically relates to an automatic adjusting method, device and storage medium for an eMMC correction input/output effective window.
Background
eMMC has different transmission rates, each transmission rate having different conditions for the output-to-input timing. And the setting of the bus speed mode, which is a timing specification for host and eMMC communication.
CLK
The CLK signal is used for outputting a clock signal from the Host end, and carrying out synchronization of data transmission and driving of equipment operation.
During one clock cycle, 1 bit transmission, i.e., SDR (Single Data Rate) mode, can be supported on both the CMD and DAT0-7 signals. In addition, the DAT0-7 signal also supports configuration in a DDR (double Data rate) mode, where 2 bits may be transferred in one clock cycle.
Host can dynamically adjust the frequency of the clock signal during communication (note that the frequency range needs to meet the Spec definition). By adjusting the clock frequency, power saving or data flow control (avoiding Over-run or Under-run) functions can be achieved. In some scenarios, the Host may also turn off the clock, for example, when the eMMC is in Busy State, or when receiving data and entering into Programming State.
CMD
The CMD signal is mainly used for sending Command to the eMMC by the Host and sending Response to the Host by the eMMC.
DAT0-7
The DAT0-7 signal is primarily used for data transfer between Host and eMMC. After the eMMC is powered on or is in soft reset, only the DAT0 can perform data transmission, and after initialization is completed, the configurable DAT0-3 or DAT0-7 performs data transmission, namely the data bus can be configured to be in a 4-bit or 8-bit mode.
Data Strobe
The Data Strobe clock signal is sent to the Host by the eMMC, has the same frequency as the CLK signal, and is used for synchronizing Data receiving at the Host end. The Data Strobe signal can be configured and started only in the HS400 mode, and after being started, the stability of Data transmission can be improved, and the bus tuning process is omitted.
In the eMMC bus, there may be one Host, a plurality of eMMC Devices. All communication on the bus is initiated by a Command terminal, and the Host can only communicate with one eMMC Device at a time. After the system is powered on and started, the Host allocates addresses (RCA) to all eMMC devices one by one. When the Host needs to communicate with one eMMC Device, the eMMC Device is selected according to the RCA, and only the selected eMMC Device responds to the Command of the Host.
The bus speed modes of the host and the emmc device need to be matched to realize normal communication, and a host side and an emmc device side need to be set. The host side may send tuning pattern data blocks for transmission rate changes using instructions 21, device. And the Host collects data at different sampling points to find the optimal sampling point. The emmc device adjusts the output and input timings for different transmission rates, which is usually based on factory initial general settings, and cannot adjust a single emmc device one by one, so that there may be calibration difficulties and blind spots for different environments or chips.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to solve the defects in the prior art and provides an automatic adjustment method for an eMMC correction input/output valid window, wherein the adjustment of input/output timing for different transmission rates by an eMMC device is usually based on factory initial universal setting, and single eMMC device cannot be adjusted one by one, so that the transmission rate change can be set for a host side aiming at different environments or chips possibly with difficulty and blind points in correction, and the eMMC device can automatically correct the corresponding input/output valid window.
The technical scheme is as follows:
an automatic adjusting method for an eMMC correction input/output valid window comprises the following steps:
receiving instruction data;
processing the received data;
clock control, according to the received instruction data, controlling and adjusting the position of the reference clock;
performing delay adjustment processing to correct the reference clock position data;
sending data to an internal loopback data interface;
the internal loop processes the received data and searches left and right boundaries of each data interface;
checking whether the data of the internal loop is correct, if so, outputting the data of the internal loop, and adjusting delay;
recording the left and right boundaries, setting an optimal value aiming at the new speed, and finding out all data interfaces in sequence;
closing the internal loop data interface;
leaving the program state.
The invention is further improved in that the internal loop processes the received data by the specific steps of:
receiving corrected clock position data;
outputting the corrected clock position data;
receiving clock position data of the corrected clock position;
carrying out feedback output on the clock position data of the corrected clock position;
comparing the feedback output clock position data with the corrected clock position data;
and judging whether the clock position data fed back and output is correct or not, and if so, adjusting the delay.
A further improvement of the invention is that the delay adjustment process adjusts the reference clock position according to the clock output timing requirements.
An automatic adjustment device for eMMC calibration I/O valid window,
the method comprises the following steps: a processor for executing the following program modules stored in the memory:
the receiving module is used for receiving instruction data;
the clock control unit module is used for controlling and adjusting the reference clock position data according to the received instruction data;
the delay unit module is used for correcting the reference clock position data;
and the internal loop module is used for searching the left and right boundaries of each data interface, checking whether the data of the internal loop is correct or not, and recording the left and right boundaries.
The invention is further improved in that the internal loop-back module comprises a feedback mode data module and a loop-back module;
the feedback mode data module is used for receiving the corrected clock position data and outputting the corrected clock position data;
the loop-returning module is used for receiving the clock position data output by the feedback mode data module and performing feedback output on the clock position data output by the feedback mode data module;
the feedback mode data module is also used for receiving the clock position data output by feedback and comparing the clock position data output by feedback with the corrected clock position data.
The invention is further improved in that the feedback mode data module is a bidirectional IO pad, and includes an input terminal, an output enable port, and a loopback enable port, and the loopback enable port is connected to the input port.
The device for automatically adjusting the eMMC correction input-output valid window comprises a memory, a processor and a computer program which is stored in the memory and can run on the processor, wherein when the processor executes the computer program, the steps of the method for automatically adjusting the eMMC correction input-output valid window are realized.
A computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for automatically adjusting the eMMC correction I/O valid window are realized.
Compared with the prior art, the method for automatically adjusting the eMMC correction input/output valid window provided by the invention at least has the following beneficial effects:
the invention can set the transmission rate change aiming at the host side, and the emmc device can automatically correct the corresponding input and output valid window.
Of course, it is not specifically necessary for any one product that implements the invention to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a flow chart of the operation of the present invention;
FIG. 2 is a state diagram of an output port prior to adjustment;
FIG. 3 is a state diagram of the output port after adjustment;
FIG. 4 is a schematic diagram of output port with clock control after adjustment;
FIG. 5 is a schematic diagram of adjusting the position of a reference clock;
FIG. 6 is a flow chart of the implementation operation.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
In the case of the example 1, the following examples are given,
as shown in fig. 1, an eMMC calibration io effective window automatic adjustment method includes the following steps:
receiving instruction data;
processing the received data;
clock control, according to the received instruction data, controlling and adjusting the position of the reference clock;
performing delay adjustment processing to correct the reference clock position data; wherein, the schematic diagram of adjusting the reference clock position is shown in fig. 5;
sending data to an internal loopback data interface;
the internal loop processes the received data and searches left and right boundaries of each data interface;
checking whether the data of the internal loop is correct, if so, outputting the data of the internal loop, and adjusting delay;
recording the left and right boundaries, setting an optimal value aiming at the new speed, and finding out all data interfaces in sequence;
closing the internal loop data interface;
leaving the program state.
Based on the above embodiment, when the eMMC host controls to send a command to switch speeds, the eMMC device enters a program state (Prg state) upon receiving the command. After entering the program state, the reference clock position is adjusted according to the new speed setting, and the reference clock position can be adjusted according to the clock output timing requirement. And sending data to the data interface of the internal loop, enabling the data interface to enable the internal loop, namely opening the internal loop through the data interface, and adjusting the delay unit to search the left and right boundaries of each data interface. The method for searching the left and right boundaries of the data interface can be to send a set of specific data combinations internally, send the data by feedback mode, check whether the data is wrong after looping back, and adjust the delay unit if the data is correct until the data error occurs.
To further explain the embodiment, it should be noted that the specific steps of the internal loopback for processing the received data are as follows:
a feedback mode data module in the internal loop receives the corrected clock position data;
meanwhile, a feedback mode data module in the internal loop outputs the corrected clock position data;
a loopable module in the internal looper receiving the clock position data of the corrected clock position;
a loop returning module in the internal loop for performing feedback output on the clock position data of the corrected clock position;
a feedback mode data module in the internal loop compares the feedback output clock position data with the corrected clock position data;
and judging whether the clock position data fed back and output is correct or not, and if so, adjusting the delay.
To further explain the present embodiment, it should be noted that the delay adjustment process adjusts the reference clock position according to the clock output timing requirement.
In the case of the example 2, the following examples are given,
as shown in fig. 1, an apparatus for automatic adjustment of an eMMC calibration io active window includes: a processor for executing the following program modules stored in the memory:
the receiving module is used for receiving instruction data;
the clock control unit module is used for controlling and adjusting the reference clock position data according to the received instruction data;
the delay unit module is used for correcting the reference clock position data;
and the internal loop module is used for searching the left and right boundaries of each data interface, checking whether the data of the internal loop is correct or not, and recording the left and right boundaries.
To further explain the present embodiment, it should be noted that the internal loopback module includes a feedback mode data module and a loopback module;
the feedback mode data module is used for receiving the corrected clock position data and outputting the corrected clock position data;
the loop-returning module is used for receiving the clock position data output by the feedback mode data module and performing feedback output on the clock position data output by the feedback mode data module; the internal loop back module is started to enable the output data to be fed back;
the feedback mode data module is also used for receiving the clock position data output by feedback, comparing the clock position data output by feedback with the corrected clock position data and outputting the data.
Based on the embodiment, the invention can set the transmission rate change aiming at the host side, and the emmc device can automatically correct the corresponding input and output valid window.
To further explain the embodiment, it should be noted that the feedback mode data module is a bidirectional IO pad, and includes an input terminal, an output enable port, and a loopback enable port, where the loopback enable port is connected to the input port. Wherein, enable is an enable meaning for opening IO internal loop. The output enable port and the loopback enable port are opened only in the state required to be adjusted.
The invention adjusts emmc device to correct the output valid window of the corresponding clock. Fig. 2, 3 and 4 show the differences of emmc device output ports, wherein the state diagram of the output ports before adjustment is as shown in fig. 2, the state diagram of the output ports after adjustment is as shown in fig. 3, and the schematic diagram of the output ports after adjustment and the clock control are as shown in fig. 4.
In the case of the example 3, the following examples are given,
an apparatus/terminal device for automatically adjusting an eMMC calibration io window includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the eMMC calibration io window automatic adjustment method in embodiment 1 when executing the computer program.
In the case of the example 4, the following examples are given,
a computer readable storage medium storing a computer program which, when executed by a processor, performs the steps of the method for automatically adjusting an eMMC calibration io window, as in embodiment 1.
In the case of the example 5, the following examples were conducted,
as shown in fig. 6, an eMMC calibration io effective window automatic adjustment method includes the following steps:
starting;
judging whether the tuning phase is automatically adjusted or not;
and (3) the harmonic phase needs to be automatically adjusted, then an internal loop is opened through a data interface:
setting a DATA left boundary, and checking feedback DATA;
setting a DATA right boundary, and checking feedback DATA;
closing a loop inside the data interface;
and (6) ending.
And if the harmonic phase does not need to be automatically adjusted, directly skipping is finished.
As can be seen from the foregoing embodiments, the method, apparatus, and storage medium for automatically adjusting an eMMC calibration i/o valid window according to the present invention at least achieve the following advantages:
the invention can set the transmission rate change aiming at the host side, and the emmc device can automatically correct the corresponding input and output valid window.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (8)
1. An automatic adjustment method for an eMMC correction input/output valid window is characterized by comprising the following steps:
receiving instruction data;
processing the received data;
clock control, according to the said instruction data received, control and regulate the position of reference clock;
performing delay adjustment processing to correct the reference clock position data;
sending data to an internal loopback data interface;
the internal loop processes the received data and searches left and right boundaries of each data interface;
checking whether the data of the internal loop is correct, if so, outputting the data of the internal loop, and adjusting delay;
recording the left and right boundaries, setting an optimal value aiming at the new speed, and finding out all data interfaces in sequence;
closing the internal loopback data interface;
leaving the program state.
2. The method of claim 1, wherein the eMMC correction IO payload window auto-adjustment,
the specific steps of the internal loop for processing the received data are as follows:
receiving the corrected clock position data;
outputting the corrected clock position data;
receiving clock position data of the corrected clock position;
carrying out feedback output on the clock position data of the corrected clock position;
comparing the clock position data output by feedback with the corrected clock position data;
and judging whether the clock position data output by feedback is correct or not, and if so, adjusting the delay.
3. The method of claim 1, wherein the eMMC correction IO payload window auto-adjustment,
and the delay adjustment processing is used for adjusting the position of the reference clock according to the clock output timing requirement.
4. An apparatus for automatically adjusting an input/output valid window for eMMC calibration, comprising: a processor for executing the following program modules stored in memory:
the receiving module is used for receiving instruction data;
the clock control unit module is used for controlling and adjusting the reference clock position data according to the received instruction data;
the delay unit module is used for correcting the reference clock position data;
and the internal loop module is used for searching the left and right boundaries of each data interface, checking whether the data of the internal loop is correct or not, and recording the left and right boundaries.
5. The apparatus of claim 4, wherein the eMMC device is configured to automatically adjust the IO enabled window,
the internal loop back module comprises a feedback mode data module and a loop back module;
the feedback mode data module is used for receiving the corrected clock position data and outputting the corrected clock position data;
the loop-returning module is used for receiving the clock position data output by the feedback mode data module and performing feedback output on the clock position data output by the feedback mode data module;
the feedback mode data module is also used for receiving the clock position data output by feedback and comparing the clock position data output by feedback with the corrected clock position data.
6. The apparatus for automatic adjustment of an IO valid window for eMMC correction of claim 5,
the feedback mode data module is a bidirectional IO pad and comprises an input end, an output enabling port and a loop enabling port, and the loop enabling port is connected with the input port.
7. An apparatus for eMMC corrected io active window auto-adjustment, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the steps of the method of claim 1 or 2 are performed when the computer program is executed by the processor.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method steps of claim 1 or 2.
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| CN201910778526.5A CN110489362B (en) | 2019-08-22 | 2019-08-22 | eMMC correction output/input effective window automatic adjustment method, device and storage medium |
| PCT/CN2019/112183 WO2021031325A1 (en) | 2019-08-22 | 2019-10-21 | Adjustment method and device for emmc to correct output/input valid window, and storage medium |
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| CN201910778526.5A CN110489362B (en) | 2019-08-22 | 2019-08-22 | eMMC correction output/input effective window automatic adjustment method, device and storage medium |
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| CN111722670B (en) * | 2020-06-23 | 2022-06-07 | 湖南国科微电子股份有限公司 | eMMC timing sequence adjustment method, system and eMMC main control chip |
| CN115440295B (en) * | 2022-11-09 | 2023-02-03 | 合肥康芯威存储技术有限公司 | Device and method for testing data loading capacity of eMMC chip |
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| CN105930241A (en) * | 2016-05-05 | 2016-09-07 | 福州瑞芯微电子股份有限公司 | Method and apparatus for adjusting phases of EMMC interface and NAND interface |
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| KR100863001B1 (en) * | 2007-02-09 | 2008-10-13 | 주식회사 하이닉스반도체 | Delayed Locked Loop Circuit with Duty Cycle Correction and Control Method of the same |
| US9772651B2 (en) * | 2012-09-14 | 2017-09-26 | Samsung Electronics Co., Ltd. | Embedded multimedia card (eMMC), host controlling eMMC, and method operating eMMC system including the use of a switch command defining an adjustment delay for a data signal |
| CN109284238B (en) * | 2018-09-04 | 2021-10-19 | 晶晨半导体(上海)股份有限公司 | Method and system for enhancing stability of eMMC interface |
| CN110109509B (en) * | 2019-03-27 | 2021-03-02 | 北京比特大陆科技有限公司 | Delay correction method, circuit, device, equipment and computer readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105895161A (en) * | 2015-02-17 | 2016-08-24 | 三星电子株式会社 | Storage Devices, Memory Systems And Operating Methods Thereof |
| CN105930241A (en) * | 2016-05-05 | 2016-09-07 | 福州瑞芯微电子股份有限公司 | Method and apparatus for adjusting phases of EMMC interface and NAND interface |
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