CN110489298A - A method of improving server PCIe device job stability - Google Patents
A method of improving server PCIe device job stability Download PDFInfo
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- CN110489298A CN110489298A CN201910631232.XA CN201910631232A CN110489298A CN 110489298 A CN110489298 A CN 110489298A CN 201910631232 A CN201910631232 A CN 201910631232A CN 110489298 A CN110489298 A CN 110489298A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- General Engineering & Computer Science (AREA)
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Abstract
The present invention provides a kind of method for improving server PCIe device job stability: 1. establish server PCIe device topology List；2. the PCIe device in pair server PCIe device topology List carries out applied voltage test；3. monitoring the AER characteristic of PCIe device, whether the frequency that reports an error that judgement can wherein correct mistake CE is normal；If so, into 4；If it is not, into 5；4. judging whether the applied voltage test time reaches setting time；If it is not, returning to 3；If so, into 6；5. the position of the PCIe device of the frequency anomaly that reports an error of CE is recorded, into 6；6. test terminates, output test result.The present invention is reported an error frequency using CE in AER, the relevant register of CE is monitored by backstage, filters out assemble server not in place in advance, there are the PCIe devices of risk for discovery in time, the stability of PCIe device is improved, the stability and reliability of server assembling production are improved.
Description
Technical field
The invention belongs to server the field of test technology, and in particular to a kind of raising server PCIe device job stability
Method.
Background technique
PCIe is Peripheral Component Interconnect Express abbreviation, is a kind of server periphery
Bus interface.
AER is the abbreviation of Advanced Error Reporting, is a kind of Capability of PCIe bus (characteristic).
The CE (Correctable Error) and UCE that general record PCIe device is run in this Capability
(Uncorrectable Error), UCE report an error generally equipment and server platform, software it is incompatible caused by, and CE more may be used
Can cause for assembling factor (including but it is not comprehensive, in addition to assembling factor, it is also possible to for deficient purchase etc.).CE is
The abbreviation of Correctable Error is recoverable mistake.
PCIe bus is a kind of most important peripheral bus in current server field, and almost all of CPU peripheral hardware is all logical
It crosses PCIe bus to be expanded, common peripheral hardware includes GPU card, FPGA card, storage card, network interface card, NVME hard disk etc..
PCIe bus has point-to-point transmission characteristic, and transmission rate is high, quite long in the past with roomy, Yi Tuozhan
In the development of time, a very complete ecosystem is formd, a large amount of peripheral hardware all uses this interface, it may be said that
PCIe bus is a kind of most important peripheral bus in current traditional server field.PCIe bus is developed so far, after
Mostly generation, the interface being most widely used at present are Gen3, and rate 8Gb/s, next-generation Gen4 rate is even more up to 16Gb/s.
PCIe interface rate is high, if because of assembly failure in production process, such as cable, board grafting are not in place, clothes
Business device will lead to the problem of in the course of subsequent work it is various, so PCIe is set when server production and assembly
The stability of standby work is particularly important, lacks the effective ways to the monitoring of PCIe device job stability at present.
This is the deficiencies in the prior art, therefore, in view of the above-mentioned drawbacks in the prior art, provides a kind of raising server
The method of PCIe device job stability, is necessary.
Summary of the invention
For the above-mentioned defect for lacking the effective ways to the monitoring of PCIe device job stability of the prior art, the present invention
A kind of method for improving server PCIe device job stability is provided, to solve the above technical problems.
The present invention provides a kind of method for improving server PCIe device job stability, includes the following steps:
S1. server PCIe device topology List is established；
S2. applied voltage test is carried out to the PCIe device in server PCIe device topology List；
S3. the AER characteristic of PCIe device is monitored, whether the frequency that reports an error that judgement can wherein correct mistake CE is normal；
If so, entering step S4；
If it is not, entering step S5；
S4. judge whether the applied voltage test time reaches setting time；
If it is not, return step S3；
If so, entering step S6；
S5. record can correct mistake the position of the PCIe device of the frequency anomaly that reports an error of CE, and enter step S6；
S6. test terminates, and outputs test result.
Further, specific step is as follows by step S1:
S11. the topological structure of PCIe device is obtained by lspci order；
S12. all PCIe devices of AER characteristic will be supported to generate a PCIe device list, PCIe device list is with every
Bus, device name and the function of a PCIe device are index.Lspci-vt orders the available topology knot to PCIe device
Structure, PCIe device include three kinds of topological structures with CPU interconnection: one, PCIe device directly passes through PCIe bus interface and CPU phase
Even；Two, PCIe device is expanded by PCIe-switch, and the end upstream is connected with CPU；Three, PCIe device passes through
PCIe-bridge is connected with CPU.The PCIe device of these three topological structures is added to PCIe device list in step S1
In.
Further, further include following steps in step S1:
S13. the frequency threshold that reports an error for correcting mistake CE that each PCIe device allows is generated.The step is supplied to step
Report an error frequency threshold of the S3 as the benchmark CE of monitoring.
Further, specific step is as follows by step S3:
S31. the AER characteristic of each PCIe device is monitored, the frequency real value that reports an error that can correct mistake CE is obtained；
S32. the frequency real value that reports an error for correcting mistake CE of more each PCIe device is corrected mistake with what is allowed
The frequency threshold that reports an error of CE；
What whether the frequency real value that reports an error that S33. judgement can correct mistake CE was less than permission corrects mistake reporting an error for CE
Frequency threshold；
If so, the frequency that reports an error for correcting mistake CE of corresponding PCIe device is normal；
If it is not, then corresponding to the frequency anomaly that reports an error for correcting mistake CE of PCIe device.The benchmark CE that step S13 is provided
Report an error frequency threshold compared with the frequency that reports an error of real-time CE, can determine whether that CE reports an error exception.
Further, specific step is as follows by S31:
S311. the CE status register in the AER characteristic of each PCIe device is monitored, the CE status register includes not
Good TLP status register, bad DLLP status register, rollover states register and replay timeout register；
S312. judge whether set occur in aforementioned four CE status register；
If so, CE of record reports an error to CE and reports an error list；The CE status register of set is emptied, is entered step
S313；
If it is not, then entering step S313；
S313. judge whether poll time setting value reaches；
If so, return step S311；
If it is not, then return step S313.One in four CE status registers there is set, then proves to generate a CE
It reports an error.
Further, poll time setting value takes 10s.Monitoring is by the way of poll, automatic regular polling, it is ensured that do not omit CE
It reports an error.
Further, it in S31, obtains CE and reports an error the time interval that reports an error in list, reporting an error for CE can be corrected mistake by calculating
Frequency real value.It can calculate CE according to the CE of the same PCIe device multiple time intervals that report an error in list that report an error and report an error frequency
Rate.
Further, specific step is as follows by step S13:
S131. the value for reading the connection status register of each PCIe device obtains the connection speed and band of PCIe device
It is wide；
S132. the frequency that reports an error that can correct mistake CE is calculated according to the connection speed and bandwidth meter of the bit error rate and PCIe device
Rate threshold value.CE reports an error frequency threshold, can be set in advance, can also be according to the connection speed of PCIE device, bandwidth and error rate calculation
Out.
Further, the value of the bit error rate takes 10-13。10-13For the admissible bit error rate.
Further, it in step S6, if the frequency that reports an error is normal, exports test and passes through；
If reporting an error frequency anomaly, export test and do not pass through, records bus, device name and the function of the position that reports an error, and
Maintenance personal is notified to overhaul.
The beneficial effects of the present invention are,
A kind of method improving server PCIe device job stability provided by the invention, is reported an error using the CE in AER
Frequency is logical, and platform is monitored the relevant register of CE later, filters out assemble server not in place in advance, timely find
There are the PCIe devices of risk, are repaired in time, improve the stability and reliability of server assembling production, improve PCIE
The stability of equipment.
In addition, design principle of the present invention is reliable, structure is simple, has very extensive application prospect.
It can be seen that compared with prior art, the present invention implementing with substantive distinguishing features outstanding and significant progress
Beneficial effect be also obvious.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the method for the embodiment of the present invention 1；
Fig. 2 is the flow diagram of the method for the embodiment of the present invention 2；
Fig. 3 is the flow diagram for obtaining the frequency real value that reports an error that can correct mistake CE；
Fig. 4 is the flow diagram for generating the frequency threshold that reports an error for correcting mistake CE that each PCIe device allows.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
Embodiment 1:
As shown in Figure 1, the present invention provides a kind of method for improving server PCIe device job stability, including walk as follows
It is rapid:
S1. server PCIe device topology List is established；
S2. applied voltage test is carried out to the PCIe device in server PCIe device topology List；
S3. the AER characteristic of PCIe device is monitored, whether the frequency that reports an error that judgement can wherein correct mistake CE is normal；
If so, entering step S4；
If it is not, entering step S5；
S4. judge whether the applied voltage test time reaches setting time；
If it is not, return step S3；
If so, entering step S6；
S5. record can correct mistake the position of the PCIe device of the frequency anomaly that reports an error of CE, and enter step S6；
S6. test terminates, and outputs test result；
If the frequency that reports an error is normal, exports test and pass through；
If reporting an error frequency anomaly, export test and do not pass through, records bus, device name and the function of the position that reports an error, and
Maintenance personal is notified to overhaul.
In the embodiment, PCIe device and CPU interconnection include three kinds of topological structures: one, PCIe device directly passes through PCIe
Bus interface is connected with CPU；Two, PCIe device is expanded by PCIe-switch, and the end upstream is connected with CPU；Three,
PCIe device is connected by PCIe-bridge with CPU.The PCIe device of these three topological structures is added in step S1
In PCIe device list.Corresponding pressure test is carried out to different PCIe devices in step S2, as NVME hard disk progress fio is hard
Disk pressure test, NV-GPU card carry out NV-QUAL test, and the pressure test that different PCIe devices carries out is different, it is therefore an objective to will
All PCIe devices carry out pressure test, run.
Embodiment 2:
As shown in Fig. 2, the present invention provides a kind of method for improving server PCIe device job stability, including walk as follows
It is rapid:
S1. server PCIe device topology List is established；Specific step is as follows:
S11. the topological structure of PCIe device is obtained by lspci order；It is grabbed under system by lspci-vt order
The topological structure of PCIe device；
S12. all PCIe devices of AER characteristic will be supported to generate a PCIe device list, PCIe device list is with every
Bus, device name and the function of a PCIe device are index；
S13. the frequency threshold that reports an error for correcting mistake CE that each PCIe device allows is generated；
S2. applied voltage test is carried out to the PCIe device in server PCIe device topology List；
S3. the AER characteristic of PCIe device is monitored, whether the frequency that reports an error that judgement can wherein correct mistake CE is normal；Specifically
Steps are as follows:
S31. the AER characteristic of each PCIe device is monitored, the frequency real value that reports an error that can correct mistake CE is obtained；
S32. the frequency real value that reports an error for correcting mistake CE of more each PCIe device is corrected mistake with what is allowed
The frequency threshold that reports an error of CE；
What whether the frequency real value that reports an error that S33. judgement can correct mistake CE was less than permission corrects mistake reporting an error for CE
Frequency threshold；
If so, the frequency that reports an error for correcting mistake CE of corresponding PCIe device is normal；Enter step S4；
If it is not, then corresponding to the frequency anomaly that reports an error for correcting mistake CE of PCIe device；Enter step S5；
S4. judge whether the applied voltage test time reaches setting time；
If it is not, return step S3；
If so, entering step S6；
S5. record can correct mistake the position of the PCIe device of the frequency anomaly that reports an error of CE, and enter step S6；
S6. test terminates, and outputs test result.
Embodiment 3:
The present embodiment is unlike implementation 2:
S31. the AER characteristic of each PCIe device is monitored, the frequency real value that reports an error that can correct mistake CE is obtained；Obtain CE
Report an error the time interval that reports an error in list, calculates the frequency real value that reports an error that can correct mistake CE；Specific step is as follows:
S311. the CE status register in the AER characteristic of each PCIe device is monitored, the CE status register includes not
Good TLP status register, bad DLLP status register, rollover states register and replay timeout register；
S312. judge whether set occur in aforementioned four CE status register；
If so, CE of record reports an error to CE and reports an error list；The CE status register of set is emptied, is entered step
S313；
If it is not, then entering step S313；
S313. judge whether poll time setting value reaches；Poll time setting value takes 10s；
If so, return step S311；
If it is not, then return step S313.The CE Status register in AER Capability is monitored, Bad is paid close attention to
TLP, Bad DLLP, Replay_num Rollover, Replay Timer Timeout, any 1 of above-mentioned 4 register-bits
There is set in position, then illustrates corresponding CE mistake occurred, then then one mistake of time point record (is recorded and reports an error
In list)；Later, which is carried out writing 1 clear 0, which is emptied, is persistently monitored.Monitoring is by the way of poll, often
10s poll is primary.
Embodiment 4:
As shown in figure 4, the present embodiment is unlike implementation 2:
S13. the frequency threshold that reports an error for correcting mistake CE that each PCIe device allows is generated；Specific step is as follows:
S131. the value for reading the connection status register of each PCIe device obtains the connection speed and band of PCIe device
It is wide；
S132. the frequency that reports an error that can correct mistake CE is calculated according to the connection speed and bandwidth meter of the bit error rate and PCIe device
Rate threshold value.
Although by reference to attached drawing and combining the mode of preferred embodiment to the present invention have been described in detail, the present invention
It is not limited to this.Without departing from the spirit and substance of the premise in the present invention, those of ordinary skill in the art can be to the present invention
Embodiment carry out various equivalent modifications or substitutions, and these modifications or substitutions all should in covering scope of the invention/appoint
What those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, answer
It is included within the scope of the present invention.Therefore, protection scope of the present invention is answered described is with scope of protection of the claims
It is quasi-.
Claims (10)
1. a kind of method for improving server PCIe device job stability, which comprises the steps of:
S1. server PCIe device topology List is established；
S2. applied voltage test is carried out to the PCIe device in server PCIe device topology List；
S3. the AER characteristic of PCIe device is monitored, whether the frequency that reports an error that judgement can wherein correct mistake CE is normal；
If so, entering step S4；
If it is not, entering step S5；
S4. judge whether the applied voltage test time reaches setting time；
If it is not, return step S3；
If so, entering step S6；
S5. record can correct mistake the position of the PCIe device of the frequency anomaly that reports an error of CE, and enter step S6；
S6. test terminates, and outputs test result.
2. improving the method for server PCIe device job stability as described in claim 1, which is characterized in that step S1 tool
Steps are as follows for body:
S11. the topological structure of PCIe device is obtained by lspci order；
S12. all PCIe devices of AER characteristic will be supported to generate a PCIe device list, PCIe device list is with each
Bus, device name and the function of PCIe device are index.
3. improving the method for server PCIe device job stability as claimed in claim 2, which is characterized in that in step S1
Further include following steps:
S13. the frequency threshold that reports an error for correcting mistake CE that each PCIe device allows is generated.
4. improving the method for server PCIe device job stability as claimed in claim 3, which is characterized in that step S3's
Specific step is as follows:
S31. the AER characteristic of each PCIe device is monitored, the frequency real value that reports an error that can correct mistake CE is obtained；
S32. the frequency real value that reports an error for correcting mistake CE of more each PCIe device corrects mistake CE's with what is allowed
Report an error frequency threshold；
Whether the frequency real value that reports an error that S33. judgement can correct mistake CE is less than the frequency that reports an error for correcting mistake CE of permission
Threshold value；
If so, the frequency that reports an error for correcting mistake CE of corresponding PCIe device is normal；
If it is not, then corresponding to the frequency anomaly that reports an error for correcting mistake CE of PCIe device.
5. improving the method for server PCIe device job stability as claimed in claim 4, which is characterized in that S31 is specific
Steps are as follows:
S311. the CE status register in the AER characteristic of each PCIe device is monitored, the CE status register includes bad
TLP status register, bad DLLP status register, rollover states register and replay timeout register；
S312. judge whether set occur in aforementioned four CE status register；
If so, CE of record reports an error to CE and reports an error list；The CE status register of set is emptied, S313 is entered step；
If it is not, then entering step S313；
S313. judge whether poll time setting value reaches；
If so, return step S311；
If it is not, then return step S313.
6. improving the method for server PCIe device job stability as claimed in claim 5, which is characterized in that poll time
Setting value takes 10s.
7. improving the method for server PCIe device job stability as claimed in claim 5, which is characterized in that in S31, obtain
It takes CE to report an error the time interval that reports an error in list, calculates the frequency real value that reports an error that can correct mistake CE.
8. improving the method for server PCIe device job stability as claimed in claim 3, which is characterized in that step S13
Specific step is as follows:
S131. the value for reading the connection status register of each PCIe device obtains the connection speed and bandwidth of PCIe device；
S132. the frequency threshold that reports an error that can correct mistake CE is calculated according to the connection speed and bandwidth meter of the bit error rate and PCIe device
Value.
9. improving the method for server PCIe device job stability as claimed in claim 8, which is characterized in that the error code
The value of rate takes 10-13。
10. improving the method for server PCIe device job stability as described in claim 1, which is characterized in that step S6
In, if the frequency that reports an error is normal, exports test and pass through；
If reporting an error frequency anomaly, exports test and do not pass through, record bus, device name and the function of the position that reports an error, and notify
Maintenance personal's maintenance.
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| CN201910631232.XA CN110489298B (en) | 2019-07-12 | 2019-07-12 | Method for improving working stability of PCIe (peripheral component interface express) equipment of server |
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| CN201910631232.XA CN110489298B (en) | 2019-07-12 | 2019-07-12 | Method for improving working stability of PCIe (peripheral component interface express) equipment of server |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107832179A (en) * | 2017-11-27 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of PCIe Error Enabling method of testings |
| CN109542669A (en) * | 2018-11-28 | 2019-03-29 | 郑州云海信息技术有限公司 | A kind of detection method and device of PCIe network interface card error message |
| CN109710501A (en) * | 2018-12-18 | 2019-05-03 | 郑州云海信息技术有限公司 | A kind of detection method and system of server data transport stability |
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2019
- 2019-07-12 CN CN201910631232.XA patent/CN110489298B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107832179A (en) * | 2017-11-27 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of PCIe Error Enabling method of testings |
| CN109542669A (en) * | 2018-11-28 | 2019-03-29 | 郑州云海信息技术有限公司 | A kind of detection method and device of PCIe network interface card error message |
| CN109710501A (en) * | 2018-12-18 | 2019-05-03 | 郑州云海信息技术有限公司 | A kind of detection method and system of server data transport stability |
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