CN110474711A - Coding method, equipment and readable storage medium storing program for executing - Google Patents
Coding method, equipment and readable storage medium storing program for executing Download PDFInfo
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- CN110474711A CN110474711A CN201810451087.2A CN201810451087A CN110474711A CN 110474711 A CN110474711 A CN 110474711A CN 201810451087 A CN201810451087 A CN 201810451087A CN 110474711 A CN110474711 A CN 110474711A
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- bit stream
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- logical value
- certain bits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
Abstract
The invention discloses a kind of coding methods, this method comprises: the first bit stream is obtained, wherein the first bit stream is 8 bit streams；Quality estimation is carried out to the first bit stream；Wherein, if the first bit stream meets at least one of the following conditions, determine that the first bit stream is unsatisfactory for quality standard: the 4th to the 7th logical value in the first bit stream is identical；The 1st to the 6th logical value in first bit stream is identical；The 0th to the 5th logical value in first bit stream is identical；The 6th in first bit stream is identical with the 7th logical value, and the 0th to the 4th logical value is identical, and opposite with the logical value of the 6th and the 7th.The invention also discloses a kind of code device and readable storage medium storing program for executing.By the above-mentioned means, the present invention can ensure the coding quality of third bit stream.
Description
Technical field
The present invention relates to field of data transmission, more particularly to a kind of coding method, equipment and readable storage medium storing program for executing.
Background technique
In serial data transmission, the data of transmission can be encoded into include clock frequency component code stream so that
Receiving end can extract clock synchronization information from code stream, clock synchronization information can guarantee receiving end according to correct timing from
Initial data is regenerated in the signal received.
4B5B is commonly to encode, and is exported after 4 data of input are converted to 5.It is generally designed using searching
Code table completes coding and work decoding, therefore transmitting terminal and receiving end require additional memory to store code table.4B5B
Coding is also possible to reduce coding quality, i.e. the identical continuous bit quantity of logical value is excessive, such as is using 4B5B coding transmission 8
When data.Low-quality coding is unfavorable for receiving end and extracts clock synchronization information, and brings biggish DC component, improves and misses
Code rate.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of coding method, equipment and readable storage medium storing program for executing, can solve
The problem of coding certainly in the prior art may be decreased coding quality.
In order to solve the above-mentioned technical problems, the present invention provides a kind of coding methods, this method comprises: obtaining the first bit
Stream, wherein the first bit stream is 8 bit streams；Quality estimation is carried out to the first bit stream；Wherein, if the first bit stream meet with
At least one of lower condition then determines that the first bit stream is unsatisfactory for quality standard: the 4th to the 7th in the first bit stream
Logical value it is identical；The 1st to the 6th logical value in first bit stream is identical；The 0th to the 5th in first bit stream
The logical value of position is identical；The 6th in first bit stream is identical with the 7th logical value, the 0th to the 4th logical value phase
Together, and it is opposite with the logical value of the 6th and the 7th.
In order to solve the above-mentioned technical problems, the present invention provides a kind of code device, which includes processor, processor
For executing instruction to realize method above-mentioned.
In order to solve the above-mentioned technical problems, the present invention provides a kind of readable storage medium storing program for executing, are stored with instruction, and instruction is held
Method above-mentioned is realized when row.
The beneficial effects of the present invention are: first judging whether the first bit stream meets preset quality mark in an encoding process
Standard converts the first bit stream for being unsatisfactory for quality standard, and exports the second bit stream, then by described the first of output
Bit stream or second bit stream are combined with marker, to form third bit stream, the second bit stream phase after conversion
Than being improved in the coding quality of the first bit stream, the coding quality of third bit stream is protected.
Detailed description of the invention
Fig. 1 is the flow diagram of one embodiment of coding method of the present invention；
Fig. 2 is the idiographic flow schematic diagram of S3 in Fig. 1 in one specific embodiment of coding method of the present invention；
Fig. 3 is the idiographic flow schematic diagram of S3 in Fig. 1 in coding method still another embodiment of the present invention；
Fig. 4 is the idiographic flow schematic diagram of S4 in Fig. 1 in coding method still another embodiment of the present invention；
Fig. 5 is the flow diagram of coding method still another embodiment of the present invention；
Fig. 6 is the flow diagram of coding method still another embodiment of the present invention；
Fig. 7 is the flow diagram of coding method still another embodiment of the present invention；
Fig. 8 is the flow diagram of coding method still another embodiment of the present invention；
Fig. 9 is the structural schematic diagram of one embodiment of encoding device of the present invention；
Figure 10 is the structural schematic diagram of one embodiment of readable storage medium storing program for executing of the present invention.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawings and examples.What is do not conflicted in following embodiment can phase
Mutually combine.
As shown in Figure 1, one embodiment of coding method of the present invention includes:
S1: Quality estimation is carried out to the first bit stream.
First bit stream can be un-encoded data, digit can depending on actual transmissions demand, such as 8
Position, 16 etc..Quality estimation can be to judge whether the quality of the first bit stream meets preset quality standard.The quality standard
Can continuous position identical with logical value in the first bit stream it is related.In general, meet in the first bit stream of quality standard
The identical continuous digit of logical value be no more than a threshold value, the size of the threshold value can be related to the digit of the first bit stream, example
As the half of the digit of the first bit stream adds a positive integer.
In the case that first bit stream is 8 bit streams in a specific embodiment of the invention, if the first bit stream meets
At least one of the following conditions a, b, c and d then determine that the first bit stream is unsatisfactory for quality standard:
A. the 4th to the 7th logical value in the first bit stream is identical；
B. the 1st to the 6th logical value in the first bit stream is identical；
C. the 0th to the 5th logical value in the first bit stream is identical；
D. the 6th in the first bit stream is identical with the 7th logical value, and the 0th to the 4th logical value is identical, and
It is opposite with the logical value of the 6th and the 7th.
Optionally, above-mentioned judgment mode can be converted to the judgement to following logical expression calculated result:
NAND (NAND (bm [4~7]), NAND (bm [1~6]), NAND (bm [0~5]), OR (NA ND (bm [6~7]),
OR (bm [0~4])), OR (OR (bm [6~7]), NAND (bm [0~4])), OR (bm [4~7]), OR (bm [1~6]), OR (bm
[0~5])) (1)
Wherein, NAND is NOT-AND operation, and OR is or operates, and bm [i~j] is the i-th bit of the first bit stream to jth position, i and
J is integer and i < j in 0 to 7.
In formula (1), when being 1 for the 4th to the 7th of the first bit stream, NAND (bm [4~7]) is 0.
When being 1 for the 1st to the 6th of the first bit stream, NAND (bm [1~6]) is 0.
When being 1 for the 0th to the 5th of the first bit stream, NAND (bm [0~5]) is 0.
When the 6th to the 7th of the first bit stream be 1 and first the 0th to the 4th of bit stream be 0 when, NAND
(bm [6~7]) be 0, OR (bm [0~4]) be 0, OR (NAND (bm [6~7]), OR (bm [0~4])) be 0.
When the 6th to the 7th of the first bit stream be 0 and first the 0th to the 4th of bit stream be 1 when, OR
(bm [6~7]) be 0, NAND (bm [0~4]) be 0, OR (OR (bm [6~7]), NAND (bm [0~4])) be 0.
When being 0 for the 4th to the 7th of the first bit stream, OR (bm [4~7]) is 0.
When being 0 for the 1st to the 6th of the first bit stream, OR (bm [1~6]) is 0.
When being 0 for the 0th to the 5th of the first bit stream, OR (bm [0~5]) is 0.
If the calculated result of formula (1) is 1, it is meant that NAND (bm [4~7]), NAND (bm [1~6]), NAND (bm [0~
5]), OR (NAND (bm [6~7]), OR (bm [0~4])), OR (OR (bm [6~7]), NAND (bm [0~4])), OR (bm [4~
7]), (bm [1~6]) OR, at least one of OR (bm [0~5]) are 0, and the condition for being 0 in conjunction with each logical formula above can
Meet at least one of condition a, b, c and d to obtain the first bit stream, then the first bit stream is unsatisfactory for quality standard.If formula
(1) calculated result is 0, then the first bit stream meets quality standard.
In the case that first bit stream is 8 bit streams in another specific embodiment of the present invention, if the first bit stream is same
When meet following all conditions e, f, g and h, then determine that the first bit stream meets quality standard:
E. at least two logical values in the 4th to the 7th in the first bit stream are different；
F. at least two logical values in the 1st to the 6th in the first bit stream are different；
G. at least two logical values in the 0th to the 5th in the first bit stream are different；
H. meet at least one of following sub- condition:
H1. the 6th in the first bit stream is different with the 7th logical value.
H2. the 0th to the 4th logical value in the first bit stream is different.
H3. the 6th in the first bit stream is identical with the 7th logical value, and the 0th to the 4th logical value is identical, and
It is identical as the logical value of the 6th and the 7th.
Optionally, above-mentioned judgment mode can be converted to the judgement to following logical expression calculated result:
AND (XOR (bm [4~7]), XOR (bm [1~6]), XOR (bm [0~5]), OR (NAND (bm [6~7]), OR (bm
[0~4])), OR (OR (bm [6~7]), NAND (bm [0~4]))) (2)
Wherein, AND be with operation, NAND is NOT-AND operation, and OR is or operates that XOR is xor operation；Bm [i-j] is the
For the i-th bit of one bit stream to jth position, i and j are integer and i < j in 0 to 7.
In formula (2), when different (i.e. wherein at least two logics of the 4th to the 7th logical value of the first bit stream
Value is different) when, XOR (bm [4~7]) is 1.
When the 1st to the 6th of the first bit stream logical value difference, XOR (bm [1~6]) is 1.
When the 0th to the 5th of the first bit stream logical value difference, XOR (bm [0~5]) is 1.
Bm [6~7] and bm [0~4] can combine discussion.
When the 6th of the first bit stream is different with the 7th logical value, NAND (bm [6~7]) and OR (bm [6~7])
Be 1, no matter the first bit stream the 0th to the 4th logical value it is whether identical, OR (NAND (bm [6~7]), OR (bm [0
~4])) and OR (OR (bm [6~7]), NAND (bm [0~4])) is 1.
When the 0th to the 4th of the first bit stream logical value difference, NAND (bm [0~4]) and OR (bm [0~4])
Be 1, no matter the first bit stream the 6th and the 7th logical value it is whether identical, OR (NAND (bm [6~7]), OR (bm [0
~4])) and OR (OR (bm [6~7]), NAND (bm [0~4])) is 1.
In the 6th identical with the 7th logical value and the first bit stream the 0th to the 4th of the first bit stream patrol
Collect in the identical situation of value: when being 0 for the first bit stream the 6th and the 7th, NAND (bm [6~7]) is 1, OR (NAND (bm
[6~7]), OR (bm [0~4])) it is 1, while OR (bm [6~7]) is 0, to meet OR (OR (bm [6~7]), NAND (bm [0
~4])) it should be 1 for 1, NAND (bm [0~4]), i.e. the 0th to the 4th of the first bit stream is 0；When the first bit stream the 6th
Position and the 7th be when being 1, and OR (bm [6~7]) is that 1, OR (OR (bm [6~7]), NAND (bm [0~4])) is 1, while NAND
(bm [6~7]) are 0, and to meet OR (NAND (bm [6~7]), OR (bm [0~4])) is that 1, OR (bm [0~4]) should be 1, i.e., the
The 0th to the 4th of one bit stream is 1.
If the calculated result of formula (2) is 1, it is meant that XOR (bm [4~7]), XOR (bm [1~6]), XOR (bm [0~5]),
OR (NAND (bm [6~7]), OR (bm [0~4])), OR (OR (bm [6~7]), NAND (bm [0~4])) is 1, in conjunction with previous
Available first bit stream of description of section meets all conditions e, f, g and h simultaneously, then the first bit stream meets quality standard.
If the calculated result of formula (2) is 0, the first bit stream is unsatisfactory for quality standard.
After Quality estimation, if the first bit stream meets quality standard, S2 is jumped to；If the first bit stream is unsatisfactory for
Quality standard then jumps to S3.
S2: the first bit stream of output.
In the case that first bit stream meets preset quality standard, the coding quality for improving the first bit stream is not needed,
It can directly export.
Jump to S4.
S3: converting the first bit stream, and exports the second bit stream.
The purpose of conversion is the coding quality in order to improve the first bit stream.In general, obtained after conversion second
Bit stream can satisfy preset quality standard.S4 is jumped to after exporting the second bit stream.
As shown in Fig. 2, this step can specifically include in a specific embodiment of the invention:
S31: logical operation is carried out to the first certain bits collection in the first bit stream.
The result of logical operation can be the first result or second as a result, the first result is different from the second result.
If logical operation result be first as a result, if jump to S32；If logical operation result be second as a result, if
Jump to S33.
S32: the second certain bits collection in the first bit stream is negated.
S33: the third certain bits collection in the first bit stream is negated.
It includes at least one that first certain bits collection, the second certain bits collection, third certain bits, which are concentrated,.In general, second is special
Positioning collection is different at least partly position that third certain bits are concentrated.
Completing the first bit stream after negating can be used as the output of the second bit stream.
For example, can be carried out to the 0th and the 1st in the first bit stream when the first bit stream is 8 bit streams
Xor operation.If the result of xor operation is 1, it is meant that the 0th in the first bit stream is different with the 1st, the first bit stream
In a high position in continuous multi-bit logical value it is identical a possibility that it is larger, then to the 4th, the 5th and the 7th in the first bit stream
It is negated；If the result of xor operation is 0, it is meant that the 0th in the first bit stream is identical with the 1st, the first bit stream
In low level in continuous multi-bit logical value it is identical a possibility that it is larger, then to the 0th, the 3rd, the 5th in the first bit stream
It is negated with the 6th.
As shown in figure 3, in still another embodiment of the present invention, this method may include:
S35: assignment is carried out to third bit stream using the first bit stream or the second bit stream.
S36: to special at least partly the first certain bits collection, the second certain bits collection or third in the third bit stream after assignment
Positioning collects corresponding position and carries out logical operation or negated.
The main distinction of the present embodiment embodiment corresponding with Fig. 2 is to have carried out logical operation to third bit stream or take
Inverse operations.Such as logical operation first can be carried out to the first certain bits collection in the first bit stream, then the first bit stream is assigned
It is worth and gives third bit stream, then third bit stream is negated.Or first to the first certain bits collection in the first bit stream into
Row logical operation, a part then concentrated to second/third certain bits in the first bit stream are negated to obtain the second ratio
Spy's stream, is then assigned to third bit stream for the second bit stream, then remain with second/third certain bits collection in third bit stream
The corresponding position of remaining part point is negated.In a kind of last situation, inversion operation is divided into two steps, respectively to the first bit stream and the
Three bit streams carry out.In other embodiments, inversion operation can also carry out the first bit stream and the second bit stream or the
One, second and third bit stream carry out.
For example, can be carried out to the 0th and the 1st in the first bit stream when the first bit stream is 8 bit streams
Xor operation.If the result of xor operation is 1, it is meant that the 0th in the first bit stream is different with the 1st, the first bit stream
In a high position in continuous multi-bit logical value it is identical a possibility that it is larger, then the 4th and the 7th in the first bit stream is taken
Instead；If the result of xor operation is 0, it is meant that the 0th in the first bit stream is identical with the 1st, low in the first bit stream
A possibility that continuously multi-bit logical value is identical in position is larger, then takes to the 0th, the 3rd and the 6th in the first bit stream
Instead.First bit stream obtains the second bit stream after negating for the first time, and the second bit stream is then assigned to third bit
Stream, then (no matter exclusive or, which is grasped, is negated to the 6th (the 5th be equivalent in first/second bit stream) in third bit stream
It is making the result is that 0 or 1).
S4: the first bit stream of output or the second bit stream are combined with marker, to form third bit stream.
The digit of marker can be 1, or more.Specifically, marker can be inserted directly into first/second
Before bit stream/in/after to form third bit stream, can also by at least partly position of first/second bit stream carry out logic fortune
It is inserted into marker after calculation, other combinations can also be used, herein with no restrictions.In general, marker and first/second
The combination of bit stream should not influence coding quality, i.e. third bit stream still meets preset quality standard.To realize this target,
The logical value of marker can be inserted into from it after adjacent bit (one or two) at least one logical value it is different.
For example, marker is inserted in front of the 0th of first/second bit stream, logical value and the first/second bit stream of marker
0th logical value is different.
As shown in figure 4, this step can specifically include in still another embodiment of the present invention:
S41: if output be the first bit stream, by the certain bits of the first bit stream in the way of the second assignment to mark
Marker and the first bit stream are simultaneously combined by position assignment；If output is the second bit stream, the second bit stream is utilized
Certain bits are combined in a manner of the first assignment to marker assignment, and by marker and the second bit stream.
Marker can be any position in first/second bit stream.In third bit stream after combination, marker can
It is adjacent with position corresponding with certain bits, it can also be non-conterminous.First assignment mode is different from the second assignment mode, to pass through mark
Position and certain bits can distinguish whether third bit stream carried out Mass adjust- ment.For example, the first assignment mode can be directly tax
One of be worth and negate assignment, the second assignment mode can be indirect assignment and negate the another kind in assignment.It receiving end can
Judge whether the third bit stream received passes through Mass adjust- ment with the exclusive or result by marker and certain bits, to select
Different decoding processes.
In practical application, the certain bits of first/second bit stream directly or after negating can be assigned to marker,
Can also be in such a way that other be equivalent, such as judge whether the logical value of certain bits is 0/1, according to judging result combine whether
It needs to negate the logical value of marker is arranged.
For example, if output is the first bit stream, it can patrolling the 0th (i.e. marker) of third bit stream
Volume value is equal to the negating as a result, wherein the 1st of third bit stream and subsequent bit are by first of the 0th of the first bit stream
The 0th of bit stream and subsequent bit progress assignment acquisition.Assignment and marker setting between sequence there is no restriction, can first by
0th result that negates of the first bit stream is assigned to marker, then again by the 0th of the first bit stream and subsequent bit assignment
To the 1st of third bit stream and subsequent bit；The 0th of the first bit stream and subsequent bit first can also be assigned to third bit
1st and subsequent bit of stream, then again by the 0th of the first bit stream the 1st 's for negating result or third bit stream
It negates result and is assigned to marker.
If output is the second bit stream, the logical value of the 0th (i.e. marker) of third bit stream can be arranged
For the 0th equal to the second bit stream, wherein the 1st of third bit stream and subsequent bit by the 0th of the second bit stream and after
Continuous position carries out assignment acquisition.There is no restriction for sequence between assignment and marker setting, can be first by the 0th of the second bit stream
It is assigned to marker, the 0th of the second bit stream and subsequent bit are then assigned to the 1st of third bit stream and subsequent again
Position；The 0th of second bit stream and subsequent bit can also be first assigned to the 1st and subsequent bit of third bit stream, then again
Marker is assigned to by the 1st of the 0th of the second bit stream or third bit stream.
In the above example, the logical value of marker be equal to the 0th of the first bit stream negate result or
Person is equal to the 0th of the second bit stream.Reality can also in turn, i.e. the logical value of marker is equal to the first bit stream
The 0th or negate result equal to the 0th of the second bit stream.
By the implementation of the present embodiment, first judge whether the first bit stream meets preset quality mark in an encoding process
Standard converts the first bit stream for being unsatisfactory for quality standard, and exports the second bit stream, then by the first bit of output
Stream or the second bit stream are combined with marker, and to form third bit stream, the second bit stream is compared to first after conversion
The coding quality of bit stream is improved, to ensure that the coding quality of third bit stream.
Complete cataloged procedure is illustrated with reference to the accompanying drawing.
As shown in figure 5, in still another embodiment of the present invention, coding method includes:
S101: the first bit stream bm [0~7] is obtained.
S102: whether the calculated result of decision logic expression formula (1) is 1.
==in figure indicates to be equal to ,=indicate assignment.
If the calculated result of logical expression (1) is 1, S103 is jumped to；If the calculated result of logical expression (1) is
0, then jump to S107.
S103: whether the calculated result for judging XOR (bm [0~1]) is 1.
If the calculated result of XOR (bm [0~1]) is 1, S104 is jumped to；If the calculated result of XOR (bm [0~1]) is
0, then jump to S105.
S104: bm [4] and bm [7] are negated.
Before bm [] or bn []~indicate to negate.
Remaining invariant position obtains the second bit stream, jumps to S106.
S105: bm [0], bm [3] and bm [6] are negated.
Remaining invariant position obtains the second bit stream, jumps to S106.
S106: being assigned to the 1st~8 of third bit stream for the second bit stream, to the 6th (bn of third bit stream
[6], equal to the 5th of the first and second bit streams) it negates, the 0th of third bit stream is assigned to by the 0th of the second bit stream
Position (bn [0] is marker).
Obtain third bit stream bn [0~8].
S107: the first bit stream is assigned to the 1st~8 of third bit stream.
S108: the result that negates of the 0th (equal to the 1st of third bit stream) of the first bit stream is assigned to third ratio
The 0th (i.e. marker) of spy's stream.
Obtain third bit stream bn [0~8].
As shown in fig. 6, in still another embodiment of the present invention, coding method includes:
S201: the first bit stream bm [0~7] is obtained.
S202: whether the calculated result of decision logic expression formula (2) is 1.
==in figure indicates to be equal to ,=indicate assignment.
If the calculated result of logical expression (2) is 1, S203 is jumped to；If the calculated result of logical expression (2) is
0, then jump to S207.
S203: the first bit stream is assigned to the 1st~8 of third bit stream.
S204: the result that negates of the 0th (equal to the 1st of third bit stream) of the first bit stream is assigned to third ratio
The 0th (i.e. marker) of spy's stream.
Obtain third bit stream bn [0~8].
S205: whether the calculated result for judging XOR (bm [0~1]) is 1.
If the calculated result of XOR (bm [0~1]) is 1, S206 is jumped to；If the calculated result of XOR (bm [0~1]) is
0, then jump to S207.
S206: bm [4] and bm [7] are negated.
Before bm [] or bn []~indicate to negate.
Remaining invariant position obtains the second bit stream, jumps to S208.
S207: bm [0], bm [3] and bm [6] are negated.
Remaining invariant position obtains the second bit stream, jumps to S208.
S208: being assigned to the 1st~8 of third bit stream for the second bit stream, to the 6th (bn of third bit stream
[6], equal to the 5th of the first and second bit streams) it negates, the 0th of third bit stream is assigned to by the 0th of the second bit stream
Position (bn [0] is marker).
Obtain third bit stream bn [0~8].
As shown in fig. 7, in still another embodiment of the present invention, coding method includes:
S301: the first bit stream bm [0~7] is obtained.
S302: whether the calculated result of decision logic expression formula (1) is 1.
==in figure indicates to be equal to ,=indicate assignment.
If the calculated result of logical expression (1) is 1, S303 is jumped to；If the calculated result of logical expression (1) is
0, then jump to S308.
S303: whether the calculated result for judging XOR (bm [0~1]) is 1.
If the calculated result of XOR (bm [0~1]) is 1, S304 is jumped to；If the calculated result of XOR (bm [0~1]) is
0, then jump to S305.
S304: bm [4] and bm [7] are negated.
Before bm [] or bn []~indicate to negate.
Jump to S306.
S305: bm [0], bm [3] and bm [6] are negated.
Jump to S306.
S306: bm [5] is negated.
Remaining invariant position obtains the second bit stream.
S307: by the 0th of the second bit stream the 0th (bn [0], for mark for negating result and being assigned to third bit stream
Know position), and the second bit stream is assigned to the 1st~8 of third bit stream.
Obtain third bit stream bn [0~8].
S308: the first bit stream is assigned to the 1st~8 of third bit stream.
S309: judge whether the 1st (equal to the 0th of the first bit stream) of third bit stream is 1.
If the 1st of third bit stream is 1, S310 is jumped to；If the 1st of third bit stream is 0, jump to
S311。
S310: 1 is set as by the 0th (i.e. marker) of third bit stream.
Obtain third bit stream bn [0~8].
S311: 0 is set as by the 0th (i.e. marker) of third bit stream.
Obtain third bit stream bn [0~8].
As shown in figure 8, in still another embodiment of the present invention, coding method includes:
S401: the first bit stream bm [0~7] is obtained.
==in figure indicates to be equal to ,=indicate assignment.
S402: whether the calculated result of decision logic expression formula (1) is 1.
If the calculated result of logical expression (1) is 1, S403 is jumped to；If the calculated result of logical expression (1) is
0, then jump to S407.
S403: whether the calculated result for judging XOR (bm [0~1]) is 1.
If the calculated result of XOR (bm [0~1]) is 1, S404 is jumped to；If the calculated result of XOR (bm [0~1]) is
0, then jump to S405.
S404: bm [4], bm [5] and bm [7] are negated.
Before bm [] or bn []~indicate to negate.
Remaining invariant position obtains the second bit stream, jumps to S406.
S405: bm [0], bm [3], bm [5] and bm [6] are negated.
Remaining invariant position obtains the second bit stream, jumps to S406.
S406: by the 0th of the second bit stream the 0th (bn [0], for mark for negating result and being assigned to third bit stream
Know position), and the second bit stream is assigned to the 1st~8 of third bit stream.
Obtain third bit stream bn [0~8].
S407: the first bit stream is assigned to the 1st~8 of third bit stream.
S408: judge whether the 1st (equal to the 0th of the first bit stream) of third bit stream is 1.
If the 1st of third bit stream is 1, S409 is jumped to；If the 1st of third bit stream is 0, jump to
S410。
S409: 1 is set as by the 0th (i.e. marker) of third bit stream.
Obtain third bit stream bn [0~8].
S410: 0 is set as by the 0th (i.e. marker) of third bit stream.
Obtain third bit stream bn [0~8].
As shown in figure 9, one embodiment of encoding device of the present invention includes: processor 110.In addition to this, encoding device may be used also
To include memory (being not drawn into figure).
Processor 110 controls the operation of encoding device, and processor 110 can also be known as CPU (Central Processing
Unit, central processing unit).Processor 110 may be a kind of IC chip, the processing capacity with signal sequence.Place
Reason device 110 can also be general processor, digital signal sequences processor (DSP), specific integrated circuit (ASIC), ready-made compile
Journey gate array (FPGA) either other programmable logic device, discrete gate or transistor logic, discrete hardware components.It is logical
It can be microprocessor with processor or the processor be also possible to any conventional processor etc..
Processor 110 realizes that coding method any embodiment of the present invention and possible combination are provided for executing instruction
Method.
As shown in Figure 10, one embodiment of readable storage medium storing program for executing of the present invention includes memory 210, and memory 210 is stored with finger
It enables, which, which is performed, realizes method provided by coding method any embodiment of the present invention and possible combination.
Memory 210 may include read-only memory (ROM, Read-Only Memory), random access memory (RAM,
Random Access Memory), flash memory (Flash Memory), hard disk, CD etc..
In several embodiments provided by the present invention, it should be understood that disclosed method and apparatus can pass through it
Its mode is realized.For example, device embodiments described above are only schematical, for example, the module or unit
Division, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or group
Part can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown
Or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit it is indirect
Coupling or communication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.Some or all of unit therein can be selected to realize present embodiment scheme according to the actual needs
Purpose.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that the independent physics of each unit includes, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
It is each that equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute the present invention
The all or part of the steps of embodiment the method.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory
(ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic or disk
Etc. the various media that can store program code.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (13)
1. a kind of coding method, which is characterized in that the described method includes:
The first bit stream is obtained, wherein first bit stream is 8 bit streams；
Quality estimation is carried out to the first bit stream；
Wherein, if first bit stream meets at least one of the following conditions, determine that first bit stream is unsatisfactory for
The quality standard:
The 4th to the 7th logical value in first bit stream is identical；
The 1st to the 6th logical value in first bit stream is identical；
The 0th to the 5th logical value in first bit stream is identical；
The 6th in first bit stream is identical with the 7th logical value, and the 0th to the 4th logical value is identical, and with
Described 6th and the 7th logical value is opposite.
2. the method according to claim 1, wherein the step of carrying out Quality estimation to the first bit stream packet
It includes:
If the calculated result of following logical expression is equal to 1, first bit stream is unsatisfactory for the quality standard:
NAND (NAND (bm [4~7]), NAND (bm [1~6]), NAND (bm [0~5]), OR (NAND (bm [6~7]), OR (bm
[0~4])), OR (OR (bm [6~7]), NAND (bm [0~4])), OR (bm [4~7]), OR (bm [1~6]), OR (bm [0~
5]))
Wherein, NAND is NOT-AND operation, and OR is or operates, and bm [i-j] is the i-th bit of first bit stream to jth position.
3. according to the method described in claim 2, it is characterized in that, the method further includes:
If first bit stream meets preset quality standard, first bit stream is exported；
If first bit stream is unsatisfactory for preset quality standard, first bit stream is converted, and exports the
Two bit streams；
First bit stream of output or second bit stream are combined with marker, to form third bit stream.
4. according to the method described in claim 3, it is characterized in that, described convert first bit stream, and exporting
The step of second bit stream includes:
Logical operation is carried out to the first certain bits collection in first bit stream；
If the logical operation result be first as a result, if the second certain bits collection in first bit stream is taken
Instead；
If the logical operation result be second as a result, if the third certain bits collection in first bit stream is taken
Instead.
5. according to the method described in claim 4, it is characterized in that, the method further includes:
Assignment is carried out to the third bit stream using first bit stream or the second bit stream；
It is the step of wherein first certain bits collection in first bit stream carries out logical operation, described to described first
The step of the second certain bits collection in bit stream is negated or the third certain bits collection in first bit stream
The step of being negated include:
To in the third bit stream after assignment at least partly described first certain bits collection, the second certain bits collection or institute
The corresponding position of third certain bits collection is stated to carry out logical operation or negated.
6. according to the method described in claim 4, it is characterized in that, described convert first bit stream, and exporting
The step of second bit stream includes:
To the 0th and the 1st progress xor operation in first bit stream；
If the result of xor operation is 1, the 4th, the 5th and the 7th in first bit stream is negated；
If the result of xor operation is 0, the 0th, the 3rd, the 5th and the 6th in first bit stream is taken
Instead.
7. according to the method described in claim 6, it is characterized in that, the method further includes:
Assignment is carried out to the 1st of the third bit stream and subsequent bit using the 0th of second bit stream and subsequent bit；
Wherein, negate to the 0th, the 3rd, the 4th, the 6th, the 7th in first bit stream is for described
First bit stream is operated, and negate to the 5th in first bit stream is in the third bit stream
6th is operated.
8. according to the method described in claim 3, it is characterized in that, described by first bit stream of output or described second
The step of bit stream is combined with marker include:
If output be second bit stream, by the certain bits of second bit stream in the way of the first assignment to described
Marker assignment, and the marker and second bit stream are combined；
If output be first bit stream, by the certain bits of first bit stream in the way of the second assignment to described
The marker and first bit stream are simultaneously combined by marker assignment；
Wherein the first assignment mode is different from the second assignment mode, to pass through the marker and the certain bits energy
Enough distinguish whether the third bit stream carried out Mass adjust- ment.
9. according to the method described in claim 8, it is characterized in that, the first assignment mode is indirect assignment and negates assignment
One of, the second assignment mode is indirect assignment and negates the another kind in assignment.
If 10. according to the method described in claim 9, it is characterized in that, it is described output be second bit stream, utilize
The certain bits of second bit stream include: to the step of marker assignment in a manner of the first assignment
0th logical value of the third bit stream is equal to the 0th of second bit stream, wherein described
The 1st of three bit streams and subsequent bit carries out conversion by the 0th of second bit stream and subsequent bit and assignment obtains.
If 11. according to the method described in claim 9, it is characterized in that, it is described output be first bit stream, utilize
The certain bits of first bit stream include: to the step of marker assignment in a manner of the second assignment
By the 0th logical value of the third bit stream be equal to the 0th of first bit stream negate as a result,
Wherein the 1st of the third bit stream and subsequent bit carry out assignment acquisition by the 0th of first bit stream and subsequent bit.
12. a kind of encoding device, which is characterized in that including processor, the processor is for executing instruction to realize such as right
It is required that method described in any one of 1-11.
13. a kind of readable storage medium storing program for executing is stored with instruction, which is characterized in that described instruction is performed realization such as claim
Method described in any one of 1-11.
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| CN113438051A (en) * | 2021-06-11 | 2021-09-24 | Tcl华星光电技术有限公司 | Encoding method, encoding device, and storage medium |
| CN113630211A (en) * | 2021-07-27 | 2021-11-09 | Tcl华星光电技术有限公司 | Encoding method and storage medium |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112947875B (en) * | 2021-01-28 | 2023-02-07 | Tcl华星光电技术有限公司 | Data encoding method, data encoding device, storage medium and computer equipment |
| CN113347428B (en) * | 2021-05-26 | 2023-01-24 | Tcl华星光电技术有限公司 | Decoding method and decoding device |
| CN113438050B (en) * | 2021-06-03 | 2022-08-23 | Tcl华星光电技术有限公司 | Encoding method, decoding method, encoding device and decoding device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63245147A (en) * | 1987-03-31 | 1988-10-12 | Nec Home Electronics Ltd | Repeater |
| CN1294820A (en) * | 1999-02-09 | 2001-05-09 | 索尼公司 | Coding system and its method, coding device and its method decoding device and its method, recording device and its method, and reproducing device and its method |
| CN1339922A (en) * | 2000-08-18 | 2002-03-13 | 株式会社媒体糊 | Separating and merging device, method for coding signal and computer program product |
| US20020073136A1 (en) * | 2000-12-07 | 2002-06-13 | Tomoaki Itoh | Data reproduction method, data receiving terminal and data receiving method |
| EP1560389A1 (en) * | 2004-01-30 | 2005-08-03 | Alcatel Alsthom Compagnie Generale D'electricite | Method and receiver for optical or electromagnetic signals with iterative equalization and error correction |
| CN102497249A (en) * | 2011-10-07 | 2012-06-13 | 友达光电股份有限公司 | Encoding method, encoding device, decoding method, decoding device, data transmission device, and data reception device |
| CN103368582A (en) * | 2012-04-11 | 2013-10-23 | 联咏科技股份有限公司 | Data coding and decoding method and device |
| CN104052577A (en) * | 2014-06-23 | 2014-09-17 | 硅谷数模半导体（北京）有限公司 | Signal transmission processing method and device and video data transmission method and system |
| GB2533412A (en) * | 2014-12-19 | 2016-06-22 | Blu Wireless Tech Ltd | Methods for wireless communications |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040151208A1 (en) * | 2003-01-31 | 2004-08-05 | Maupin Patrick E. | Parallel encoding/decoding for communications protocol |
| CN108768587B (en) * | 2018-05-11 | 2021-04-27 | Tcl华星光电技术有限公司 | Encoding method, apparatus and readable storage medium |
-
2018
- 2018-05-11 CN CN201810451087.2A patent/CN110474711B/en active Active
- 2018-09-26 WO PCT/CN2018/107463 patent/WO2019214139A1/en active Application Filing
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63245147A (en) * | 1987-03-31 | 1988-10-12 | Nec Home Electronics Ltd | Repeater |
| CN1294820A (en) * | 1999-02-09 | 2001-05-09 | 索尼公司 | Coding system and its method, coding device and its method decoding device and its method, recording device and its method, and reproducing device and its method |
| CN1339922A (en) * | 2000-08-18 | 2002-03-13 | 株式会社媒体糊 | Separating and merging device, method for coding signal and computer program product |
| US20020073136A1 (en) * | 2000-12-07 | 2002-06-13 | Tomoaki Itoh | Data reproduction method, data receiving terminal and data receiving method |
| EP1560389A1 (en) * | 2004-01-30 | 2005-08-03 | Alcatel Alsthom Compagnie Generale D'electricite | Method and receiver for optical or electromagnetic signals with iterative equalization and error correction |
| CN102497249A (en) * | 2011-10-07 | 2012-06-13 | 友达光电股份有限公司 | Encoding method, encoding device, decoding method, decoding device, data transmission device, and data reception device |
| CN103368582A (en) * | 2012-04-11 | 2013-10-23 | 联咏科技股份有限公司 | Data coding and decoding method and device |
| CN104052577A (en) * | 2014-06-23 | 2014-09-17 | 硅谷数模半导体（北京）有限公司 | Signal transmission processing method and device and video data transmission method and system |
| GB2533412A (en) * | 2014-12-19 | 2016-06-22 | Blu Wireless Tech Ltd | Methods for wireless communications |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113438051A (en) * | 2021-06-11 | 2021-09-24 | Tcl华星光电技术有限公司 | Encoding method, encoding device, and storage medium |
| CN113630211A (en) * | 2021-07-27 | 2021-11-09 | Tcl华星光电技术有限公司 | Encoding method and storage medium |
| CN113630211B (en) * | 2021-07-27 | 2023-05-02 | Tcl华星光电技术有限公司 | Encoding method and storage medium |
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| CN110474711B (en) | 2021-11-09 |
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