CN110459557B

CN110459557B - Chip wafer, preparation method thereof and Micro-LED display

Info

Publication number: CN110459557B
Application number: CN201910757851.3A
Authority: CN
Inventors: 杨涛; 强力; 宋吉鹏; 周天民; 黄睿; 尹东升; 李颖
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-08-16
Filing date: 2019-08-16
Publication date: 2022-06-24
Anticipated expiration: 2039-08-16
Also published as: CN110459557A

Abstract

The embodiment of the invention provides a chip wafer, a preparation method thereof and a Micro-LED display, relates to the technical field of display, and can detect whether an LED chip can emit light or not before the LED chip is transferred. The chip wafer includes: a substrate and a plurality of LED chips disposed on the substrate; the LED chip comprises a second semiconductor pattern, a light-emitting pattern and a first semiconductor pattern which are sequentially stacked and arranged on the substrate; the LED chip further includes a first electrode in contact with the first semiconductor pattern and a second electrode in contact with the second semiconductor pattern; the chip wafer further comprises a first signal line and a second signal line which are arranged on the substrate; the first signal line is used for providing electric signals for the first electrodes of the LED chips, the second electrodes are electrically connected with the second signal line, and the second signal line is used for providing electric signals for the second electrodes.

Description

Chip wafer, preparation method thereof and Micro-LED display

Technical Field

The invention relates to the technical field of display, in particular to a chip wafer, a preparation method of the chip wafer and a Micro-LED display.

Background

The Micro-LED (Micro-Light-Emitting Diode) display has the advantages of independent pixel control, self-luminescence, high brightness, wide color gamut, stable material performance, long service life and the like, and thus becomes the next-generation novel display technology with the greatest potential at present.

At present, the manufacturing process of a Micro-LED display mainly includes preparation and testing of a Micro LED chip, preparation of a receiving backplane (which may also be referred to as a circuit substrate), and transfer and binding of the Micro LED chip and the receiving backplane. Since the Micro LED chip may be damaged and may not emit light normally in the preparation process, and the Micro-LED display manufactured by transferring the LED chip to the receiving backplane may affect the display effect of the Micro-LED display, it is necessary to detect whether the LED chip emits light normally before transferring the LED chip to the receiving backplane.

Disclosure of Invention

The embodiment of the invention provides a chip wafer, a preparation method thereof and a Micro-LED display, which can detect whether an LED chip can emit light or not before the LED chip is transferred.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in a first aspect, a chip wafer is provided, which includes: a substrate and a plurality of LED chips disposed on the substrate; the LED chip comprises a second semiconductor pattern, a light-emitting pattern and a first semiconductor pattern which are sequentially stacked and arranged on the substrate; the LED chip further includes a first electrode in contact with the first semiconductor pattern and a second electrode in contact with the second semiconductor pattern; the chip wafer further comprises a first signal line and a second signal line which are arranged on the substrate; the first signal line is used for providing electric signals for the first electrodes of the LED chips, the second electrodes are electrically connected with the second signal line, and the second signal line is used for providing electric signals for the second electrodes.

In some embodiments, the chip wafer further comprises at least a scanning signal line, a data signal line and a plurality of control circuits; one of the control circuits corresponds to one of the LED chips; each control circuit is electrically connected with at least the scanning signal line, the data signal line, the first signal line and the first electrode, and at least under the control of signals on the scanning signal line and the data signal line, the first signal line is communicated with the first electrode so as to provide an electric signal for the first electrode.

In some embodiments, the control circuit includes a first transistor, a second transistor, and a storage capacitor; the grid electrode of the first transistor is electrically connected with the scanning signal line, the first pole of the first transistor is electrically connected with the data signal line, and the second pole of the first transistor is electrically connected with the grid electrode of the second transistor; a first pole of the second transistor is electrically connected with a first signal line, and a second pole of the second transistor is electrically connected with the first electrode of the LED chip; one end of the storage capacitor is electrically connected with the grid electrode of the second transistor, and the other end of the storage capacitor is electrically connected with the first signal line.

In some embodiments, the first semiconductor pattern is proximate to the substrate relative to the first transistor and the second transistor; the second electrode of the LED chip is shared with the second pole of the second transistor.

In some embodiments, the first electrodes of the plurality of LED chips are all electrically connected to the first signal line.

In some embodiments, the chip wafer further comprises a plurality of control switches; one of the control switches corresponds to one of the LED chips; each of the control switches includes at least one transistor.

In a second aspect, a method for manufacturing a chip wafer is provided, including: forming a plurality of LED chips, a first signal line, and a second signal line on a substrate; the LED chip comprises a second semiconductor pattern, a light emitting pattern and a first semiconductor pattern which are sequentially stacked and arranged on the substrate; the LED chip further includes a first electrode in contact with the first semiconductor pattern and a second electrode in contact with the second semiconductor pattern; the first signal line is used for providing electric signals for the first electrodes of the LED chips, the second electrodes are electrically connected with the second signal line, and the second signal line is used for providing electric signals for the second electrodes.

In some embodiments, the method for manufacturing a chip wafer further includes: forming at least a scanning signal line, a data signal line, and a plurality of control circuits on the substrate; one of the control circuits corresponds to one of the LED chips; each control circuit is electrically connected with at least the scanning signal line, the data signal line, the first signal line and the first electrode, and at least under the control of signals on the scanning signal line and the data signal line, the first signal line is communicated with the first electrode so as to provide an electric signal for the first electrode.

In some embodiments, before forming at least a scan signal line, a data signal line, and a plurality of control circuits on the substrate, the method for manufacturing a chip wafer further includes: forming an insulating layer on the first semiconductor pattern; forming a control circuit on the substrate, comprising: forming a first transistor, a second transistor, and a storage capacitor over the insulating layer; the grid electrode of the first transistor is electrically connected with the scanning signal line, the first pole of the first transistor is electrically connected with the data signal line, and the second pole of the first transistor is electrically connected with the grid electrode of the second transistor; a first pole of the second transistor is electrically connected with a first signal line, and a second pole of the second transistor is electrically connected with the first electrode of the LED chip; one end of the storage capacitor is electrically connected with the grid electrode of the second transistor, and the other end of the storage capacitor is electrically connected with the first signal line.

In some embodiments, after forming the first semiconductor pattern of the LED chip on the substrate, the method of manufacturing a chip wafer further includes: forming an insulating layer on the first semiconductor pattern; forming a plurality of control switches on the insulating layer; one of the control switches corresponds to one of the LED chips, and each of the control switches includes at least one transistor.

In a third aspect, a Micro-LED display is provided, which includes a receiving backplane and a plurality of light emitting units disposed on the receiving backplane, each of the light emitting units including an LED chip; the plurality of light-emitting units are obtained by cutting the chip wafer and transferring the chip wafer; the receiving backboard at least comprises a first signal line, a second signal line, a data signal line and a scanning signal line; the second electrodes of the LED chips are electrically connected with the second signal wires; the Micro-LED display further comprises: a plurality of control circuits; one of the control circuits corresponds to one of the LED chips; the control circuit communicates the first signal line with the first electrode at least under the control of signals on the scanning signal line and the data signal line so as to provide an electric signal for the first electrode; the control circuit comprises a plurality of transistors and a storage capacitor; the receiving backplane and/or the light emitting unit includes a plurality of the transistors and the storage capacitors.

The embodiment of the invention provides a chip wafer, a preparation method thereof and a Micro-LED display, wherein the chip wafer comprises a substrate and a plurality of LED chips arranged on the substrate, and each LED chip comprises a second semiconductor pattern, a light-emitting pattern and a first semiconductor pattern which are sequentially arranged on the substrate in a stacked mode; the LED chip further includes a first electrode in contact with the first semiconductor pattern and a second electrode in contact with the second semiconductor pattern. The chip wafer further comprises a first signal line and a second signal line which are arranged on the substrate; the first signal line is used for providing electric signals for the first electrodes of the LED chips, the second electrodes are electrically connected with the second signal line, and the second signal line is used for providing electric signals for the second electrodes. The first signal line can provide an electric signal for the first electrode, and the second signal line can provide an electric signal for the second electrode, so that whether the LED chip is damaged or not can be judged by detecting whether the LED chip emits light or not under the condition that the first signal line provides the electric signal for the first electrode and the second signal line provides the electric signal for the second electrode. If the LED chip does not emit light, the LED chip is damaged, namely the LED chip is unqualified; if the LED chip emits light, the LED chip is not damaged, namely the LED chip is qualified. Therefore, when the Micro-LED display is manufactured, only the LED chips which are not damaged are transferred, and the display effect of the Micro-LED display is ensured.

Compared with the prior art, whether the LED chip is damaged or not is detected through optical testing, and whether the LED chip is damaged or not is detected through electrical testing in the embodiment of the invention, so that effective and invalid LED chips can be screened reliably, the detection result is more accurate, and the risk of missed detection is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a first schematic structural diagram of a chip wafer according to an embodiment of the present invention;

fig. 2 is a second schematic structural diagram of a chip wafer according to an embodiment of the present invention;

fig. 3a is a schematic structural diagram of a chip wafer according to an embodiment of the present invention;

fig. 3b is a schematic structural diagram of a chip wafer according to an embodiment of the present invention;

fig. 4 is a first schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 5 is a second schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a chip wafer according to an embodiment of the present invention;

fig. 7 is a sixth schematic structural view of a chip wafer according to an embodiment of the present invention;

fig. 8 is a schematic flow chart illustrating a method for manufacturing a chip wafer according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of forming a second semiconductor layer, a light-emitting layer, and a first semiconductor layer on a substrate according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of forming a second semiconductor layer, a light-emitting layer, a first semiconductor layer, and a first electrode layer on a substrate according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram illustrating a second semiconductor pattern, a light emitting pattern, and a first semiconductor pattern formed on a substrate according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram illustrating a second semiconductor pattern, a light emitting pattern, a first semiconductor pattern, and a first electrode formed on a substrate according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram illustrating a structure of removing portions of the light-emitting pattern, the first semiconductor pattern, and the first electrode to expose the second semiconductor pattern according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram illustrating an insulating layer formed on a first electrode according to an embodiment of the present invention;

FIG. 15 is a schematic diagram illustrating a structure of an active layer formed on an insulating layer according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram illustrating a gate insulating layer and a gate electrode formed on an active layer according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of an embodiment of an interlayer dielectric layer formed on a gate electrode;

fig. 18 is a schematic structural diagram illustrating a first electrode, a second electrode, a gate connecting terminal, a first electrode connecting terminal, and a second electrode formed on an interlayer defining layer according to an embodiment of the present invention;

fig. 19 is a schematic structural diagram of a method for forming a plurality of independent light-emitting units on a substrate according to an embodiment of the present invention;

fig. 20 is a first schematic structural diagram of a receiving backplane according to an embodiment of the present invention;

fig. 21 is a second schematic structural diagram of a receiving backplane according to an embodiment of the present invention;

fig. 22 is a schematic structural diagram of transferring an LED chip onto a receiving backplane by using a transferring device according to an embodiment of the present invention.

Reference numerals:

01-an electrical test area; 02-a control circuit; 10-a substrate; 20-an LED chip; 201-a first semiconductor pattern; 2011-first semiconductor layer; 202-a light emitting pattern; 2021-a light emitting layer; 203-a second semiconductor pattern; 2031 — a second semiconductor layer; 204-a first electrode; 2041 — a first electrode layer; 205-a second electrode; 30-a first signal line; 40-a second signal line; 50-an insulating layer; 60-a transistor; 601-an active layer; 602-a gate insulating layer; 603-a gate; 604-interlayer definition layer; 605-a first pole; 606-second pole; 70-an interlayer-defining layer; 701-a first conductive terminal; 702-a second conductive terminal; 703-a third conductive terminal; 704-a fourth conducting terminal; 80-a receiving backplane; 801-conductive terminals; 90-transfer device.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a chip wafer, as shown in fig. 1, including: a substrate 10, and a plurality of LED chips 20 disposed on the substrate 10.

The LED chip 20 includes a second semiconductor pattern 203, a light emitting pattern 202, and a first semiconductor pattern 201 sequentially stacked and disposed on the substrate 10; the LED chip 20 further includes a first electrode 204 in contact with the first semiconductor pattern 201 and a second electrode 205 in contact with the second semiconductor pattern 203. The chip wafer further includes a first signal line 30 and a second signal line 40 disposed on the substrate 10; the first signal line 30 is used for providing an electrical signal to the first electrodes 204 of the plurality of LED chips 20, the second electrodes 205 are electrically connected to the second signal line 40, and the second signal line 40 is used for providing an electrical signal to the second electrodes 205.

Referring to fig. 1, an insulating layer 50 may be disposed between the first and

second signal lines

30 and 40 and the first semiconductor pattern 201. In order to facilitate the electrical connection of the second electrode 205 with the second signal line 40, in some embodiments, as shown in fig. 1, the second electrode 205 is located on a side of the insulating layer 50 away from the substrate 10, and the second electrode 205 contacts the second semiconductor pattern 203 through a via hole on the insulating layer 50.

Here, the substrate 10 is not limited to the case where the first semiconductor pattern 201, the light emitting pattern 202, and the second semiconductor pattern 203 can be grown on the substrate 10. By way of example, the substrate 10 may be an alumina substrate, a silicon substrate, or a sapphire substrate.

In some embodiments, the first semiconductor pattern 201 is a p-type semiconductor pattern and the second semiconductor pattern 203 is an n-type semiconductor pattern. In other embodiments, the first semiconductor pattern 201 is an n-type semiconductor pattern and the second semiconductor pattern 203 is a p-type semiconductor pattern. In addition, the material of the first semiconductor pattern 201 and the material of the second semiconductor pattern 203 are not limited, and the material of the first semiconductor pattern 201 and the material of the second semiconductor pattern 203 are exemplified by GaN (gallium nitride).

On this basis, an electrode in contact with the p-type semiconductor pattern of the first electrode 204 and the second electrode 205 is a p-electrode, and an electrode in contact with the n-type semiconductor pattern is an n-electrode.

In some embodiments, the light emitting pattern 202 is a quantum well layer. The material of the light emitting pattern 202 is not limited, and the material of the light emitting pattern 202 is GaN, for example.

In some embodiments, the voltage on the first signal line 30 is greater than the voltage on the second signal line 40, in which case the first signal line 30 may be referred to as the VDD signal line and the second signal line 40 may be referred to as the Vref signal line. In other embodiments, the voltage on the second signal line 40 is greater than the voltage on the first signal line 30, in which case the second signal line 40 may be referred to as the VDD signal line and the first signal line 30 may be referred to as the Vref signal line. In the embodiment of the present invention, the first signal line 30 is taken as a VDD signal line, and the second signal line 40 is taken as a Vref signal line for illustration.

It should be understood by those skilled in the art that since the first signal line 30 can provide the first electrode 204 with an electrical signal and the second signal line 40 can provide the second electrode 205 with an electrical signal, the LED chip 20 can emit light if the LED chip 20 is not damaged in the case where the first signal line 30 provides the first electrode 204 with an electrical signal and the second signal line 40 provides the second electrode 205 with an electrical signal.

In addition, as shown in fig. 2, in the embodiment of the present invention, an electrical test area 01 may be disposed at an edge of the substrate 10, signal lines in the chip wafer, such as the first signal line 30 and the second signal line 40, extend to the electrical test area 01, and a test signal is input to the first signal line 30 and the second signal line 40 located in the electrical test area 01 by an electrical test device to detect whether the LED chip 20 is damaged.

The embodiment of the present invention may include one first signal line 30, or may include a plurality of first signal lines 30. The embodiment of the present invention may include one second signal line 40, or may include a plurality of second signal lines 40. In the case where the embodiment of the present invention includes the plurality of first signal lines 30 and the plurality of second signal lines 40, as shown in fig. 2, the plurality of first signal lines 30 are parallel to each other, the plurality of second signal lines 40 are parallel to each other, and the first signal lines 30 and the second signal lines 40 cross each other.

In the embodiment of the present invention, the LED chips 20 may all emit white light, or may emit three primary colors of light, such as red light, green light, and blue light, and one LED chip 20 emits light of one color.

In the related art, when the array of LED chips 20 is formed on the substrate 10, since only the LED chips 20 are formed on the substrate 10 and no signal line is provided, it is impossible to electrically test the plurality of LED chips 20 on the substrate 10 to determine whether the LED chips 20 are damaged during the manufacturing process. Thus, if the damaged LED chip 20 is transferred to the receiving backplane to manufacture the Micro-LED display, the display effect of the Micro-LED display is affected. In order to solve this problem, the related art tests whether the LED chip 20 is damaged by optical detection, however, the optical detection reliability is low, and there is a high risk of missing detection, that is, the failed or damaged LED chip 20 may show normal under optical detection.

The embodiment of the invention provides a chip wafer, which comprises a substrate 10 and a plurality of LED chips 20 arranged on the substrate 10, wherein each LED chip 20 comprises a second semiconductor pattern 203, a light-emitting pattern 202 and a first semiconductor pattern 201 which are sequentially stacked on the substrate 10; the LED chip 20 further includes a first electrode 204 in contact with the first semiconductor pattern 201 and a second electrode 205 in contact with the second semiconductor pattern 203. The chip wafer further includes a first signal line 30 and a second signal line 40 disposed on the substrate 10; the first signal line 30 is used for providing an electrical signal to the first electrodes 204 of the plurality of LED chips 20, the second electrodes 205 are electrically connected to the second signal line 40, and the second signal line 40 is used for providing an electrical signal to the second electrodes 205. Since the first signal line 30 can provide an electrical signal to the first electrode 204 and the second signal line 40 can provide an electrical signal to the second electrode 205, in the case where the first signal line 30 provides an electrical signal to the first electrode 204 and the second signal line 40 provides an electrical signal to the second electrode 205, by detecting whether the LED chip 20 emits light, it can be determined whether the LED chip 20 is damaged. If the LED chip 20 does not emit light, the LED chip 20 is damaged, i.e., the LED chip 20 is not qualified; if the LED chip 20 emits light, the LED chip 20 is not damaged, i.e., the LED chip 20 is qualified. Therefore, when the Micro-LED display is manufactured, only the undamaged LED chips 20 are transferred, and the display effect of the Micro-LED display is ensured.

Compared with the prior art, whether the LED chip 20 is damaged or not is detected through optical testing, and whether the LED chip 20 is damaged or not is detected through electrical testing in the embodiment of the invention, so that the effective and ineffective LED chips 20 can be screened reliably, the detection result is more accurate, and the risk of missed detection is avoided.

Based on the above, before transferring the LED chips 20 to the receiving backplane, the chip wafer needs to be diced to form a plurality of independent LED chips 20. It should be understood by those skilled in the art that, in the process of cutting the chip wafer, since the first signal line 30 and the second signal line 40 are cut off, when the LED chip 20 is transferred to the receiving backplane to be bonded to a Micro-LED display, the manufactured first signal line 30 and second signal line 40 do not affect the normal display of the Micro-LED display.

The embodiment of the present invention provides the first electrode 204 with an electrical signal through the first signal line 30, and in some embodiments, the first electrodes 204 of the plurality of LED chips 20 are electrically connected to the first signal line 30. That is, the first electrodes 204 of the plurality of LED chips 20 are directly electrically connected to the first signal line 30. In other embodiments, the first electrodes 204 of the plurality of LED chips 20 are electrically connected to the first signal line 30 through a control circuit. That is, the first electrodes 204 of the plurality of LED chips 20 are indirectly electrically connected to the first signal line 30.

In the embodiment of the present invention, under the condition that the first electrodes 204 of the plurality of LED chips 20 are all electrically connected to the first signal line 30, the test signal is directly input to the first signal line 30 and the second signal line 40 at the same time, and if the LED chips 20 emit light, the LED chips 20 are not damaged; if the LED chip 20 does not emit light, the LED chip 20 is damaged. On this basis, compared with the related art, the chip wafer provided by the embodiment of the invention can detect the validity and the invalidity of the LED chip 20 by only adding the first signal line 30 and the second signal line 40, so that the chip wafer has a simple structure.

In the case where the first electrodes 204 of the plurality of LED chips 20 are all electrically connected to the first signal line 30, in some embodiments, as shown in fig. 3a and 3b, the chip wafer further includes a plurality of control switches; one control switch corresponds to one LED chip 20; each control switch includes at least one transistor 60.

Here, each control switch may be as shown in fig. 3a, comprising one transistor 60; two or more transistors 60 may also be included as shown in fig. 3 b. Fig. 3b illustrates an example in which the control switch comprises two transistors 60.

The transistor 60 may be a top gate transistor or a bottom gate transistor, and is not limited thereto. The transistor 60 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer, and both the source electrode and the drain electrode are in contact with the active layer.

The positional relationship between the transistor 60 and the LED chip 20 in the control switch is not limited, and in some embodiments, the transistor 60 and the LED chip 20 are stacked on the substrate 10, in which case, the transistor 60 may be close to the substrate 10 relative to the LED chip 20, or the LED chip 20 may be close to the substrate 10 relative to the transistor 60. In other embodiments, the transistor 60 and the LED chip 20 are disposed side-by-side on the substrate 10.

It should be understood that, since the chip wafer includes a control switch corresponding to each LED chip 20 in addition to the LED chips 20, a plurality of light emitting units are obtained after cutting the chip wafer, and each light emitting unit includes one LED chip 20 and one control switch.

The Micro-LED display includes a plurality of LED chips 20, and also includes a plurality of control circuits, one control circuit corresponding to one LED chip 20, and the control circuit is used to control the LED chip 20 corresponding thereto to emit light. The control circuit includes a plurality of transistors. In the related art, a plurality of transistors are manufactured on the receiving backboard, and the light-emitting unit obtained by cutting the chip wafer in the embodiment of the invention comprises the LED chip 20 and the control switch which comprises at least one transistor, so that the transistor in the control switch can be used as a transistor in the control circuit, and thus, the transistor does not need to be manufactured on the receiving backboard, or only a part of the transistors need to be manufactured, and the manufacturing process of the receiving backboard is simplified. If the transistors are manufactured on the receiving backboard, the selection of the material of the receiving backboard is limited by the conditions of temperature and the like in the process of manufacturing the transistors, and the selection range of the material of the receiving backboard is narrow. In the embodiment of the invention, because the transistors are formed on the chip wafer, the transistors do not need to be manufactured on the receiving backboard, only the signal lines need to be manufactured on the receiving backboard, or only partial types of transistors need to be manufactured on the receiving backboard, so that the optional range of the receiving backboard material can be remarkably expanded.

Optionally, as shown in fig. 4, the chip wafer at least further includes a Scan signal line Scan, a Data signal line Data, and a plurality of control circuits; one control circuit corresponds to one LED chip 20; each control circuit is electrically connected to at least the Scan signal line Scan, the Data signal line Data, the first signal line VDD30, and the first electrode 204, and communicates the first signal line VDD30 with the first electrode 204 under the control of signals on at least the Scan signal line Scan and the Data signal line Data to supply an electrical signal to the first electrode 204. The second electrode 205 of the LED chip 20 is electrically connected to the second signal line Vref 40.

In fig. 4, the first signal line 30 is a VDD signal line, and the second signal line 40 is a Vref signal line.

Here, the control circuit 02 is not limited, and the control circuit 02 may be a control circuit including 2T1C (2 transistors, 1 storage capacitor) as shown in fig. 5; a control circuit comprising 6T 1C; of course, a control circuit including 7T1C, etc. may be used.

In addition, under the control of signals on at least the scanning signal line Scan and the Data signal line Data, the first signal line VDD30 may be simultaneously connected to the first electrodes 204 of the plurality of LED chips 20, or the plurality of first electrodes 204 may be connected to the first signal line VDD30 line by line.

In the case where the control circuit 02 includes 2T1C, the chip wafer includes a Scan signal line Scan and a Data signal line Data, and the control circuit including 2T1C communicates the first signal line VDD30 with the first electrode 204 under the control of signals on the Scan signal line Scan and the Data signal line Data to supply an electric signal to the first electrode 204.

In the case where the control circuit 02 includes 2T1C, as shown in fig. 5, the control circuit 02 includes a first transistor T1, a second transistor T2, and a storage capacitor Cst.

A gate of the first transistor T1 is electrically connected to a Scan signal line Scan, a first pole is electrically connected to a Data signal line Data, and a second pole is electrically connected to a gate of the second transistor T2; a first pole of the second transistor T2 is electrically connected to the first signal line VDD30, and a second pole is electrically connected to the first electrode 204 of the LED chip 20; one end of the storage capacitor Cst is electrically connected to the gate of the second transistor T2, and the other end is electrically connected to the first signal line VDD 30.

In some embodiments, the first poles of the first transistor T1 and the second transistor T2 are sources, and the second poles are drains. In other embodiments, the first poles of the first transistor T1 and the second transistor T2 are drains, and the second poles are sources.

It should be understood that the Scan signal line Scan may be formed at the same time when the gates of the first and second transistors T1 and T2 are formed. The Data signal line Data is manufactured while the first and second poles of the first and second transistors T1 and T2 are manufactured.

In the embodiment of the present invention, when the Scan signal line Scan inputs the Scan signal, the first transistor T1 is turned on, the signal on the Data signal line Data is input to the gate of the second transistor T2 through the first transistor T1, the second transistor T2 is turned on, and the first signal line VDD30 is communicated with the first electrode 204 of the LED chip 20, so as to provide the first electrode 204 with an electrical signal.

The positional relationship between the first transistor T1 and the second transistor T2 and the LED chip 20 is not limited, and in some embodiments, as shown in fig. 6, the first transistor T1 and the second transistor T2 are stacked on the substrate 10, in which case, the first transistor T1 and the second transistor T2 may be close to the substrate 10 relative to the LED chip 20, or the LED chip 20 may be close to the substrate 10 relative to the first transistor T1 and the second transistor T2. In the case where the first transistor T1, the second transistor T2, and the LED chip 20 are stacked on the substrate 10, as shown in fig. 6, an insulating layer 50 may be disposed between the first transistor T1, the second transistor T2, and the LED chip 20. In other embodiments, the first transistor T1, the second transistor T2, and the LED chip 20 are disposed side by side on the substrate 10.

In some embodiments, as shown in fig. 6, the first semiconductor pattern 201 is close to the substrate 10 with respect to the first and second transistors T1 and T2; the second electrode 205 of the LED chip 20 is shared with the second pole of the second transistor T2.

The storage capacitor Cst is not illustrated in fig. 6.

Compared with the method for manufacturing the second electrode 205 of the LED chip 20 and the second pole of the second transistor T2, in the embodiment of the present invention, the second electrode 205 of the LED chip 20 and the second pole of the second transistor T2 are shared, so that the manufacturing process of the chip wafer can be simplified.

As shown in fig. 7, in order to increase the contact area between the Data signal line Data and the first pole of the first transistor T1 to reduce the contact resistance, in some embodiments, an interlayer defining layer 70 is formed on the sides of the first transistor T1 and the second transistor T2 away from the substrate 10, a first conductive terminal 701 is formed on the side of the interlayer defining layer 70 away from the substrate 10, the first conductive terminal 701 passes through a via hole on the interlayer defining layer 70 to be electrically connected to the first pole of the first transistor T1, and the first conductive terminal 701 is also electrically connected to the Data signal line Data. In order to increase the contact area between the Scan signal line Scan and the gate of the first transistor T1 to reduce the contact resistance, in some embodiments, a second conductive terminal 702 is formed on the side of the interlayer defining layer 70 away from the substrate 10, the second conductive terminal 702 is electrically connected to the gate of the first transistor T1 through a via hole on the interlayer defining layer 70, and the second conductive terminal 702 is also electrically connected to the Scan signal line Scan. In order to increase the contact area between the first signal line VDD and the first electrode of the second transistor T2 to reduce the contact resistance, in some embodiments, a third conductive terminal 703 is formed on the interlayer defining layer 70 on the side away from the substrate 10, the third conductive terminal 703 passes through a via hole on the interlayer defining layer 70 to electrically connect to the first electrode of the second transistor T2, and the third conductive terminal 703 is electrically connected to the first signal line VDD. In order to increase the contact area between the second signal line Vref and the second electrode 205 of the LED chip 20 to reduce the contact resistance, in some embodiments, a fourth conductive terminal 704 is fabricated on a side of the interlayer defining layer 604 away from the substrate 10, the fourth conductive terminal 704 passes through a via hole on the interlayer defining layer 70 to be electrically connected to the second electrode 205 of the LED chip 20, and the fourth conductive terminal 704 is also electrically connected to the second signal line Vref.

On this basis, the first conductive terminal 701, the second conductive terminal 702, the third conductive terminal 703 and the fourth conductive terminal 704 may be fabricated at the same time or one by one.

An embodiment of the present invention further provides a method for manufacturing a chip wafer, which can be used for manufacturing the chip wafer, and the method for manufacturing the chip wafer, as shown in fig. 8, includes:

s100, as shown in fig. 1, a plurality of LED chips 20, a first signal line 30, and a second signal line 40 are formed on a substrate 10.

Wherein the LED chip 20 includes a second semiconductor pattern 203, a light emitting pattern 202, and a first semiconductor pattern 201 sequentially stacked on the substrate 10; the LED chip 20 further includes a first electrode 204 in contact with the first semiconductor pattern 201 and a second electrode 205 in contact with the second semiconductor pattern 203; the first signal line 30 is used for providing an electrical signal to the first electrodes 204 of the plurality of LED chips 20, the second electrodes 205 are electrically connected to the second signal line 40, and the second signal line 40 is used for providing an electrical signal to the second electrodes 205.

Here, the plurality of LED chips 20 may be formed on the substrate 10 first, and then the first signal line 30 and the second signal line 40 may be formed; the first signal line 30 and the second signal line 40 may be formed on the substrate 10, and then the plurality of LED chips 20 may be formed; of course, the first signal line 30 and/or the second signal line 40 may be formed in synchronization with the first electrode 204 or the second electrode 205 in the LED chip 20.

On this basis, the second semiconductor pattern 203, the light emitting pattern 202, and the first semiconductor pattern 201 are formed on the substrate 10, including:

s200, as shown in fig. 9, a second semiconductor layer 2031, a light-emitting layer 2021, and a first semiconductor layer 2011 are sequentially formed (e.g., grown by epitaxial growth) on the substrate 10.

Here, in some embodiments, after the first semiconductor layer 2011 is formed, as shown in fig. 10, a first electrode layer 2041 may also be formed on the first semiconductor layer 2011.

S201, as shown in fig. 11, the second semiconductor layer 2031, the light-emitting layer 2021, and the first semiconductor layer 2011 are patterned once to obtain a second semiconductor pattern 203, a light-emitting pattern 202, and a first semiconductor pattern 201 which are sequentially stacked.

Here, the patterning includes mask exposure, development, and etching processes.

In some embodiments, after S201, the method for manufacturing a chip wafer further includes: a portion of the first semiconductor pattern 201 and a portion of the light emitting pattern 202 are removed to expose a portion of the second semiconductor pattern 203.

When the first electrode layer 2041 is formed on the first semiconductor layer 2011, as shown in fig. 12, the second semiconductor layer 2031, the light-emitting layer 2021, the first semiconductor layer 2011, and the first electrode layer 2041 are patterned at one time, and the second semiconductor pattern 203, the light-emitting pattern 202, the first semiconductor pattern 201, and the first electrode 204 are sequentially stacked.

In the case where the second semiconductor pattern 203, the light emitting pattern 202, the first semiconductor pattern 201, and the first electrode 204 are sequentially stacked after S201, as shown in fig. 13, a portion of the first electrode 204, a portion of the first semiconductor pattern 201, and a portion of the light emitting pattern 202 are removed to expose a portion of the second semiconductor pattern 203.

Embodiments of the present invention provide a method for manufacturing a chip wafer, which has the same structure and beneficial effects as the chip wafer provided in the above embodiments, and the above embodiments have already described the chip wafer in detail, so that details are not repeated herein.

In embodiments of the present invention, the first signal line 30 is used to provide an electrical signal to the first electrode 204, and in some embodiments, the first electrodes 204 of the plurality of LED chips 20 are electrically connected to the first signal line 30.

Here, the embodiment of the present invention may include a first signal line 30, and the first electrodes 204 of all the LED chips 20 are electrically connected to the first signal line 30, so that the first signal line 30 provides the electrical signals to the first electrodes 204 of all the LED chips 20 at the same time. Two or more first signal lines 30 may also be included, each first signal line 30 is electrically connected to at least one LED chip 20, in this case, two or more first signal lines 30 may simultaneously provide an electrical signal to the first electrodes 204 of all the LED chips 20, or two or more first signal lines 30 may sequentially input an electrical signal to provide an electrical signal to the first electrodes 204 of the LED chips 20 electrically connected thereto.

Since the first electrodes 204 of the plurality of LED chips 20 are all electrically connected to the first signal line 30, the first signal line 30 may directly provide the first electrodes 204 of the plurality of LED chips 20 with an electrical signal.

In a case where the first electrodes 204 of the LED chips 20 are all electrically connected to the first signal line 30, after the first semiconductor pattern 201 of the LED chip 20 is formed on the substrate 10, the method for manufacturing a chip wafer further includes:

s300, as shown in fig. 14, an insulating layer 50 is formed on the first semiconductor pattern 201.

In the case where the first electrode 204 is formed on the first semiconductor pattern 201, as shown in fig. 14, the insulating layer 50 is formed on the first electrode 204.

Here, the material of the insulating layer 50 may be an organic material or an inorganic material.

S301, as shown in fig. 3a and 3b, forming a plurality of control switches on the insulating layer 50; one control switch corresponds to one LED chip 20, and each control switch includes at least one transistor 60.

Here, each control switch may include one transistor 60, or may include two or more transistors 60.

The transistor 60 may be a top gate transistor or a bottom gate transistor, and is not limited thereto. The process of manufacturing the transistor 60 will be described in detail below by taking the transistor 60 as a top gate transistor as an example.

S400, as shown in fig. 15, a semiconductor layer is formed on the insulating layer 50, and the semiconductor layer is patterned to form an active layer 601.

Here, the material of the semiconductor layer may be an oxide semiconductor, polycrystalline silicon, amorphous silicon, single crystal silicon, or other semiconductor material. The Oxide semiconductor may be, for example, one or more of IGZO (Indium Gallium Zinc Oxide), ZnO (Zinc Oxide), or IZO (Indium Zinc Oxide).

S401, as shown in fig. 16, a gate insulating layer 602 and a first conductive layer are sequentially formed on the active layer 601, and the first conductive layer is patterned to form a gate electrode 603.

S402, as shown in fig. 17, an interlayer defining layer 604 is formed on the gate electrode 603, and the interlayer defining layer 604 and the gate insulating layer 602 are patterned to form a first via hole and a second via hole so as to expose the active layer 601.

In addition, as shown in fig. 17, the interlayer defining layer 604 may be patterned to form a third via hole to expose the gate 603; the interlayer defining layer 604, the gate insulating layer 602, and the insulating layer 50 are patterned to form fourth and fifth via holes to expose the first electrode 204 and the second semiconductor pattern 203.

S403, as shown in fig. 18, a first pole 605 and a second pole 606 are formed on the interlayer defining layer 604, and the first pole 605 and the second pole 606 are electrically connected to the active layer 601 through a first via hole and a second via hole, respectively.

In addition, as shown in fig. 18, a gate connection terminal 603a, a first electrode connection terminal 204a, and a second electrode 205 may be further formed on the interlayer defining layer 604. The gate connection terminal 603a passes through the third via to be electrically connected to the gate electrode 603, the first electrode connection terminal 204a passes through the fourth via to be electrically connected to the first electrode 204, and the second electrode 205 passes through the fifth via to be electrically connected to the second semiconductor pattern 203.

In other embodiments, the first electrodes 204 of the plurality of LED chips 20 are indirectly electrically connected to the first signal line 30. In this case, optionally, the method for manufacturing a chip wafer further includes:

forming at least a Scan signal line Scan, a Data signal line Data, and a plurality of control circuits on the substrate 10; one control circuit corresponds to one LED chip 20; each control circuit is electrically connected to at least one of the Scan signal line Scan, the Data signal line Data, the first signal line VDD30, and the first electrode 204, and at least under the control of signals on the Scan signal line Scan and the Data signal line Data, the first signal line VDD30 is connected to the first electrode 204, so as to provide an electrical signal to the first electrode 204.

Since the first signal line VDD30 may provide an electrical signal to the first electrode 204 and the second signal line 40 may provide an electrical signal to the second electrode 205, in the case where the first signal line 30 provides an electrical signal to the first electrode 204 and the second signal line 40 provides an electrical signal to the second electrode 205, if the LED chip 20 is not damaged, the LED chip 20 may emit light.

Here, the control circuit 02 is not limited, and the control circuit 02 may be a control circuit including 2T1C (2 transistors, 1 storage capacitor); a control circuit comprising 6T 1C; of course, a control circuit including 7T1C is also possible.

In addition, under control of signals on at least the Scan signal line Scan and the Data signal line Data, the first signal line VDD30 may be simultaneously connected to the plurality of first electrodes 204, or the plurality of first electrodes 204 may be connected to the first signal line VDD30 line by line.

Optionally, before at least forming the Scan signal line Scan, the Data signal line Data, and the plurality of control circuits on the substrate 10, the method for preparing the chip wafer further includes:

an insulating layer 50 is formed on the first semiconductor pattern 201.

In the case where the first electrode 204 is formed on the first semiconductor pattern 201, the insulating layer 50 is formed on the first electrode 204.

Forming a control circuit on a substrate 10, comprising:

forming a first transistor T1, a second transistor T2, and a storage capacitor Cst on the insulating layer 50; a gate of the first transistor T1 is electrically connected to the Scan signal line Scan, a first electrode is electrically connected to the Data signal line Data, and a second electrode is electrically connected to a gate of the second transistor T2; a first pole of the second transistor T2 is electrically connected to the first signal line VDD, and a second pole is electrically connected to the first electrode 204 of the LED chip 20; one end of the storage capacitor Cst is electrically connected to the gate of the second transistor T2, and the other end is electrically connected to the first signal line VDD.

Here, the manufacturing methods of the first transistor T1 and the second transistor T2 may refer to the manufacturing method of the transistor 60, and are not described herein again.

In the embodiment of the present invention, after the chip wafer is prepared, the first signal line 30 provides an electrical signal to the first electrode 204, the second signal line 40 provides an electrical signal to the second electrode 205, and the light emitting condition of each LED chip 20 is recorded, so as to obtain the position distribution of the undamaged LED chips 20 on the substrate 10. Then, the chip wafer is cut to obtain a plurality of light emitting units each including an LED chip 20 as shown in fig. 19, and after the substrate 10 is removed, the plurality of light emitting units are independent of each other.

It should be understood that, in the case that the chip wafer includes a control switch, the light emitting unit obtained by cutting the chip wafer includes the control switch in addition to the LED chip 20. Alternatively, when the chip wafer includes the control circuit, the light-emitting unit obtained by cutting the chip wafer includes the control circuit in addition to the LED chip 20.

On this basis, the side of the substrate 10 facing away from the LED chip 20 may be irradiated with laser light to separate the substrate 10 from the light emitting unit.

The embodiment of the invention also provides a Micro-LED display, which comprises a receiving back plate and a plurality of light-emitting units arranged on the receiving back plate, wherein each light-emitting unit comprises an LED chip 20; the plurality of light-emitting units are obtained by cutting the chip wafer and transferring; the receiving backplane comprises at least a first signal line 30, a second signal line 40, a Data signal line Data and a scanning signal line Scan; the second electrodes 205 of the LED chips 20 are all electrically connected to the second signal line 40; the Micro-LED display further comprises: a plurality of control circuits; one control circuit corresponds to one LED chip 20; the control circuit communicates the first signal line 30 with the first electrode 204 under the control of signals on at least the Scan signal line Scan and the Data signal line Data to provide an electric signal to the first electrode 204; the control circuit comprises a plurality of transistors and a storage capacitor; the receiving backplane and/or the light emitting cells comprise a plurality of transistors and storage capacitors.

Here, it may be that the light emitting unit includes all the transistors and storage capacitors in the control circuit, and in this case, as shown in fig. 20, the receiving backplane 80 includes a first signal line VDD30, a second signal line Vref40, a Data signal line Data, and a Scan signal line Scan, and a lead terminal on the first signal line VDD30, a lead terminal on the second signal line Vref40, a lead terminal on the Data signal line Data, and a lead terminal on the Scan signal line Scan are all electrically connected to the light emitting unit for controlling the LED chip 20 in the light emitting unit to emit light. The light emitting unit may also include a part of transistors and a storage capacitor in the control circuit, the receiving backplane 80 includes a part of transistors and/or a storage capacitor in the control circuit in addition to the first signal line 30, the second signal line 40, the Data signal line Data and the scanning signal line Scan, as shown in fig. 21, a transistor is provided for each control circuit on the receiving backplane 80, and the part of control circuits in the light emitting unit and the part of control circuits in the receiving backplane 80 are used together as a whole to control the LED chip 20 in the light emitting unit to emit light.

In the case where the light emitting unit includes a part of the transistors and the receiving backplane 80 includes a part of the transistors, the type of the transistors included in the light emitting unit and the type of the transistors included in the receiving backplane 80 may be the same or different. In some embodiments, the transistors included in the receiving backplane 80 may be polysilicon transistors, and the polysilicon transistors have high mobility, and thus may be used as driving transistors in the control circuit to improve driving capability. The transistor included in the light emitting unit may be an oxide transistor, and since a leakage current of the oxide transistor is low, it may be used as a switching transistor in a control circuit for reducing power consumption.

The manufacturing process of the Micro-LED display comprises the following steps: as shown in fig. 22, the transfer head of the transfer device 90 is used to pick up the qualified LED chip 20, transfer the LED chip onto the receiving backplane 80, and bind the LED chip with the corresponding conductive terminals 801 on the receiving backplane 80.

The embodiment of the invention provides a Micro-LED display, because the LED chips 20 in the light emitting units of the Micro-LED display are detected before being transferred to the receiving backboard 80, the LED chips 20 transferred to the receiving backboard 80 can normally emit light, and the display effect of the Micro-LED display is further ensured.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A chip wafer, comprising: a substrate and a plurality of LED chips disposed on the substrate;

the LED chip comprises a second semiconductor pattern, a light-emitting pattern and a first semiconductor pattern which are sequentially stacked on the substrate; the LED chip further includes a first electrode in contact with the first semiconductor pattern and a second electrode in contact with the second semiconductor pattern;

the chip wafer further comprises a first signal line and a second signal line which are arranged on the substrate; the first signal line is used for providing electric signals for the first electrodes of the LED chips when detecting whether the LED chips are damaged, the second electrodes are electrically connected with the second signal line, and the second signal line is used for providing electric signals for the second electrodes when detecting whether the LED chips are damaged;

the chip wafer further comprises a plurality of control switches; one of the control switches corresponds to one of the LED chips;

each of the control switches comprises at least one transistor;

the control switch is used for controlling the LED chip corresponding to the control switch to emit light when detecting whether the LED chip is damaged, and the transistor in the control switch can be multiplexed as a transistor in the control circuit.

2. The chip wafer of claim 1, further comprising at least a scan signal line, a data signal line, and a plurality of control circuits; one of the control circuits corresponds to one of the LED chips;

each control circuit is electrically connected with at least the scanning signal line, the data signal line, the first signal line and the first electrode, and at least under the control of signals on the scanning signal line and the data signal line, the first signal line is communicated with the first electrode so as to provide an electric signal for the first electrode.

3. The chip wafer of claim 2, in which the control circuit comprises a first transistor, a second transistor and a storage capacitor;

the grid electrode of the first transistor is electrically connected with the scanning signal line, the first pole of the first transistor is electrically connected with the data signal line, and the second pole of the first transistor is electrically connected with the grid electrode of the second transistor;

a first pole of the second transistor is electrically connected with a first signal line, and a second pole of the second transistor is electrically connected with the first electrode of the LED chip;

one end of the storage capacitor is electrically connected with the grid electrode of the second transistor, and the other end of the storage capacitor is electrically connected with the first signal line.

4. The chip wafer according to claim 3, wherein the first semiconductor pattern is close to the substrate with respect to the first transistor and the second transistor;

the second electrode of the LED chip is shared with the second pole of the second transistor.

5. The chip wafer according to claim 1, wherein the first electrodes of the plurality of LED chips are electrically connected to the first signal line.

6. A preparation method of a chip wafer is characterized by comprising the following steps:

forming a plurality of LED chips, a first signal line, and a second signal line on a substrate;

the LED chip comprises a second semiconductor pattern, a light emitting pattern and a first semiconductor pattern which are sequentially stacked and arranged on the substrate; the LED chip further includes a first electrode in contact with the first semiconductor pattern and a second electrode in contact with the second semiconductor pattern; the first signal line is used for providing an electric signal for the first electrodes of the LED chips, the second electrodes are electrically connected with the second signal line, and the second signal line is used for providing an electric signal for the second electrodes;

after forming the first semiconductor pattern of the LED chip on the substrate, the method for manufacturing a chip wafer further includes:

forming an insulating layer on the first semiconductor pattern;

forming a plurality of control switches on the insulating layer; one of the control switches corresponds to one of the LED chips, and each of the control switches includes at least one transistor.

7. The method for manufacturing a chip wafer according to claim 6, further comprising:

forming at least a scanning signal line, a data signal line, and a plurality of control circuits on the substrate; one of the control circuits corresponds to one of the LED chips;

8. The method of manufacturing a chip wafer according to claim 7, wherein before forming at least a scanning signal line, a data signal line, and a plurality of control circuits on the substrate, the method further comprises:

forming an insulating layer on the first semiconductor pattern;

forming a control circuit on the substrate, comprising:

forming a first transistor, a second transistor, and a storage capacitor over the insulating layer; the grid electrode of the first transistor is electrically connected with the scanning signal line, the first pole of the first transistor is electrically connected with the data signal line, and the second pole of the first transistor is electrically connected with the grid electrode of the second transistor; a first pole of the second transistor is electrically connected with a first signal line, and a second pole of the second transistor is electrically connected with the first electrode of the LED chip; one end of the storage capacitor is electrically connected with the grid electrode of the second transistor, and the other end of the storage capacitor is electrically connected with the first signal line.

9. The method for manufacturing a chip wafer according to claim 6, wherein the first electrodes of the LED chips are electrically connected to the first signal line.

10. A Micro-LED display is characterized by comprising a receiving back plate and a plurality of light-emitting units arranged on the receiving back plate, wherein each light-emitting unit comprises an LED chip; a plurality of the light emitting units are obtained by dicing the chip wafer according to any one of claims 1 to 5, and transferring;

the receiving backboard at least comprises a first signal line, a second signal line, a data signal line and a scanning signal line; the second electrodes of the LED chips are electrically connected with the second signal wires;

the Micro-LED display further comprises: a plurality of control circuits; one of the control circuits corresponds to one of the LED chips; the control circuit communicates the first signal line with the first electrode at least under the control of signals on the scanning signal line and the data signal line so as to provide an electric signal for the first electrode; the control circuit comprises a plurality of transistors and a storage capacitor; the receiving back plate and/or the light emitting unit include a plurality of the transistors and the storage capacitors.