CN110459544B - Three-dimensional memory, preparation method thereof and electronic equipment - Google Patents
Three-dimensional memory, preparation method thereof and electronic equipment Download PDFInfo
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- CN110459544B CN110459544B CN201910623636.4A CN201910623636A CN110459544B CN 110459544 B CN110459544 B CN 110459544B CN 201910623636 A CN201910623636 A CN 201910623636A CN 110459544 B CN110459544 B CN 110459544B
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Abstract
The application provides a three-dimensional memory, a preparation method thereof and electronic equipment, wherein the preparation method comprises the following steps: providing a substrate, forming a storage part and a control part on one side of the substrate, and enabling the storage part to be electrically connected with the control part, wherein the storage part comprises a first conductive connecting piece. An interlayer insulating layer is formed on the other side of the substrate. A connection hole penetrating the interlayer insulating layer and the substrate is formed to expose the first conductive connection member. And sequentially forming an etching barrier layer and a protective layer on the hole wall of the connecting hole. And etching the protective layer corresponding to the first conductive connecting piece to expose at least part of the etching barrier layer. The etch stop layer is etched using a wet etch to again expose at least a portion of the first conductive connection. A second conductive connecting member connected to the first conductive connecting member is formed in the connection hole. The etching barrier layer is additionally arranged on the hole wall of the connecting hole, and the etching barrier layer is etched by adopting a wet etching method, so that the service performance of the three-dimensional memory is improved, and the service life of the three-dimensional memory is prolonged.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a three-dimensional memory, a preparation method of the three-dimensional memory and electronic equipment.
Background
A three-dimensional (3D) memory is a memory device in which memory cells are three-dimensionally arranged over a substrate, and has advantages of high integration density, large storage capacity, and low power consumption, thereby being widely used in electronic products.
In the process of manufacturing the three-dimensional memory, the memory portion is generally formed in some regions on the same side of the substrate, the control portion is formed in other regions, and then the conductive portion is formed on the other side of the substrate. In forming the conductive portion, a connection hole is usually etched by dry etching to expose the conductive connection member in the storage portion. When the connecting hole is etched, charged particles in the plasma gas can be transmitted to the control device in the control part through the conductive connecting piece, the service performance and the service life of the control device are influenced, and therefore the service performance and the service life of the three-dimensional memory can be reduced.
Disclosure of Invention
In view of this, the present application provides a three-dimensional memory, a method for manufacturing the same, and an electronic device, in which an etching barrier layer is additionally disposed on a hole wall of the connection hole, so as to prevent charged particles from entering the first conductive connection member. And the etching barrier layer is etched by adopting a wet etching method, so that the influence on the normal use of the control device caused by the transmission of charged particles of plasma gas to the first conductive connecting piece in a dry etching method is avoided. The service performance and the service life of the control device and the three-dimensional memory are improved.
The first aspect of the present application provides a method for manufacturing a three-dimensional memory, the method comprising:
providing a substrate, forming a storage part and a control part on one side of the substrate, and enabling the storage part to be electrically connected with the control part, wherein the storage part comprises a first conductive connecting piece;
forming an interlayer insulating layer on the other side of the substrate;
forming a connection hole penetrating the interlayer insulating layer and the substrate to expose the first conductive connection member;
forming an etching barrier layer and a protective layer on the hole wall of the connecting hole in sequence;
etching the protective layer corresponding to the first conductive connecting piece to expose at least part of the etching barrier layer;
etching the etching barrier layer by a wet etching method to expose at least part of the first conductive connecting piece again; and
and forming a second conductive connecting piece connected with the first conductive connecting piece in the connecting hole.
In the manufacturing method provided by the first aspect of the present application, an etching barrier layer is additionally provided on the hole wall of the connection hole, and the etching barrier layer is provided between the hole wall of the connection hole and the protection layer. Due to the arrangement of the etching barrier layer, when the protective layer corresponding to the first conductive connecting piece is etched, even if the protective layer corresponding to the first conductive connecting piece is etched, the etching barrier layer is further arranged on the surface of the first conductive connecting piece, so that charged particles are not transmitted to the first conductive connecting piece when the protective layer is etched. In addition, the etching barrier layer is etched by adopting a wet etching method, charged particles are prevented from being introduced, and the charged particles of plasma gas in a dry etching method are prevented from being transmitted to the first conductive connecting piece, so that the charged particles are transmitted to the control device, the normal use of the control device is influenced, and the service life of the control device is shortened. The preparation method provided by the first aspect of the application has the advantages of simple process and low cost, can avoid the charged particles from being transmitted to the control device, and improves the service performance and the service life of the control device and the three-dimensional memory.
Wherein "etching the etch stop layer using a wet etch process to re-expose at least a portion of the first conductive connection" comprises:
etching the etching barrier layer corresponding to the first conductive connecting piece by using an etching solution, wherein the etching solution comprises phosphoric acid, the etching temperature is 150-.
Wherein "etching the etch stop layer using a wet etch process to re-expose at least a portion of the first conductive connection" comprises:
etching the etching barrier layer to expose at least part of the first conductive connecting piece again, and controlling etching parameters to enable the size of the connecting hole close to the substrate to be larger than the size of the connecting hole far away from the substrate.
Wherein "etching the protective layer corresponding to the first conductive connection to expose at least a portion of the etch stop layer" comprises:
etching the protective layer and the etching barrier layer corresponding to the first conductive connecting piece to expose at least part of the etching barrier layer, and controlling etching parameters to enable the surface of the etching barrier layer to form a groove.
Wherein, the step of sequentially forming the etching barrier layer and the protective layer on the hole wall of the connecting hole comprises the following steps:
forming the etch stopper layer on a top surface of the interlayer insulating layer and a hole wall of the connection hole;
removing the etch stop layer on the top surface of the interlayer insulating layer; and
forming the protective layer on a top surface of the interlayer insulating layer and a surface of the etch stopper layer within the connection hole.
Wherein, after "forming the protective layer on the top surface of the interlayer insulating layer and the surface of the etch stopper layer in the connection hole", further comprising: removing the protective layer on the top surface of the interlayer insulating layer.
Wherein "forming a connection hole penetrating the interlayer insulating layer and the substrate to expose the first conductive connection member" includes:
etching the interlayer insulating layer and the substrate corresponding to the first conductive connecting piece to form a connecting hole penetrating through the interlayer insulating layer and the substrate, exposing the first conductive connecting piece, and enabling an orthographic projection of the connecting hole on the substrate to cover an orthographic projection of the first conductive connecting piece on the substrate.
A second aspect of the present application provides a three-dimensional memory including a substrate, a memory part, a control part, an insulating layer, and a conductive part, the storage part is internally provided with a first conductive connecting piece, the storage part and the control part are sequentially stacked on one side of the substrate, the insulating layer is arranged on the other side of the substrate, the conducting part is embedded in the insulating layer and the substrate and corresponds to the first conductive connecting piece, the conduction part comprises a second conductive connecting piece, and a protective layer and an etching barrier layer which are sequentially stacked on two opposite sides of the conduction part, the second conductive connecting piece is electrically connected with the first conductive connecting piece, the control part comprises a third conductive connecting piece and a control device, the third conductive connecting piece is electrically connected with the control device, and the third conductive connecting piece is electrically connected with the first conductive connecting piece.
The three-dimensional memory that this application second aspect provided adds the etching barrier layer through the relative both sides at the electrically conductive second connecting piece of second, has avoided in preparation process charged particle transmission to first electrically conductive connecting piece and then transmit to the controlling means, has avoided influencing the normal use of controlling means. The three-dimensional memory provided by the second aspect of the application has the advantages that the service performance service lives of the control device and the three-dimensional memory are prolonged, and the practicability is very strong.
Wherein the insulating layer comprises an interlayer insulating layer; alternatively, the insulating layer includes an interlayer insulating layer and either one or both of the etch stopper layer and the protective layer provided on a top surface of the interlayer insulating layer.
Wherein, when the insulating layer includes an interlayer insulating layer and the etch stop layer and the protective layer provided on a top surface of the interlayer insulating layer, the etch stop layer and the protective layer are sequentially stacked on the top surface of the interlayer insulating layer.
Wherein a dimension of the second conductive connector near the substrate is greater than a dimension of the second conductive connector away from the substrate.
A third aspect of the present application provides an electronic device comprising a three-dimensional memory as provided in the second aspect of the present application and a processor for writing data into and/or reading data from the three-dimensional memory.
According to the electronic device provided by the third aspect of the present application, by using the three-dimensional memory provided by the second aspect of the present application, the service performance and the service life of the three-dimensional memory and the electronic device can be improved.
Drawings
In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.
Fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of the three-dimensional memory corresponding to step S100 in fig. 1.
Fig. 3 is a schematic structural diagram of the three-dimensional memory corresponding to step S200 in fig. 1.
Fig. 4 is a schematic structural diagram of the three-dimensional memory corresponding to step S300 in fig. 1.
Fig. 5 is a schematic structural diagram of the three-dimensional memory corresponding to step S400 in fig. 1.
Fig. 6 is a schematic structural diagram of the three-dimensional memory corresponding to step S500 in fig. 1.
Fig. 7 is a schematic structural diagram of the three-dimensional memory corresponding to step S600 in fig. 1.
Fig. 8 is a schematic structural diagram of the three-dimensional memory corresponding to step S700 in fig. 1.
Fig. 9 is a process flow diagram included in step S600 in fig. 1.
Fig. 10 is a schematic structural diagram of the three-dimensional memory corresponding to step S610 in fig. 9.
Fig. 11 is a process flow diagram included in step S500 in fig. 1.
Fig. 12 is a schematic structural diagram of the three-dimensional memory corresponding to step S510 in fig. 11.
Fig. 13 is a process flow diagram included in step S400 in fig. 1.
Fig. 14 is a schematic structural diagram of the three-dimensional memory corresponding to step S410 in fig. 13.
Fig. 15 is a schematic structural diagram of the three-dimensional memory corresponding to step S420 in fig. 13.
Fig. 16 is a schematic structural diagram of the three-dimensional memory corresponding to step S430 in fig. 13.
Fig. 17 is a process flow diagram included in step S400 in fig. 1.
Fig. 18 is a schematic structural diagram of the three-dimensional memory corresponding to step S440 in fig. 17.
Fig. 19 is a process flow diagram included in step S300 in fig. 1.
Fig. 20 is a schematic structural diagram of the three-dimensional memory corresponding to step S310 in fig. 19.
Fig. 21 is a schematic structural diagram of a three-dimensional memory according to a first embodiment of the present application.
Fig. 22 is a schematic structural diagram of a three-dimensional memory according to a second embodiment of the present application.
Fig. 23 is a schematic structural diagram of a three-dimensional memory according to a third embodiment of the present application.
Fig. 24 is a schematic structural diagram of a three-dimensional memory according to a fourth embodiment of the present application.
Fig. 25 is a schematic structural diagram of a three-dimensional memory according to a fifth embodiment of the present application.
Fig. 26 is a schematic structural diagram of a three-dimensional memory according to a sixth embodiment of the present application.
Fig. 27 is a schematic circuit structure diagram of an electronic device according to an embodiment of the present application.
Wherein:
the three-dimensional memory comprises a three-dimensional memory body-1, a substrate-10, a memory portion-20, a sub-memory portion-21, a step structure-210, a memory stacking layer-211, an interlayer dielectric layer-212, a gate layer-213, a peripheral circuit portion-22, a first conductive connecting piece-220, a control portion-30, a control device-300, a third conductive connecting piece-310, an interlayer insulating layer-40, a connecting hole-41, an etching barrier layer-50, a groove-51, a protective layer-60, a second conductive connecting piece-70, an insulating layer-80 and a conductive portion-90.
Detailed Description
The following is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications are also considered as the protection scope of the present application.
Prior to the description of the embodiments of the present application, the technical problems mentioned in the background will be first described.
In the fabrication of a three-dimensional memory, it is a conventional practice to form a memory portion in some regions on the same side of a substrate, and after forming a control portion in other regions, to first form an interlayer insulating layer on the other side of the substrate, and then form a connection hole penetrating the interlayer insulating layer and the substrate to expose the conductive connection member. Thereafter, a protective layer is formed on the hole wall of the connection hole, and then the protective layer is etched, typically by dry etching, to expose the conductive connection member. Plasma gas is generally used in the preparation process of the dry etching method, and a large amount of charged particles exist in the plasma gas. Once the protective layer is etched away and the conductive connecting member is exposed, the charged particles in the plasma gas contact the conductive connecting member due to the conductive connecting member being made of a material that is easily conductive, and are transmitted into the conductive connecting member. The conductive connecting piece is electrically connected with the control device in the control part, so that the charged particles transmitted into the conductive connecting piece can be continuously transmitted into the control device. Since the charged particles may affect not only the performance of the control device but also the lifetime of the control device, the performance and lifetime of the three-dimensional memory may be reduced.
According to the preparation method of the three-dimensional memory provided by the embodiment of the application, the etching barrier layer is additionally arranged, the protective layer is formed, the protective layer and the etching barrier layer corresponding to the first conductive connecting piece are sequentially removed, and the etching barrier layer is removed by adopting a wet etching method, so that the influence of charged particles on a control device is avoided, the service performance of the three-dimensional memory is further improved, and the service life of the three-dimensional memory is prolonged.
Please refer to fig. 1-8 together. Fig. 1 is a process flow chart of a method for manufacturing a three-dimensional memory 1 according to an embodiment of the present disclosure. Fig. 2 to 8 are schematic structural diagrams of the three-dimensional memory 1 corresponding to steps S100, S200, S300, S400, S500, S600, and S700 in fig. 1, respectively.
The embodiment of the application provides a preparation method of a three-dimensional memory 1, which comprises S100-S700, and is specifically described as follows. Fig. 2 is a schematic structural diagram of the three-dimensional memory corresponding to step S100 in fig. 1. As shown in fig. 2, S100, a substrate 10 is provided, a memory portion 20 and a control portion 30 are formed on one side of the substrate 10, and the memory portion 20 is electrically connected to the control portion 30, wherein the memory portion 20 includes a first conductive connection 220.
The substrate 10 of the present application is used to support device structures thereon, such as the memory portion 20 and the control portion 30. Alternatively, the substrate 10 of the present application includes, but is not limited to, a Silicon substrate, a Germanium substrate, a Silicon On Insulator (SOI) substrate or a Germanium On Insulator (GOI) substrate, and the like. Further optionally, the substrate 10 is a silicon substrate. Optionally, the substrate 10 has a thickness of 1.5-2.0 μm. Further optionally, the substrate 10 has a thickness of 1.8 μm. In the present application, a memory portion 20 is formed on one side of a substrate 10, a control portion 30 is formed on the side of the memory portion 20 away from the substrate 10, and the memory portion 20 is electrically connected to the control portion 30.
Next, the storage section 20 and the control section 30 will be described.
The storage unit 20 mainly functions as a storage function in the three-dimensional memory 1. The memory section 20 includes a sub memory section 21 and a peripheral circuit section 22. The sub-memory portion 21 is mainly used for forming a core memory circuit structure, and the peripheral circuit portion 22 is mainly used for forming a peripheral circuit structure for electrically connecting other structures in the three-dimensional memory 1. The sub-storage part 21 is provided therein with a step structure 210, and the step structure 210 mainly functions as a storage function. Wherein the step structure 210 is formed by a multilayer memory stack layer 211. Each memory stack layer 211 includes an interlayer dielectric layer 212 and a gate layer 213. The material of the interlayer dielectric layer 212 includes, but is not limited to, an oxide such as silicon oxide, and the material of the gate layer 213 includes, but is not limited to, a conductive metal such as metal tungsten and a compound of tungsten. The interlayer dielectric layer 212 in each memory stack layer 211 is closer to the substrate 10 than the gate layer 213. The step structure 210 can be regarded as an ONO stack structure, i.e., an interlayer dielectric layer 212, a gate layer 213, etc. are sequentially formed on the surface of the substrate 10. The peripheral circuit portion 22 is provided with a first conductive connecting member 220 therein, and the first conductive connecting member 220 is used for electrically connecting other structures in the three-dimensional memory 1. As for other structures of the storage portion 20, reference may be made to related structures of the storage portion 20 in the related art, and details are not described herein.
The control unit 30 mainly functions to control the three-dimensional memory 1 in the three-dimensional memory 1. The control portion 30 is generally provided with a control device 300 therein, and the control device 300 includes, but is not limited to, a MOS device (CMOS device or PMOS device). A third conductive connection member 310 is also provided in the control portion 30. The third conductive connection 310 is electrically connected to the control device 300. The first conductive connector 220 is electrically connected to the third conductive connector 310, and thus the first conductive connector 220 may be electrically connected to the control device 300, thereby allowing the control device 300 to control the three-dimensional memory 1.
Fig. 3 is a schematic structural diagram of the three-dimensional memory corresponding to step S200 in fig. 1. Referring to fig. 3, S200, an interlayer insulating layer 40 is formed on the other side of the substrate 10.
In the present invention, after the memory portion 20 and the control portion 30 are formed on one side of the substrate 10, the interlayer insulating layer 40 is formed on the other side of the substrate 10, which not only protects the substrate 10, but also insulates and isolates the substrate 10 from the easily conductive devices. Alternatively, the material of the interlayer insulating layer 40 includes, but is not limited to, any one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and doped silicon oxide. Alternatively, the interlayer insulating layer 40 has a thickness of 1.0 to 1.5 μm. Further alternatively, the thickness of the interlayer insulating layer 40 is 1.2 μm.
Fig. 4 is a schematic structural diagram of the three-dimensional memory corresponding to step S300 in fig. 1. Referring to fig. 4, a connection hole 41 is formed through the interlayer insulating layer 40 and the substrate 10 to expose the first conductive connection member 220S 300.
In the present application, holes are formed in the interlayer insulating layer 40 and the substrate 10 corresponding to the first conductive connecting member 220, that is, a connecting hole 41 penetrating through the interlayer insulating layer 40 and the substrate 10 is formed to expose the first conductive connecting member 220, so that a foundation can be laid for the first conductive connecting member 220 after the second conductive connecting member 70 is formed subsequently. Optionally, the width of the connection hole 41 (i.e. the vertical distance between the sidewalls of the two opposite sides of the connection hole 41) is 500-. Further optionally, the width of the connection hole 41 is 660 nm.
Fig. 5 is a schematic structural diagram of the three-dimensional memory corresponding to step S400 in fig. 1. Referring to fig. 5, S400, an etching stop layer 50 and a protection layer 60 are sequentially formed on the hole wall of the connection hole 41.
As can be seen from the above, the conventional method for manufacturing the three-dimensional memory 1 only forms the protective layer 60 on the hole wall of the connection hole 41, so that the above-mentioned problem of short service life of the three-dimensional memory 1 occurs when the protective layer 60 is removed by the dry etching method in the following. In the present application, however, an etch stop layer 50 is added, and the etch stop layer 50 is provided between the hole wall and the protective layer 60. It is also understood that the etching stop layer 50 is formed on the hole wall first and then the etching stop layer is formedThe surface of the barrier layer 50 (i.e. the side of the etch stop layer 50 facing away from the hole wall) is formed with a protective layer 60, which provides a blocking and protecting function for the subsequent etching operation, thereby solving the problem that the charged particles are transmitted into the first conductive connection member 220. Optionally, the materials of the etch stop layer 50 and the protection layer 60 include, but are not limited to, any one or combination of silicon oxide, silicon nitride, silicon oxynitride, and doped silicon oxide. Further alternatively, the material of the etching stop layer 50 is silicon nitride, and the material of the protection layer 60 is silicon oxide. This facilitates subsequent selective etching. Optionally, the etch stop layer 50 has a thickness of
Further optionally, the etch stop layer 50 has a thickness of
Optionally, the thickness of the protective layer 60 is
Further optionally, the thickness of the protective layer 60 is
Fig. 6 is a schematic structural diagram of the three-dimensional memory corresponding to step S500 in fig. 1. Referring to fig. 6, S500, the protection layer 60 corresponding to the first conductive connection element 220 is etched to expose at least a portion of the etch stop layer 50.
The protective layer 60 on the surface in the connection hole 41, i.e. the outermost protective layer 60, is etched first, and then the protective layer 60 corresponding to the first conductive connection element 220 is etched, so that the first conductive connection element 220 can be directly exposed after the etching of the etching barrier layer 50. The etching method generally includes a dry etching method and a wet etching method. Alternatively, the present application generally employs dry etching to etch the protective layer 60, because the dry etching can precisely control the etching position and has a definite etching direction, so that the desired microstructure can be etched better.
In addition, since the etch stopper layer 50 is additionally provided, the etch stopper layer 50 is exposed instead of the first conductive connection member 220 after the dry etching is performed to remove the etch stopper layer. Since the etch stop layer 50 does not conduct the charged particles, the charged particles are shielded by the etch stop layer 50 and are not transmitted into the first conductive connection member 220, so that the charged particles do not affect the control device 300.
Fig. 7 is a schematic structural diagram of the three-dimensional memory corresponding to step S600 in fig. 1. Referring to fig. 7, S600, the etching barrier layer 50 is etched by wet etching to expose at least a portion of the first conductive connecting element 220 again.
The etching stop layer 50 is etched by a wet etching method, that is, the etching stop layer 50 corresponding to the first conductive connection 220 is etched. Since the wet etching method mainly uses the etching solution to corrode the etching barrier layer 50 through a chemical reaction, when the etching barrier layer 50 corresponding to the first conductive connection member 220 is etched away to expose the first conductive connection member 220, since there is no charged particle in the etching solution, there is no charged particle entering the first conductive connection member 220 to enter the control device 300, and compared with the conventional art, the service life and the use performance of the control device 300 are not affected.
In addition, in S500, since a portion of the protection layer 60 is etched away, a pit is formed in the connection hole 41, so that when the etching barrier layer 50 is etched by wet etching, the etching solution preferentially erodes the etching barrier layer 50 in the pit in a direction close to the first conductive connection 220, and then etches the etching barrier layer in a direction toward a sidewall of the connection hole 41. Therefore, the directionality of the wet etching method is improved, and the control of the wet etching method is facilitated.
Fig. 8 is a schematic structural diagram of the three-dimensional memory corresponding to step S700 in fig. 1. Referring to fig. 8, S700, a second conductive connection member 70 connected to the first conductive connection member 220 is formed in the connection hole 41.
When the first conductive link 220 is exposed again, a conductive metal, for example, a compound of tungsten and tungsten, is filled into the connection hole 41, thereby forming the second conductive link 70 within the connection hole 41. Further, since the second conductive connector 70 is electrically connected to the first conductive connector 220, and the first conductive connector 220 is electrically connected to the control device 300 as can be seen from the above, the second conductive connector 70 is electrically connected to the control device 300. The first conductive connection 220, the second conductive connection 70, and the third conductive connection 310 act as three interconnected "wires" to draw the internal control device 300 to the outside for electrical connection to other structures.
In the manufacturing method provided by this embodiment, the etching stopper layer 50 is additionally provided on the hole wall of the connection hole 41, and the etching stopper layer 50 is provided between the hole wall of the connection hole 41 and the protective layer 60. Due to the arrangement of the etching barrier layer 50, when the protective layer 60 corresponding to the first conductive connection member 220 is etched, even if the protective layer 60 corresponding to the first conductive connection member 220 is etched away, the etching barrier layer 50 is further arranged on the surface of the first conductive connection member 220, so that charged particles are not transmitted to the first conductive connection member 220 when the protective layer 60 is etched. In addition, the etching barrier layer 50 is etched by a wet etching method, so that charged particles are prevented from being introduced, and charged particles of plasma gas in a dry etching method are prevented from being transmitted to the first conductive connecting member 220 and then transmitted to the control device 300, so that the normal use of the control device 300 is not influenced, and the service life of the control device 300 is not reduced. The preparation method provided by the embodiment has the advantages of simple process and low cost, can avoid the charged particles from being transmitted to the control device 300, improves the service performance of the control device 300 and prolongs the service life of the control device, and further improves the service performance of the three-dimensional memory 1 and prolongs the service life of the three-dimensional memory 1.
In this embodiment, "etching the etching stopper layer 50 by wet etching to expose at least a portion of the first conductive connection 220 again" may be implemented as follows:
etching the etching barrier layer 50 corresponding to the first conductive connection member 220 by using an etching solution, wherein the etching solution comprises phosphoric acid, the etching temperature is 150-.
The present embodiment etches the etch stop layer 50 corresponding to the first conductive connector 220. In etching the etch stopper layer 50 by wet etching, an etching solution is used. Optionally, the etching solution of the present application comprises phosphoric acid. When the material of the etching stop layer 50 is silicon nitride and the material of the protection layer 60 is silicon oxide, the phosphoric acid only etches the etching stop layer 50 made of silicon nitride and does not etch the protection layer 60 made of silicon oxide, thereby effectively protecting the protection layer 60 from being damaged.
In addition, determination of the etching parameters in the present embodiment is also important. Good etching was only possible when the etching temperature was about 150-. If it is outside this range, the effect intended by the present application may not be achieved. For example, when the etching temperature is too high, which is greater than 200 ℃, or the etching time is too long, which is greater than 80 seconds, the etching solution not only etches the etching stop layer 50 corresponding to the first conductive connection 220, but also laterally etches toward the hole wall of the connection hole 41, thereby exposing the substrate 10. Thus, when the conductive metal is filled subsequently, the conductive metal is connected to the substrate 10, and thus, leakage and crosstalk occur. When the etching temperature is too low, less than 150 ℃, or the etching time is too short, less than 40s, the etching through the etching barrier layer 50 is not performed, resulting in exposing the first conductive connection 220. Optionally, the etching temperature is 160-190 ℃ and the etching time is 50-70 s. Further optionally, the etching temperature is 180 ℃ and the etching time is 60 s.
Please refer to fig. 9 and 10 together. Fig. 9 is a process flow diagram included in step S600 in fig. 1. Fig. 10 is a schematic structural diagram of the three-dimensional memory corresponding to step S610 in fig. 9.
In this embodiment, the step S600 of etching the etching stop layer 50 by wet etching to expose at least a portion of the first conductive connection 220 again includes the step S610 shown in fig. 10.
Referring to fig. 10, S610, the etching barrier layer 50 is etched to expose at least a portion of the first conductive connection 220 again, and the etching parameters are controlled such that the size of the connection hole 41 close to the substrate 10 is larger than the size of the connection hole 41 away from the substrate 10.
As can be seen from the above, due to the existence of the recess in the connection hole 41, the etching solution etches toward the first conductive connection 220 first, and then etches toward the side wall of the connection hole 41 in the lateral direction. The present embodiment controls etching parameters (such as concentration of etching solution, etching temperature, etching time, etc.) to make the size of the connection hole 41 close to the substrate 10 larger than the size of the connection hole 41 away from the substrate 10. It is also understood that the lateral etching continues after the first conductive link 220 is etched down. And since the etching solution only etches the etch barrier layer 50 and not the protective layer 60, the size of the substrate 10 can be increased, thereby exposing more of the first conductive connectors 220. After the second conductive connection 70 is formed, since the contact area of the second conductive connection 70 with the first conductive connection 220 is increased, the transfer rate of electrons can be further increased, thereby increasing the response speed of the three-dimensional memory 1.
Please refer to fig. 11 and 12 together. Fig. 11 is a process flow diagram included in step S500 in fig. 1. Fig. 12 is a schematic structural diagram of the three-dimensional memory corresponding to step S510 in fig. 11.
In this embodiment, the step S500 "of etching the protection layer 60 corresponding to the first conductive connection 220 to expose at least a portion of the etch stop layer 50" includes the step S510 shown in fig. 12.
Referring to fig. 12, S510, the protection layer 60 and the etch stop layer 50 corresponding to the first conductive connection 220 are etched to expose at least a portion of the etch stop layer 50, and the etching parameters are controlled to form a recess 51 on the surface of the etch stop layer 50.
In the present embodiment, after the etching of the passivation layer 60 corresponding to the first conductive connection 220 to expose the time barrier layer is performed by controlling the etching parameters (such as the concentration of the etching solution, the etching temperature, the etching time, and the like), the etching of a portion of the etching barrier layer 50 is started, and thus the recess 51 is formed on the surface of the etching barrier layer 50. By thinning the etching stopper layer 50 corresponding to the first conductive connector 220, the first conductive connector 220 can be more easily exposed when the etching stopper layer 50 is etched by wet etching, and lateral etching of the etching solution to the sidewall of the connection hole 41 can also be avoided.
Please refer to fig. 13-16 together. Fig. 13 is a process flow diagram included in step S400 in fig. 1. Fig. 14-16 are schematic structural diagrams of the three-dimensional memory corresponding to steps S410, S420, and S430 in fig. 13, respectively.
In this embodiment, S400 "sequentially forming the etching stopper layer 50 and the protective layer 60 on the hole wall of the connection hole 41" includes S410 to S430 shown in fig. 14 to 16.
Referring to fig. 14, S410, the etch stopper layer 50 is formed on the top surface of the interlayer insulating layer 40 and the hole wall of the connection hole 41.
Referring to fig. 15, S420, the etch stop layer 50 on the top surface of the interlayer insulating layer 40 is removed.
Referring to fig. 16, S430, the protective layer 60 is formed on the top surface of the interlayer insulating layer 40 and the surface of the etch stopper 50 in the connection hole 41.
This embodiment may first form the etch stopper layer 50 on the top surface of the interlayer insulating layer 40 and the hole wall of the connection hole 41, then remove the etch stopper layer 50 on the top surface of the interlayer insulating layer 40, and finally form the protective layer 60 on the top surface of the interlayer insulating layer 40 and the surface of the etch stopper layer 50 in the connection hole 41. This makes it possible to not only sequentially form the etch stopper layer 50 and the protective layer 60 on the hole wall of the connection hole 41 but also remove the etch stopper layer 50 on the top surface of the interlayer insulating layer 40, thereby reducing the total thickness of the three-dimensional memory 1 (i.e., the thickness of the etch stopper layer 50). In addition, the top surface of the present application refers to a side surface of the interlayer insulating layer 40 facing away from the substrate 10.
Please refer to fig. 17 and 18 together. Fig. 17 is a process flow diagram included in step S400 in fig. 1. Fig. 18 is a schematic structural diagram of the three-dimensional memory corresponding to step S440 in fig. 17.
In this embodiment, after forming the protective layer 60 "on the top surface of the interlayer insulating layer 40 and the surface of the etch stopper 50 in the connection hole 41" at S430 ", S440 shown in fig. 18 is further included.
Referring to fig. 18, S440, the protection layer 60 on the top surface of the interlayer insulating layer 40 is removed.
The present application may also remove the protective layer 60 on the top surface of the interlayer insulating layer 40 after removing the etch stop layer 50 on the top surface of the interlayer insulating layer 40, thereby further reducing the total thickness of the three-dimensional memory 1 (i.e., the thickness of the protective layer 60).
Please refer to fig. 19 and fig. 20 together. Fig. 19 is a process flow diagram included in step S300 in fig. 1. Fig. 20 is a schematic structural diagram of the three-dimensional memory corresponding to step S310 in fig. 19.
In this embodiment, the forming of the connection hole 41 penetrating the interlayer insulating layer 40 and the substrate 10 to expose the first conductive connection member 220 "at S300" includes S310 as shown in fig. 20.
Referring to fig. 20, S310, the interlayer insulating layer 40 and the substrate 10 corresponding to the first conductive connection element 220 are etched to form a connection hole 41 penetrating through the interlayer insulating layer 40 and the substrate 10, so as to expose the first conductive connection element 220, and an orthographic projection of the connection hole 41 on the substrate 10 covers an orthographic projection of the first conductive connection element 220 on the substrate 10.
The present embodiment increases the width of the connection hole 41 and makes the orthographic projection of the connection hole 41 on the substrate 10 cover the orthographic projection of the first conductive connector 220 on the substrate 10. In this way, a phenomenon in which the first conductive connector 220 is connected to the substrate 10 and thus short-circuited can be prevented. In addition, increasing the width of the connection hole 41 can increase the allowable offset range of the connection hole 41 and the first conductive connection element 220, and the first conductive connection element 220 can be more easily exposed again in a subsequent manufacturing process.
In addition to the above method for manufacturing a three-dimensional memory, the present application provides a three-dimensional memory. The three-dimensional memory and the preparation method of the three-dimensional memory provided by the embodiment of the application can achieve the technical effects of the application, the three-dimensional memory and the preparation method of the three-dimensional memory can be used together or independently, and the application is not particularly limited in this respect. For example, as one embodiment, the three-dimensional memory below may be fabricated using the method for fabricating a three-dimensional memory provided above.
Referring to fig. 21, fig. 21 is a schematic structural diagram of a three-dimensional memory according to a first embodiment of the present application. The three-dimensional memory 1 shown in fig. 21 includes a substrate 10, a memory portion 20, a control portion 30, an interlayer dielectric layer 212, and a conductive portion 90. The memory part 20 is provided with a first conductive connector 220 therein, and the memory part 20 and the control part 30 are sequentially stacked on one side of the substrate 10. The interlayer dielectric layer 212 is disposed on the other side of the substrate 10, and the conductive portion 90 is embedded in the interlayer dielectric layer 212 and the substrate 10 and corresponds to the first conductive connection element 220. The conductive part 90 includes a second conductive connector 70, and a protective layer 60 and an etching barrier layer 50 sequentially stacked on opposite sides of the conductive part 90, wherein the second conductive connector 70 is electrically connected to the first conductive connector 220. The control part 30 includes a third conductive connecting member 310 and a control device 300, the third conductive connecting member 310 is electrically connected to the control device 300, and the third conductive connecting member 310 is electrically connected to the first conductive connecting member 220.
The substrate 10, the memory portion 20, and the control portion 30 are described in detail above, and the description of the present application is omitted here. The interlayer dielectric layer 212 is disposed on the other side of the substrate 10, and mainly functions to insulate the substrate 10. The conductive portion 90 primarily ends up transmitting electrical signals. The conductive portion 90 is embedded in the interlayer dielectric layer 212 and the substrate 10, and it can also be understood that a connection hole 41 is formed in the interlayer dielectric layer 212 and the substrate 10, the conductive portion 90 is disposed in the connection hole 41, and the conductive portion 90 corresponds to the first conductive connection member 220. The conductive part 90 includes a second conductive connector 70, and a protective layer 60 and an etch stopper layer 50 sequentially stacked on opposite sides of the conductive part 90. The three-dimensional memory 1 provided by the embodiment has the advantages that the etching barrier layer 50 is additionally arranged on the two opposite sides of the second conductive connecting piece 70, the charged particles are prevented from being transmitted to the first conductive connecting piece 220 and then transmitted to the control device 300 in the preparation process, the influence on the normal use of the control device 300 is avoided, the service performances of the control device 300 and the three-dimensional memory 1 are improved, the service life of the three-dimensional memory is prolonged, and the three-dimensional memory has strong practicability.
Referring to fig. 22-25 together, fig. 22 is a schematic structural diagram of a three-dimensional memory according to a second embodiment of the present application. Fig. 23 is a schematic structural diagram of a three-dimensional memory according to a third embodiment of the present application. Fig. 24 is a schematic structural diagram of a three-dimensional memory according to a fourth embodiment of the present application. Fig. 25 is a schematic structural diagram of a three-dimensional memory according to a fifth embodiment of the present application. The three-dimensional memory 1 according to the second to fifth embodiments of the present application has substantially the same structure as the three-dimensional memory 1 according to the first embodiment of the present application, except that the insulating layer 80 includes the interlayer insulating layer 40 in the second to fifth embodiments. Alternatively, the insulating layer 80 may include any one or both of the etch stop layer 50 and the protective layer 60 provided on the top surface of the interlayer insulating layer 40, in addition to the interlayer insulating layer 40.
The insulating layer 80 mainly functions to insulate the substrate 10. As shown in fig. 22, the insulating layer 80 includes an interlayer insulating layer 40 and the etch stop layer 50 and the protection layer 60 disposed on the top surface of the interlayer insulating layer 40, so that the manufacturing steps are simplified, and the process time and the process cost are reduced. Under this structure, the etch stopper layer 50 and the protective layer 60 are sequentially stacked on the top surface of the interlayer insulating layer 40. Thus, in the preparation process, the etching barrier layer 50 and the protective layer 60 which are arranged on the top surface of the interlayer insulating layer 40, and the etching barrier layer 50 and the protective layer 60 which are arranged on the hole wall of the connecting hole 41 can be prepared through one preparation process, so that the preparation steps can be further simplified, and the process time and the process cost can be reduced.
As shown in fig. 23 and 24, the insulating layer 80 includes an interlayer insulating layer 40 and any one of the etch stopper layer 50 and the protective layer 60 provided on the top surface of the interlayer insulating layer 40, so that the total thickness of the three-dimensional memory 1 can be reduced. For example, as shown in fig. 23, only the etching stopper layer 50 is provided on the surface of the interlayer insulating layer 40. As shown in fig. 24, only the protective layer 60 is provided on the surface of the interlayer insulating layer 40. As shown in fig. 25, the insulating layer 80 includes only the interlayer insulating layer 40, and in this case, the interlayer insulating layer 40 is the insulating layer 80. This structure can further reduce the total thickness of the three-dimensional memory 1.
Please refer to fig. 26, fig. 26 is a schematic structural diagram of a three-dimensional memory according to a sixth embodiment of the present application. The structure of the three-dimensional memory 1 provided in the sixth embodiment of the present application is substantially the same as the structure of the three-dimensional memory 1 provided in the first embodiment of the present application, except that in this embodiment, the dimension of the second conductive connecting member 70 close to the substrate 10 is larger than the dimension of the second conductive connecting member 70 away from the substrate 10. In this embodiment, the size of the second conductive connection part 70 close to the substrate 10 is larger than the size of the second conductive connection part 70 away from the substrate 10, so that the contact area between the second conductive connection part 70 and the first conductive connection part 220 is increased, the electron transmission rate can be further increased, and the response speed of the three-dimensional memory 1 can be increased.
Referring to fig. 27, fig. 27 is a schematic circuit structure diagram of an electronic device according to an embodiment of the disclosure. The embodiment also provides an electronic device 3, wherein the electronic device 3 comprises a processor 2 and the three-dimensional memory 1 provided in the embodiment, and the processor 2 is used for writing data into the three-dimensional memory 1 and/or reading data from the three-dimensional memory 1.
The electronic device 3 provided in this embodiment may be a device having a storage device, such as an electronic computer, a smart phone, a smart television, a smart set-top box, a smart router, and an electronic digital camera. The electronic device 3 provided in the present embodiment generally further includes a processor 2, an input/output device, a display device, and the like. The three-dimensional memory 1 provided by the embodiment is manufactured by processes such as packaging and the like to form a storage device such as a flash memory, and the storage device is used for storing files or data and is called by the processor 2. The processor 2 may write data into the storage device, that is, the three-dimensional memory 1 provided in the present embodiment, or may read data from the storage device, that is, the three-dimensional memory 1 provided in the present embodiment. The input/output device is used for inputting instructions or outputting signals, and the display device visualizes the signals to realize various functions of the electronic device 3. The electronic device 3 provided by the embodiment of the application greatly improves the service performance and the service life of the three-dimensional memory 1 and improves the service performance and the service life of the electronic device 3 by adopting the three-dimensional memory 1 provided by the embodiment of the application.
The foregoing detailed description has provided for the embodiments of the present application, and the principles and embodiments of the present application have been presented herein for purposes of illustration and description only and to facilitate understanding of the methods and their core concepts; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (12)
1. A method for preparing a three-dimensional memory, the method comprising:
providing a substrate, forming a storage part and a control part on one side of the substrate, and enabling the storage part to be electrically connected with the control part, wherein the storage part comprises a first conductive connecting piece;
forming an interlayer insulating layer on the other side of the substrate;
forming a connection hole penetrating the interlayer insulating layer and the substrate to expose the first conductive connection member;
forming an etching barrier layer and a protective layer on the hole wall of the connecting hole in sequence;
etching the protective layer corresponding to the first conductive connecting piece to expose at least part of the etching barrier layer;
etching the etching barrier layer by a wet etching method to expose at least part of the first conductive connecting piece again; and
and forming a second conductive connecting piece connected with the first conductive connecting piece in the connecting hole.
2. The method of claim 1, wherein etching the etch stop layer using a wet etch to re-expose at least a portion of the first conductive connection comprises:
etching the etching barrier layer corresponding to the first conductive connecting piece by using an etching solution, wherein the etching solution comprises phosphoric acid, the etching temperature is 150-.
3. The method of claim 2, wherein etching the etch stop layer using a wet etch to re-expose at least a portion of the first conductive connection comprises:
etching the etching barrier layer to expose at least part of the first conductive connecting piece again, and controlling etching parameters to enable the size of the connecting hole close to the substrate to be larger than the size of the connecting hole far away from the substrate.
4. The method of claim 1, wherein etching the protective layer corresponding to the first conductive connection to expose at least a portion of the etch stop layer comprises:
etching the protective layer and the etching barrier layer corresponding to the first conductive connecting piece to expose at least part of the etching barrier layer, and controlling etching parameters to enable the surface of the etching barrier layer to form a groove.
5. The method according to claim 1, wherein the forming an etching stopper layer and a protective layer in this order on the hole wall of the connection hole comprises:
forming the etch stopper layer on a top surface of the interlayer insulating layer and a hole wall of the connection hole;
removing the etch stop layer on the top surface of the interlayer insulating layer; and
forming the protective layer on a top surface of the interlayer insulating layer and a surface of the etch stopper layer within the connection hole.
6. The manufacturing method according to claim 5, further comprising, after "forming the protective layer on the top surface of the interlayer insulating layer and the surface of the etching stopper layer in the connection hole",: removing the protective layer on the top surface of the interlayer insulating layer.
7. The method of claim 1, wherein forming a connection hole through the interlayer insulating layer and the substrate to expose the first conductive connection member comprises:
etching the interlayer insulating layer and the substrate corresponding to the first conductive connecting piece to form a connecting hole penetrating through the interlayer insulating layer and the substrate, exposing the first conductive connecting piece, and enabling an orthographic projection of the connecting hole on the substrate to cover an orthographic projection of the first conductive connecting piece on the substrate.
8. A three-dimensional memory is characterized by comprising a substrate, a storage part, a control part, an insulating layer and a conduction part, wherein a first conductive connecting piece is arranged in the storage part, the storage part and the control part are sequentially stacked on one side of the substrate, the insulating layer is arranged on the other side of the substrate, the conduction part is embedded in the insulating layer and the substrate and corresponds to the first conductive connecting piece, the conduction part comprises a second conductive connecting piece, a protective layer and an etching barrier layer which are sequentially stacked on two opposite sides of the second conductive connecting piece, the second conductive connecting piece is electrically connected with the first conductive connecting piece, the control part comprises a third conductive connecting piece and a control device, the third conductive connecting piece is electrically connected with the control device, and the third conductive connecting piece is electrically connected with the first conductive connecting piece, the protective layer is used for protecting the substrate and the insulating layer, and the etching barrier layer is used for preventing charged particles from being transmitted to the control device through the first conductive connecting piece due to the fact that the first conductive connecting piece is directly exposed when the protective layer is subjected to dry etching.
9. The three-dimensional memory according to claim 8, wherein the insulating layer is an interlayer insulating layer; alternatively, the insulating layer includes an interlayer insulating layer and either one or both of the etch stopper layer and the protective layer provided on a top surface of the interlayer insulating layer.
10. The three-dimensional memory according to claim 9, wherein when the insulating layer includes an interlayer insulating layer and the etch barrier layer and the protective layer are provided on a top surface of the interlayer insulating layer, the etch barrier layer and the protective layer are sequentially stacked on the top surface of the interlayer insulating layer.
11. The three-dimensional memory of claim 8, wherein a dimension of the second conductive connection proximate to the substrate is greater than a dimension of the second conductive connection away from the substrate.
12. An electronic device comprising a three-dimensional memory according to any of claims 8-11 and a processor for writing data into and/or reading data from the three-dimensional memory.
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