CN110459536B - Manufacturing method of PIP capacitor - Google Patents
Manufacturing method of PIP capacitor Download PDFInfo
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- CN110459536B CN110459536B CN201910781804.2A CN201910781804A CN110459536B CN 110459536 B CN110459536 B CN 110459536B CN 201910781804 A CN201910781804 A CN 201910781804A CN 110459536 B CN110459536 B CN 110459536B
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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Abstract
The invention provides a manufacturing method of a PIP capacitor, which comprises the following steps: providing a substrate, wherein the substrate is divided into a storage area and a logic area, and a coupling oxide layer, a floating gate layer, a first dielectric layer, a control gate layer and floating gate silicon nitride are sequentially formed on the substrate; etching the floating gate silicon nitride by using the etching layout of the floating gate silicon nitride; forming a floating gate side wall covering the outer side of the etched floating gate silicon nitride, and forming a floating gate displacement side wall and a tunneling oxide layer covering the side wall of the floating gate; forming a word line; forming protective silicon nitride and protective silicon oxide to cover the word line; removing the protective silicon nitride and the protective silicon oxide in the logic area, and partially etching the floating gate silicon nitride; forming a logic gate silicon oxide in the logic area to cover the etched floating gate silicon nitride and the word line; and forming logic gate polysilicon to cover the logic gate silicon oxide. According to the invention, the floating gate silicon nitride is etched by adding the etching layout of the floating gate silicon nitride, so that a smooth polycrystalline silicon surface can be obtained.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a PIP capacitor.
Background
A PIP (poly-insulator-poly) capacitor is a device widely used to prevent analog circuit emission noise and frequency modulation. The PIP capacitor is commonly used in an embedded flash memory process with multiple layers of polysilicon, and the area of a chip can be effectively reduced due to the large capacitance per unit area. In the embedded flash memory process, word line poly-silicon (word line poly-silicon) and logic gate poly-silicon (gate poly-silicon) and High voltage gate oxide (High voltage gate-oxide) are commonly used to form the PIP structure. Currently, in the 90nm NORD flash process platform, since Word line Poly-Silicon (Word line Poly-Silicon) uses a chemical mechanical polishing process (CMP) to remove the Poly-Silicon in the region other than the Word line. Since the CMP process causes large dishing (dishing) in bulk removal regions (e.g., poly-silicon), which results in a failure to obtain a planar polysilicon plane.
Disclosure of Invention
The invention aims to provide a manufacturing method of a PIP capacitor, which can obtain a flat polysilicon surface.
In order to achieve the above object, the present invention provides a method for manufacturing a PIP capacitor, including:
providing a substrate, wherein the substrate is divided into a storage area and a logic area, and a coupling oxide layer, a floating gate layer, a first dielectric layer, a control gate layer and floating gate silicon nitride are sequentially formed on the substrate;
etching the floating gate silicon nitride by using the etching layout of the floating gate silicon nitride;
forming a floating gate side wall covering the outer side of the etched floating gate silicon nitride, and forming a floating gate displacement side wall and a tunneling oxide layer covering the floating gate side wall;
forming a word line;
forming protective silicon nitride and protective silicon oxide to cover the word lines;
removing the protective silicon nitride and the protective silicon oxide in the logic area, and partially etching the floating gate silicon nitride;
forming a logic gate oxide silicon in the logic area to cover the etched floating gate silicon nitride and the word line;
and forming logic gate polysilicon to cover the logic gate silicon oxide.
Optionally, in the manufacturing method of the PIP capacitor, the floating gate layer and the control gate layer are polysilicon.
Optionally, in the method for manufacturing a PIP capacitor, the etching layout of the floating gate silicon nitride includes a strip-shaped etching layout of the floating gate silicon nitride and a dot-shaped etching layout of the floating gate silicon nitride.
Optionally, in the method for manufacturing a PIP capacitor, a plurality of array strip patterns are provided in a frame of the strip-shaped floating gate silicon nitride etching layout, and the width of each strip pattern is 0.2um to 0.4 um.
Optionally, in the method for manufacturing the PIP capacitor, a gap between adjacent bar patterns is between 5um and 10 um.
Optionally, in the method for manufacturing the PIP capacitor, a distance between the bar pattern close to the frame and the frame is between 0.3um and 0.5 um.
Optionally, in the method for manufacturing a PIP capacitor, a plurality of arrayed dot patterns are provided in a frame of the etching layout of the dot floating gate silicon nitride, and each dot pattern is square.
Optionally, in the method for manufacturing a PIP capacitor, the size of the dot pattern is between 0.2um and 0.4 um.
Optionally, in the method for manufacturing the PIP capacitor, a distance between the dot pattern close to the frame and the frame is between 0.3um and 0.5 um.
Optionally, in the method for manufacturing a PIP capacitor, the coupling oxide layer is silicon dioxide.
In the manufacturing method of the PIP capacitor provided by the invention, the strip-shaped or point-shaped floating gate silicon nitride etching layout is added, so that a plurality of strip-shaped or point-shaped floating gate silicon nitrides are formed by etching, and a flat polysilicon surface can be obtained in the subsequent grinding of polysilicon.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a PIP capacitor according to an embodiment of the present invention;
fig. 2-10 are cross-sectional views illustrating a method of fabricating a PIP capacitor according to an embodiment of the present invention;
fig. 11 is an etching layout of floating gate silicon nitride according to the first embodiment of the present invention;
FIG. 12 is an etching layout of floating gate silicon nitride according to the second embodiment of the present invention;
in the figure: 100-substrate, 101-coupling oxide layer, 102-floating gate layer, 103-first dielectric layer, 104-control gate layer, 105-floating gate silicon nitride, 106-floating gate side wall, 107-floating gate displacement side wall, 108-tunneling oxide layer, 109-word line, 110-protective silicon nitride, 111-protective silicon oxide, 112-logic gate silicon oxide, 113-logic gate polysilicon and 201-photoresist.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the present invention provides a method for manufacturing a PIP capacitor, including:
s11: providing a substrate, wherein the substrate is divided into a storage area and a logic area, and a coupling oxide layer, a floating gate layer, a first dielectric layer, a control gate layer and floating gate silicon nitride are sequentially formed on the substrate;
s12: etching the floating gate silicon nitride by using the etching layout of the floating gate silicon nitride;
s13: forming a floating gate side wall covering the outer side of the etched floating gate silicon nitride, and forming a floating gate displacement side wall and a tunneling oxide layer covering the floating gate side wall;
s14: forming a word line;
s15: forming protective silicon nitride and protective silicon oxide to cover the word lines;
s16: removing the protective silicon nitride and the protective silicon oxide in the logic area, and partially etching the floating gate silicon nitride;
s17: forming a logic gate oxide silicon in the logic area to cover the etched floating gate silicon nitride and the word line;
s18: and forming logic gate polysilicon to cover the logic gate silicon oxide.
Referring to fig. 2, a substrate 100 is provided, the substrate is divided into a storage region and a logic region, a coupling oxide layer 101 and a floating gate layer 102, a first dielectric layer 103, a control gate layer 104 and a floating gate silicon nitride 105 are sequentially formed on the substrate, and the first dielectric layer 103 is an ONO layer, that is, a silicon oxide-silicon nitride-silicon oxide.
Referring to fig. 3, an etching layout of the floating gate silicon nitride is added, the floating gate silicon nitride 105 is etched by using the photoresist 201, and the floating gate silicon nitride 105 is in a columnar shape after the etching is completed. Compared with the prior art, the floating gate silicon nitride 105 is etched in the logic area, an etching layout is added in the embodiment of the invention, a plurality of point-like or strip-shaped graphs are arranged in a frame of the etching layout, in the first embodiment, as shown in fig. 11, the width of each strip-shaped graph is 0.2 um-0.4 um, the gap between every two adjacent strip-shaped graphs is 5 um-10 um, and the minimum distance between each strip-shaped graph and the frame is 0.4 um. In the second embodiment of the present invention, the dot pattern is a square, and the length of the dot pattern is 0.2um to 0.4 um. The minimum distance between the dot pattern and the frame is 0.4 um. The etching layout is used for etching the floating gate silicon nitride 105, and the top view of the etched floating gate silicon nitride 105 is also in a strip or point pattern. The strip-shaped and point-shaped characteristics meet the requirements of etching the strip-shaped and point-shaped characteristics in the layout.
Referring to fig. 4, floating gate silicon oxide is deposited to cover the etched floating gate silicon nitride 105 and the control gate layer 104, and the floating gate silicon nitride is etched to expose the surface of the control gate layer 104, so as to form floating gate side walls 106 located at two sides of the floating gate silicon nitride 105.
Referring to fig. 5, the control gate layer 104 and the first dielectric layer 103 are etched with the floating gate sidewall 106 as a reference, and the control gate layer 104 and the first dielectric layer 103 outside the floating gate sidewall 106 are etched to form the control gate layer 104 and the patterned first dielectric layer 103, exposing the surface of the floating gate layer 102.
With continued reference to fig. 5, a second silicon nitride layer is deposited and etched to form a floating gate displacement sidewall 107 on the sidewalls of the floating gate sidewall 106, the control gate layer 104 and the patterned first dielectric layer 103A, wherein the floating gate displacement sidewall 107 surrounds the floating gate sidewall 106, the control gate layer 104 and the sidewalls of the patterned first dielectric layer 103A.
Referring to fig. 6, the floating gate layer 102 and the coupling oxide layer 101 are etched with the floating gate displacement spacers 107 as a reference to expose the surface of the substrate 100, and a tunnel oxide layer 108 is deposited to cover the substrate 100, the floating gate displacement spacers 107, the floating gate layer 102 and the side walls of the coupling oxide layer 101. Next, a polysilicon layer is deposited to cover the tunnel oxide layer 108, the floating gate silicon nitride 105, the floating gate sidewall spacers 106 and the floating gate displacement sidewall 107.
Referring to fig. 7 and 8, the surface of the polysilicon layer exposed by the floating gate silicon nitride 105 is polished to form a word line 109. In the prior art, the polysilicon forming the word line on the 90nm flash process platform adopts a CMP process to remove the redundant polysilicon on the floating gate silicon nitride. In the memory array, there is no problem because the pattern is more densely polished, but in the bulk region for the capacitor, if there is no pattern support in the middle, a deep recess is formed due to the loading effect of CMP, and the deepest portion may wear all the word line polysilicon through and damage the underlying dielectric layer. In the embodiment of the invention, the floating gate silicon nitride etched by the dot-shaped or strip-shaped floating gate silicon nitride etching layout is added and can be used as a supporting point in the CMP process so as to avoid the problem and obtain a smoother word line polycrystalline silicon surface. The surface of the word line 109 is oxidized to protect the word line 109, and a protective silicon nitride 110 and a protective silicon oxide 111 are sequentially formed to cover the word line 109 and the floating gate silicon nitride 105.
Referring to fig. 9, the protective silicon oxide 111 and the protective silicon nitride 110 in the logic region are removed by etching (the protective silicon oxide 111 and the protective silicon nitride 110 in the flash memory region remain), the floating gate silicon nitride 105 in a part of the logic region is etched to reduce its thickness, and forms a concave shape with the floating gate spacers 106 on both sides.
Referring to fig. 10, a logic gate oxide silicon 112 and a logic gate polysilicon 113 are then deposited, respectively, the logic gate oxide silicon 112 covering the remaining floating gate nitride silicon 105 and the word line 109, and the logic gate polysilicon 113 covering the logic gate oxide silicon 112. And etching the logic area to form a contact hole.
In summary, in the method for manufacturing a PIP capacitor according to the embodiment of the present invention, the strip-shaped or dot-shaped floating gate silicon nitride etching layout is added, so that a plurality of strip-shaped or dot-shaped floating gate silicon nitrides are formed by etching, and a flat polysilicon surface can be obtained during subsequent polysilicon grinding.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A manufacturing method of a PIP capacitor is characterized by comprising the following steps:
providing a substrate, wherein the substrate is divided into a storage area and a logic area, and a coupling oxide layer, a floating gate layer, a first dielectric layer, a control gate layer and floating gate silicon nitride are sequentially formed on the substrate;
partially etching the floating gate silicon nitride of the logic area by using the etching layout of the floating gate silicon nitride to obtain the floating gate silicon nitride with a strip-shaped top view or the floating gate silicon nitride with a dot-shaped top view;
forming a floating gate side wall covering the outer side of the floating gate silicon nitride, partially etching the control gate layer and the first dielectric layer, forming a floating gate displacement side wall covering the floating gate side wall, the control gate layer and the first dielectric layer, etching the floating gate layer and the coupling oxide layer, and forming a tunneling oxide layer covering the floating gate displacement side wall, the floating gate layer and the coupling oxide layer;
forming word line polysilicon covering the floating gate silicon nitride and the tunneling oxide layer, and grinding the word line polysilicon to form a word line;
forming protective silicon nitride and protective silicon oxide to cover the word lines;
removing the protective silicon nitride and the protective silicon oxide in the logic area, and partially etching the floating gate silicon nitride;
forming a logic gate oxide silicon in the logic area to cover the etched floating gate silicon nitride and the word line;
and forming logic gate polysilicon to cover the logic gate silicon oxide.
2. The method of fabricating a PIP capacitor of claim 1, wherein the floating gate layer and the control gate layer are polysilicon.
3. The method for manufacturing a PIP capacitor of claim 1, wherein the floating gate silicon nitride etching layout includes a strip-shaped floating gate silicon nitride etching layout and a dot-shaped floating gate silicon nitride etching layout.
4. The method for manufacturing a PIP capacitor according to claim 3, wherein a plurality of arrays of strip patterns are provided in a frame of the strip-shaped etching layout of the floating gate silicon nitride, and the width of each strip pattern is between 0.2um and 0.4 um.
5. The method of claim 4, wherein a gap between adjacent strips is between 5um and 10 um.
6. The method of claim 5, wherein a distance between the bar pattern adjacent to the frame and the frame is between 0.3um and 0.5 um.
7. The method for manufacturing a PIP capacitor of claim 3, wherein a plurality of arrays of dot patterns are arranged in a frame of the etching layout of the dot-shaped floating gate silicon nitride, and each dot pattern is a square.
8. The method of claim 7, wherein the dot pattern has a size of 0.2um to 0.4 um.
9. The method of claim 8, wherein a distance between the dot pattern near the frame and the frame is between 0.3um and 0.5 um.
10. The method of claim 1, wherein the coupling oxide layer is silicon dioxide.
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| CN201910781804.2A CN110459536B (en) | 2019-08-23 | 2019-08-23 | Manufacturing method of PIP capacitor |
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