CN110459252A - The operating method of semiconductor devices and semiconductor devices - Google Patents
The operating method of semiconductor devices and semiconductor devices Download PDFInfo
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- CN110459252A CN110459252A CN201910015412.5A CN201910015412A CN110459252A CN 110459252 A CN110459252 A CN 110459252A CN 201910015412 A CN201910015412 A CN 201910015412A CN 110459252 A CN110459252 A CN 110459252A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Bipolar Transistors (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The operating method of semiconductor devices and semiconductor devices.A kind of semiconductor devices includes memory string, which is connected between common source line and bit line, and the memory string includes at least one first choice transistor, multiple storage units and multiple second selection transistors.The semiconductor devices further includes the selection line for being individually connected to second selection transistor.The semiconductor devices further includes control logic circuit, the control logic circuit is configured as making the first group selection line in the selection line floating at the first time, and is configured as keeping the second group selection line in the selection line floating in the second time for being different from the first time.
Description
Technical field
Each embodiment of the disclosure is related to electronic device, and more particularly, to semiconductor devices and operation half
The method of conductor device.
Background technique
Semiconductor storage unit is such using such as silicon (Si), germanium (Ge), GaAs (GaAs) and indium phosphide (InP)
Memory device made of semiconductor material.Semiconductor storage unit is divided into volatile memory device and nonvolatile memory
Part.
Volatile memory device loses stored data in the event of a power failure.The example of volatile memory device
It may include static RAM (SRAM), dynamic ram (DRAM) and synchronous dram (SDRAM).Nonvolatile semiconductor memory member can not have
Stored data are kept in the case where having electric power.The example of nonvolatile semiconductor memory member includes read-only memory (ROM), can compile
Journey ROM (PROM), erasable programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, phase transformation
Random storage accesses memory RAM (PRAM), magnetic ram (MRAM), resistance RAM (RRAM) and ferroelectric RAM (FRAM).Flash is deposited
Reservoir is divided into NOR type memory and nand type memory.
Summary of the invention
According to an embodiment, a kind of semiconductor devices may include the storage being connected between common source line and bit line
Device string, the memory string include at least one first choice transistor, multiple storage units and multiple second selection transistors.
The semiconductor devices can also include the selection line for being individually connected to the second selection transistor.The semiconductor devices can be with
Including control logic circuit, which is configured as making to be each coupled to the second selection crystal at the first time
The first group selection line in second selection line of pipe is floating, and is configured as when being different from the second of the first time
Between keep the second group selection line in second selection line floating.
According to another embodiment, a kind of semiconductor devices may include the storage being connected between common source line and bit line
Device string, and the memory string includes that at least one first choice transistor, multiple storage units and multiple second selections are brilliant
Body pipe.The semiconductor devices can also include control logic circuit, which be configured as to the multiple the
First group of second selection transistor in two selection transistors applies first grid induced drain leakage (GIDL) biasing, and
Second group of second selection transistor in the multiple second selection transistor is configured as to apply and the first GIDL
Bias different the 2nd GIDL biasings.
According to other embodiment, a kind of semiconductor devices may include being connected between common source line and bit line
Memory string, the memory string respectively include at least one first choice transistor, multiple storage units and multiple second choosings
Select transistor.It is a kind of operate semiconductor devices method include into the common source line and the bit line at least one apply
Erasing voltage.This method further includes making individually to be connected in the selection line of second selection transistor at the first time
First group selection line is floating.This method further includes making individually to be connected to described in the second time for being different from the first time
The second group selection line in the selection line of second selection transistor is floating.
Detailed description of the invention
Attached drawing is incorporated into the specification together with specific embodiment below and is formed part of specification, and uses
The embodiment of the design including novelty claimed is illustrated in further, and illustrates the various of these embodiments
Principle and advantage, in the accompanying drawings, similar appended drawing reference refer to similar in identical or function in all different views
Element.
Fig. 1, which is shown, illustrates the block diagram of the configuration of the storage system according to embodiment of the present disclosure.
Fig. 2A, Fig. 2 B and Fig. 2 C, which are shown, illustrates the cell array knot of the semiconductor devices according to embodiment of the present disclosure
The circuit diagram of structure.
Fig. 3, which is shown, illustrates the flow chart of the method for the operation semiconductor devices according to embodiment of the present disclosure.
Fig. 4 A and Fig. 4 B, which are shown, illustrates the timing of the method for the operation semiconductor devices according to embodiment of the present disclosure
Figure.
Fig. 5 A and Fig. 5 B show the method for being grouped multiple selection transistors illustrated according to embodiment of the present disclosure
Figure.
Fig. 6, which is shown, illustrates the circuit diagram of the cell array structure of the semiconductor devices according to embodiment of the present disclosure.
Fig. 7, which is shown, illustrates the circuit diagram of the cell array structure of the semiconductor devices according to embodiment of the present disclosure.
Fig. 8 A, Fig. 8 B and Fig. 8 C, which are shown, illustrates the section of the structure of the semiconductor devices according to embodiment of the present disclosure
Figure.
Fig. 9, which is shown, illustrates the block diagram of the configuration of the storage system according to embodiment of the present disclosure.
Figure 10, which is shown, illustrates the block diagram of the configuration of the storage system according to embodiment of the present disclosure.
Figure 11, which is shown, illustrates the block diagram of the configuration of the computing system according to embodiment of the present disclosure.
Specific embodiment
Each embodiment of this introduction can be related to reliability and improve and the increased semiconductor devices of service speed and behaviour
Make the method for the semiconductor devices.
Describe example embodiment with reference to the accompanying drawings.However, embodiment can be implemented and not in different ways
It should be understood that and be limited to embodiment described herein.On the contrary, providing these embodiments, enable the disclosure for this
Used in the technical staff of field.Each embodiment is described in detail referring to attached drawing.In the following description, in order to concise,
It can be omitted the detailed description to correlation function and composition.In addition, embodiment can implement in different ways and
It should not be construed as limited to embodiment presented herein.
In the present specification, " connection/connection " refers to that a component is not only directly coupled to another component, but also passes through
Intermediate module is coupled indirectly to another component.In the description, when element is referred to as " include " or " contain " component, not
Have and exclude other components, and the element can also include other components, unless opposite instruction is made in associated description.
Fig. 1, which is shown, illustrates the block diagram of the configuration of the semiconductor devices 100 according to embodiment.Referring to Fig.1, semiconductor device
Part 100 may include cell array 110 and peripheral circuit 120.
Cell array 110 can be connected to address decoder 121 by line RL, and by alignment CL be connected to reading and
Write circuit 123.Line RL can be leakage selection line, wordline or source selection line, and alignment CL can be bit line.In addition, read and
Write circuit 123 can be page buffer.
Cell array 110 may include multiple memory strings, and the multiple memory string can be disposed in relatively
In in the horizontal direction of substrate or vertical direction.In addition, cell array 110 may include multiple memory blocks, and the multiple
Each of memory block may include multiple pages.For example, semiconductor devices 100 can execute erasing behaviour as unit of memory block
Make, and it can execute programming operation or read operation as unit of page.
Peripheral circuit 120 may include address decoder 121, reading and write circuit 123, input/output (I/O) circuit 124
With control logic circuit 125.
Control logic circuit 125 can be connected to address decoder 121, reading and write circuit 123 and input/output circuitry
124.Control logic circuit 125 can receive order CMD and address AD DR from input/output circuitry 124, and controllably
It location decoder 121 and reads and write circuit 123 in response to the order CMD that receives executes internal operation.
When executing erasing operation, control logic circuit 125 can make in different times selection line floating.For example, control
Logic circuit 125 processed can make at the first time first in selection line group it is floating, and can be different from the first time
The second time make second group in selection line it is floating.In other words, control logic circuit 125 can make some selection lines
Floating time delay.Selection line can be either or both of source selection line and leakage selection line.
Grid induction drain leakage (GIDL) biasing can be applied to choosing during erasing operation by control logic circuit 125
Select transistor.GIDL biasing can be the reverse bias for generating GIDL electric current in selection transistor, and can refer to
Voltage difference between the gate terminal and source terminal of selection transistor.Control logic circuit 125 can work as to selection transistor
In first group of the first GIDL of application biasing, and in selection transistor second group of the 2nd GIDL of application biasing.Change sentence
Words say that control logic circuit 125 can be applied to some GIDL biasings in selection transistor and increase.Herein, it selects
Transistor can be either or both of source selection line and leakage selection line.
According to above-mentioned control method, the GIDL electric current generated during erasing operation can be made to increase.Therefore, it can wipe
To the hole of storage unit supply sufficient amount during operation, and the operating characteristic of semiconductor devices 100 can be improved.Separately
Outside, it can prevent the threshold voltage of selection transistor from changing because of hot carrier in jection (HCI).Therefore, it can be improved semiconductor
The reliability of device 100.
Address decoder 121 can be connected to cell array 110 by line RL, and in response to control logic circuit
125 control and control line RL.Therefore, address decoder 121 can receive address AD DR from control logic circuit 125, and
And the address AD DR in response to receiving and one in the memory block of selecting unit array 110.
Programming operation and the read operation of semiconductor devices 100 can be executed using page as unit.Therefore, in programming operation and reading
During operation, address AD DR may include block address and row address.Address decoder 121 can be to the block for including in the ADDR of address
Address is decoded, and selects according to decoded block address one in memory block.Address decoder 121 can dock
The row address for including in the address AD DR received is decoded, and selected storage is selected according to decoded row address
One in the page of block.
The erasing operation of semiconductor devices 100 can be executed using memory block as unit.Therefore, during erasing operation, ground
Location ADDR may include block address.Address decoder 121 can be decoded block address, and according to decoded block address
To select one in memory block.
It reads and write circuit 123 can be coupled by alignment CL with cell array 110.During programming operation, electricity is read and write
The data DATA received from input/output circuitry 124 can be transmitted to alignment CL by road 123, and be can use and transmitted
Data DATA the storage unit of selected page is programmed.During read operation, reads and write circuit 123 can pass through column
Line CL reads data DATA from the storage unit of selected page, and read data DATA is output to input/output
Circuit 124.In erasing operation, reads and erasing voltage can be applied to alignment CL by write circuit 123.
Fig. 2A, Fig. 2 B and Fig. 2 C, which are shown, illustrates the unit battle array of the semiconductor devices 100 according to embodiment of the present disclosure
The circuit diagram of array structure.Fig. 2 B shows the region A of Fig. 2A, and Fig. 2 C shows the region B of Fig. 2A.
It can be connected between bit line BL and common source line CSL referring to Fig. 2A, memory string MS.In addition, memory string
MS may include at least one leakage selection transistor DST, multiple storage unit MC and the choosing of at least one source being coupled to one another in series
Select transistor SST.Although not showing in fig. 2, memory string MS can also include between multiple storage unit MC
Tubular type transistor.
Wordline WL can be connected to the grid of storage unit MC.Leakage selection line DSL can be connected to leakage selection transistor DST
Grid, and control the connection between memory string MS and bit line BL.Leakage selection line DSL can be connected to source selection transistor
The grid of SST, and control the connection between memory string MS and common source line CSL.
Number including the source selection transistor SST in a memory string MS can be with leakage selection transistor DST's
Number is identical or different.The number of source selection transistor SST can be greater than the number of leakage selection transistor, or leakage selection crystal
The number of pipe DST can be greater than the number of source selection transistor SST.For example, a memory string MS may include seven source choosings
Select transistor SST and three leakage selection transistor DST.
At least one of source selection transistor SST can be illusory source selection transistor, and leak selection transistor DST
At least one of can be illusory leakage selection transistor.
Referring to Fig. 2 B, a memory string MS may include multiple source selection transistor SST1 to SSTN, and a plurality of source
Selection line SSL1 to SSLN can be respectively coupled to the grid of multiple source selection transistor SST1 to SSTN.
Source selection line SSL1 to SSLN can be grouped into multiple groups of G1 to GM, and each of organizing G1 to GM can be with
Including source selection line SSL1 into SSLN at least one.For example, the first source selection line SSL1 to the source J selection line SSLJ can be with
Belong to first group of G1, and the source K selection line SSLK to the source N selection line SSLN may belong to M group GM.In addition, group G1 is extremely
GM may include the different source selection line of number (SSL1 to SSLN).In an identical manner, source selection transistor SST1 to SSTN
Each of multiple groups of G1 to GM can be divided into, and organize G1 to GM may include source selection transistor SST1 to SSTN
At least one of.Here, J, K, M and N can be the integer of two or more, so that meeting J < K < N.
At least one of group G1 to GM may include illusory source selection transistor.For example, opposite with wordline WL adjacent
Group G1 may include illusory source selection transistor.In addition, including the source selection transistor SST1 to SSTJ in corresponding group of G1
All or part can be illusory source selection transistor.
Referring to Fig. 2 C, a memory string MS may include multiple leakage selection transistor DST1 to DSTP, and a plurality of leakage
Selection line DSL1 to DSLP can be respectively coupled to the grid of multiple leakage selection transistor DST1 to DSTP.
Leakage selection line DSL1 to DSLP each of can be grouped into multiple groups of G1 to GL, and organize G1 to GL can be with
Including leaking selection line DSL1 at least one into DSLP.For example, the first leakage selection line DSL1 to J leakage selection line DSLJ can be with
Belong to first group of G1, and K leakage selection line DSLK to P leakage selection line DSLP may belong to L group GL.In addition, group G1 is extremely
GL may include the different leakage selection line of number (DSL1 to DSLP).In an identical manner, leakage selection line DST1 to DSTP can be with
Each of be grouped into multiple groups of G1 to GL, and organize G1 to GL may include leakage selection transistor DST1 into DSTP
At least one.Here, J, K, L and P can be the integer of two or more, so that meeting J < K < P.
At least one of group G1 to GL may include illusory leakage selection transistor.For example, organizing in G1 to GL and word
Line WL relatively adjacent group G1 may include illusory leakage selection transistor.In addition, including the leakage selection crystalline substance in corresponding group of GL
The all or part of body pipe DSTK to DSTP can be illusory leakage selection transistor.
The number of the group G1 to GM of source selection line SSL1 to SSLN corresponding with a memory string MS can be selected with leakage
The number of the group G1 to GL of line DSL1 to DSLP is identical or different.For example, source selection line SSL1 to SSLN can be grouped into two
Group, and leak selection line DSL1 to DSLP and can be grouped into single group.
As used in this article, " selection line " can refer to source selection line or leakage selection line.Similarly, " selection transistor "
It can refer to source selection transistor or leakage selection transistor.In addition, a group selection transistor may include multiple selection transistors
Or only one selection transistor.For example, a group selection transistor may include one or more source selection transistors or
One or more leakage selection transistors.In some embodiments, selection line is individually connected to selection transistor instruction selection
One-to-one connection between line and selection transistor.Hardware, software, or its combination can be used to realize control logic circuit.Separately
Outside, as that can refer to single circuit, compound circuit, processor for the control logic circuit that some embodiments use herein
Or combinations thereof.The smaller electricity along memory string is indicated such as the wording " closer to " used herein for some embodiments
Gas distance.For example, first choice line means between first choice line and source selection line than the second selection line closer to source selection line
The electrical distance along memory string less than the electrical distance along memory string between the second selection line and source selection line.
Fig. 3, which is shown, illustrates the flow chart of the method for the operation semiconductor devices according to embodiment.Hereinafter, referring to Fig. 2 B
Shown in cell array 110 description to multiple source selection lines grouping made of two groups execute erasing operation.
Firstly, applying erasing voltage V_ERS (S310) to common source line CSL.Can to source selection line SSL1 to SSLN and
Wordline WL applies ground voltage.Then, make source selection line SSL1 in first group of G1 in the selection line SSL1 to SSLN of source extremely
SSLJ floating (S320).Then, make the source selection line SSLK to SSLN in second group of G2 in the selection line SSL1 to SSLN of source
Floating (S330).
According to above-mentioned operating method, the source selection transistor (gate terminal and source terminal of SST1 to SSTN) can be passed through
Voltage difference (that is, GIDL is biased) between son generates GIDL electric current.The hole generated by GIDL electric current can flow into storage unit
It in the channel of MC and is tunneling in the data storage layer of each storage unit MC, the data of storage unit MC is wiped
It removes.
In addition, the source selection line SSLK to SSLN in selection line SSL1 to SSLJ and second groups of source G2 in first group of G1 can
Not by floating simultaneously.Second group of the floating of G2 can be delayed by.Therefore, by source selection transistor corresponding with second group of G2
The GIDL electric current that SSTK to SSTN is generated can increase.In other words, the hole generated by source selection transistor SSTK to SSTN
Amount can increase.However, first group of the floating of G1 can also be delayed by.As a result, it is possible to prevent the selection of the source as caused by HCI brilliant
The variation of the threshold voltage of body pipe SST1 to SSTJ.
In this embodiment, the side that erasing operation is executed to group made of source selection line SSL1 to SSLN grouping is described
Method.However, the erasing operation method is equally applicable to leakage selection line DSL1 to DSLP.It is wiped for example, can apply to bit line BL
Voltage V_ERS, and leakage selection line DSL1 to DSLP can be made floating by group.Therefore, leakage selection transistor DST1 can be controlled
To GIDL biasing, GIDL electric current and the threshold voltage variation of DSTP.
In addition, in this embodiment, source selection line SSL1 to SSLN can be grouped into two groups.However, source selection line
SSL1 to SSLN can be grouped into three groups or more.
Fig. 4 A and Fig. 4 B, which are shown, illustrates the timing of the method for the operation semiconductor devices according to embodiment of the present disclosure
Figure.Hereinafter, two groups made of the grouping of multiple source selection lines are held in the description of cell array 110 shown in B referring to Figures 1 and 2
Capable erasing operation.
Referring to Fig. 4 A, erasing voltage V_ERS can be applied to common source line CSL in first time T1.As shown, it wipes
Except the current potential of voltage V_ERS can increase step by step.It can be to the source selection line SSL1 in first group of G1 and second group of G2 extremely
SSLN and wordline WL applies ground voltage GND.
The source selection line SSL1 to SSLJ in first group of G1 can be kept floating in the second time T2.Therefore, work as erasing voltage
When the current potential of V_ERS increases, the current potential of source selection line SSL1 to SSLJ can also be increased by connection.In other words, second
Voltage difference between the gate terminal and source terminal of the source selection transistor SST1 to each of SSTJ of time T2 can be with
It is kept, and the first GIDL biasing can be applied to source selection transistor SST1 to SSTJ.
However, still ground voltage can be applied to the source selection line SSLK to SSLN in second group of G2.Therefore, with wiping
Except the current potential of voltage V_ERS increases, the gate terminal and source terminal of source selection transistor SSTK to each of SSTN it
Between voltage difference also will increase.
The source selection line SSLK to SSLN in second group of G2 can be kept floating in third time T3.Therefore, work as erasing voltage
When the current potential of V_ERS increases, the current potential of source selection line SSLK to SSLN can also be increased by connection.In other words, third
Voltage difference between the gate terminal and source terminal of the source selection transistor SSTK to each of SSTN of time T3 can be with
It is kept, and the 2nd GIDL biasing can be applied to source selection transistor SSTK to SSTN.
It can no longer increase and can be kept in the current potential of the 4th time T4, erasing voltage V_ERS.
According to above-mentioned condition, GIDL electric current can be generated by source selection transistor SST1 to SSTN, and can pass through to
Storage unit supplies hole to wipe data.
In addition, erasing voltage V_ERS can increase in period T1 to during T4, and source selection line SSL1 to SSLN can be with
It is floated into T4 in period T1.It can be controlled according to source selection line SSL1 to the SSLN floated time and be applied to source selection
The GIDL bias of transistor SST1 to SSTN.
For example, source selection transistor SSTK is every into SSTN as second group of G2 floated floating time is delayed by
Voltage difference between one gate terminal and source terminal can increase.Therefore, compared with first group of G1, it is applied to second group
The GIDL biasing of the source selection transistor SSTK to SSTN of G2 can further increase, and the source selection transistor of second group of G2
The GIDL electric current that SSTK is generated into SSTN can selectively be increased.In other words, by the source adjacent with common source line CSL
The amount in the hole that selection transistor SSTK to SSTN is generated can increase.
Although the embodiment of Fig. 4 B is similar to the embodiment of Fig. 4 A, first group of G1 can be made in a different order
It is floating with second group of G2.More specifically, referring to Fig. 4 B the source selection line SSLK in second group of G2 can be made extremely in first time T1
SSLN is floating, and the source selection line SSL1 to SSLJ in first group of G1 can be kept floating in the second time T2.
As described above, when the source selection line SSL1 to SSLJ in first group of G1 floating is delayed by, it can be to first group
Source selection transistor SST1 to SSTJ in G1 applies high GIDL biasing.As a result, the GIDL biasing for being applied to first group of G1 can be with
Relative increase, and the GIDL bias for being applied to second group of G2 opposite can reduce.In addition, the source in second group of G2 can be made to select
The bias difference selected between line SSLK to SSLN and common source line CSL reduces, and can make the source selection line in first group of G1
Bias difference between SSL1 to SSLJ and wordline WL reduces.As a result, it is possible to prevent HCI, and can prevent as caused by HCI with
The variation of the threshold voltage of wordline WL adjacent source selection transistor SSTK to SSTN.
In this embodiment, the side that erasing operation is executed to group made of source selection line SSL1 to SSLN grouping is described
Method.However, the erasing operation method is equally applicable to leakage selection line DSL1 to DSLP.In addition, in this embodiment, source selection
Line SSL1 to SSLN can be grouped into two groups.However, source selection line SSL1 to SSLN can be grouped into three groups or more.
Fig. 5 A and Fig. 5 B, which are shown, illustrates the diagram of the group technology according to embodiment.
As set forth above, it is possible to make the floating time delay of some selection lines during erasing operation, or can make to apply
GIDL to some selection transistors biases increase.However, because corresponding selection transistor is repeated exposure to high voltage, institute
With with erasing operation is repeated, these selection transistors may be damaged.It therefore, can be brilliant by selection according to embodiment
Body pipe and corresponding selection line are grouped, to reduce erasing stress.
Referring to Fig. 5 A and Fig. 5 B, memory string MS may include seven source selection transistor SST1 to SST7, and can be with
By the connection between seven source selection line SSL1 to SSL7 control memory string MS and common source line CSL.In addition, group G1 and G2 can
Jointly to include source selection line SSL1 to SSL7 corresponding with source selection transistor SST1 to SST7.First group of G1 may include
Source selection line SSL1 is some into SSL7, and second group of G2 may include other sources choosing of the source selection line SSL1 into SSL7
Select line.
Referring to first embodiment E1, the first source selection transistor SST1 to the 5th source selection transistor SST5 and and its
Corresponding first source selection line SSL1 to the 5th source selection line SSL5 may be constructed first group of G1.First source selection line SSL1 to
Five source selection line SSL5 can be controlled jointly by first group of source selection line G1_SSL.
In addition, the 6th source selection transistor SST6 and the 7th source selection transistor SST7 and the 6th corresponding source choosing
It selects line SSL6 and the 7th source selection line SSL7 may be constructed second group of G2.Belong to the 6th source selection line SSL6 and of second group of G2
Seven source selection line SSL7 can be controlled jointly by second group of source selection line G2_SSL.
In addition, the second embodiment E2 referring to shown by Fig. 5 B to the 4th embodiment E4, with a memory string pair
The number for the group (G1 and G2) answered and include that (number of SSL1 to SSL7) can have for selection line in each group (G1 and G2)
Institute is different.
As described above, by the way that by source selection transistor, ((SSL1 is to SSL7's) for the number or source selection line of SST1 to SST7)
Number is controlled into different from each other, the small numbers of source selection transistor (source selection line (SSL1 of SST1 to SST7) or the number
It can be included in the group with high erasing stress to SSL7).In other words, small numbers of source selection line can be included
In the group that the floating time is delayed by or it is applied in the group of high GIDL biasing.For example, the floating time as second group of G2 is prolonged
Chi Shi, the few source selection line of number (SSL6 and SSL7) can be included in second group of G2.
Grouping can be executed when manufacturing semiconductor devices or when program/erase circulation is repeated a predetermined number of times.Point
Group table can be stored in memory device or be transmitted from controller.
In the embodiment proposed, describe seven source selection transistors being included in a memory string into
The method of row grouping.However, the number of source selection transistor can be different.In addition, group technology also can be applied to leak
Selection transistor.
Fig. 6, which is shown, illustrates the circuit of the cell array structure of the semiconductor devices 100 according to embodiment of the present disclosure
Figure.
Referring to Fig. 6, cell array 110 may include multiple memory block BLK, and every in the multiple memory block BLK
One may include multiple memory string MS11 to MS22.For example, first memory block BLK1 may include I and in a first direction
The memory string MS11 to MS22 arranged on two direction II.In addition, each of memory string MS11 to MS22 can be
Extend on three direction III.First direction I can be line direction, and second direction II can be column direction, and third direction III
It can be stacking direction.
Multiple memory string MS11 to MS22 can be connected between bit line BL1 and BL2 and common source line CSL.In addition, depositing
Each of reservoir string MS11 to MS22 may include at least one source selection transistor (SST1 to SSTN), storage unit MC
Selection transistor (DST1 to DSTP) is leaked at least one.The grid of storage unit MC can be connected to wordline WL.
Common source line can be jointly connected to including the memory string MS11 to MS22 in a memory block BLK1
CSL.In addition, connection between memory string MS11 to MS22 and common source line CSL can respectively by source selection line SSL11 and
SSL2N control.
Being arranged in source selection transistor SST1 to SSTN in first memory the string MS11 and MS12 in the first row can be with
It is connected to the first source selection line SSL11 to SSL1N.Source choosing in second memory the string MS21 and MS22 of arrangement in a second row
Selecting transistor SST1 to SSTN can be controlled by the second source selection line SSL21 to SSL2N.First source selection line SSL11 to SSL1N
Multiple groups can be grouped into, and can control each group.In an identical manner, the second source selection line SSL21 to SSL2N can
To be grouped into multiple groups, and it can control each group.For example, can make accordingly in the different time during erasing operation
Group is floating, and can apply different GIDL biasings to these groups.
Bit line BL1 and BL2 can be connected to including the memory string MS11 to MS22 in a memory block BLK1.Separately
Outside, the corresponding connection between multiple memory string MS11 to MS22 and bit line BL1 and BL2 can be by leakage selection line DSL11 extremely
DSL2P control.
Being arranged in leakage selection transistor DST1 to DSTP in first memory the string MS11 and MS12 in the first row can be with
By the first leakage selection line DSL11 to DSL1P control.Leakage choosing in second memory the string MS21 and MS22 of arrangement in a second row
The second leakage selection line DSL21 to DSL2P can be connected to by selecting transistor DST1 to DSTP.First leakage selection line DSL11 to DSL1P
Multiple groups can be grouped into, and can control each group.In an identical manner, the second source selection line DSL21 to DSL2P can
To be grouped into multiple groups, and it can control each group.For example, can make accordingly in the different time during erasing operation
Group is floating, and can apply different GIDL biasings to these groups.
Fig. 7, which is shown, illustrates the circuit of the cell array structure of the semiconductor devices 100 according to embodiment of the present disclosure
Figure.Hereinafter, the repeated description to component already described above is omitted.
Referring to Fig. 7, cell array 110 may include multiple memory block BLK.Each of memory block BLK may include
Multiple unit string MS11 to MS22.In addition, each of memory string MS11 to MS22 can be arranged the shape of alphabetical " U "
Shape.
In addition, each of memory string MS11 to MS22 may include that (SST1 is extremely at least one source selection transistor
SSTN), storage unit MC and at least one leakage selection transistor (DST1 to DSTP).
Storage unit MC can be laminated on the third direction III intersected with first direction I and second direction II.In addition,
Storage unit MC can with coupled in series between source selection transistor SST1 and tubular type transistor PT and tubular type transistor PT with
It leaks between selection transistor DST1.In addition, the grid of storage unit MC can be respectively coupled to wordline WL.Tubular type transistor PT's
Grid can be connected to the grid of pipe grid PG.
Arrangement source selection transistor SST1 to SSTN in the same row of the memory string MS11 into MS22 can by
The first source selection line SSL1 to the SSLN control extended on same line direction.Source selection line SSL1 to SSLN can be grouped into more
A group, and can control each group.For example, can make to organize accordingly in the different time during erasing operation it is floating, and
Different GIDL biasings can be applied to these groups.
Arrangement leakage selection transistor DST1 to DSTP in the same row of the memory string MS11 into MS22 can by
Leakage selection line DSL11 to the DSL2P control extended on same line direction.Leakage selection line DSL11 to DSL2P can be grouped into more
A group, and can control each group.For example, can make to organize accordingly in the different time during erasing operation it is floating, and
Different GIDL biasings can be applied to these groups.
Fig. 8 A, Fig. 8 B and Fig. 8 C, which are shown, illustrates the section of the structure of the semiconductor devices according to embodiment of the present disclosure
Figure.
Referring to Fig. 8 A, the semiconductor devices according to embodiment may include source selection line SSL1 to SSLN, wordline WL, leakage
Selection line DSL1 to DSLP and channel layer CH.For example, semiconductor devices may include the conductive layer being alternately laminated on each other and insulation
Layer, and conductive layer can be source selection line SSL1 to SSLN or leakage selection line DSL1 to DSLP.
For example, one or more upper layers in conductive layer can be leakage selection line DSL1 to DSLP, it is one or more
Lower conductiving layer can be source selection line SSL1 to SSLN, and remaining conductive layer can be wordline WL.In this example, channel layer
CH can pass through stepped construction in vertical direction, and the bottom of channel layer CH can be connected to common source line CSL, and channel layer CH
Top can be connected to bit line BL.
In another example, one or more upper conductive layers can be leakage selection line DSL1 to DSLP and source selection line
SSL1 to SSLN, at least one lower conductiving layer can be pipe grid, and remaining conductive layer can be wordline WL.In this example,
Channel layer CH can be " U "-shaped, and an end of channel layer CH can be connected to common source line CSL, and channel layer CH's is another
One end can be connected to bit line BL.
Channel layer CH can pass through source selection line SSL1 to SSLN, wordline WL and leakage selection line DSL1 to DSLP.For example, In
It is formed after the opening of stepped construction, channel layer CH can be formed in the opening.Therefore, deposition method, choosing can be passed through
Selecting property growing method etc. forms channel layer CH.In addition, channel layer CH may include half as silicon (Si), germanium (Ge) etc.
Conductor material.For example, channel layer CH can be formed by depositing or growing undoped polysilicon layer in the opening.
Source selection transistor, storage unit and leakage selection transistor can be laminated along channel layer CH and shared channel layer
CH.It therefore, can be by forming knot JN with impurity doped channel layer CH, to control the characteristic of transistor.For example, knot JN can
To be formed at position corresponding with source selection transistor or leakage selection transistor.
Knot JN can be carried out to be formed by using heat treatment process diffusion impurity in channel layer CH.For example, in channel layer CH
Region corresponding with storage unit can be undoped with there is the undoped polysilicon layer of impurity, and with source selection transistor or
The corresponding region of leakage selection transistor can be the doped polysilicon layer doped with impurity.
When channel layer CH is formed stepped construction, impurity can be due to processing variable and in corresponding channel layer CH
With different horizontal proliferations.Fig. 8 B shows impurity and sufficiently spreads in the first channel layer CH1.First group of G1 is to M group GM's
The active selection transistor of institute can be overlapping with the first knot JN1.On the other hand, Fig. 8 C shows impurity in the second channel layer CH2
Not sufficiently diffusion.Some in the source selection transistor of first group of G1 to M group GM cannot fully overlap with the second knot JN2.
Specifically, because impurity concentration reduces due to the characteristic of diffusion technique towards the top of the second knot JN2, it is located at the of top
The source selection transistor of one group of G1 cannot fully be overlapped with the second knot JN2 or the impurity concentration of the second knot JN2 cannot be enough
It is high.
As a result, erasing speed can be made because not generating the hole of sufficient amount from the source selection transistor of first group of G1
Degree reduces, or can occur to wipe failure.Therefore, erasing operation can be improved by increasing by the GIDL electric current of second group of G2.
In other words, the floating time positioned at relatively low position or the second group G2 sufficiently overlapping with knot can be delayed by.As above
It is described, it can be compensated in first group of G1 not by increasing by the amount in the hole of the source selection transistor generation of second group of G2
Foot.
In addition, the threshold voltage without the selection transistor sufficiently overlapping with the second knot JN2 in first group of G1 can increase
Greatly, because charge is captured in gate insulation layer due to HCI.Therefore, by by the source selection line SSL1 of first group of G1 extremely
The floating time delay of SSLJ biases to increase GIDL, can prevent the threshold voltage variation as caused by HCI.
Fig. 9, which is shown, illustrates the block diagram of the configuration of the storage system 1000 according to embodiment.Referring to Fig. 9, storage system
1000 may include memory device 100' and controller 200.
Controller 200 can control memory device 100' by channel C H, and memory device 100' can be in response to control
The control of device 200 processed and operate.Memory device 100' may include the memory cell array containing multiple memory blocks.According to implementation
Mode, memory device 100' can be above-mentioned semiconductor devices 100 or flash memory device.
Controller 200 can be in response to the request from host (not shown) and order memory device 100' executes predetermined behaviour
Make.In addition, memory device 100' can receive order and address from controller 200 by channel C H, and can be in response to this
Address and access from memory cell array select region.In other words, memory device 100' can be to the area for pressing address choice
Domain executes internal operation corresponding with order.
Controller 200 can control memory device 100' and execute programming operation, read operation or erasing operation.In programming operation
Period, controller 200 can provide program command, address and data, and memory to memory device 100' by channel C H
Part 100' can be programmed with data to by the region of address choice.During read operation, controller 200 can pass through channel
CH provides read command and address to memory device 100', and reads data from by the region of address choice.Read operation can wrap
It includes the read operation for being used as the verifying needed due to programming or erasing operation and is stored in a storage unit to read and exporting
Data and the read operation that executes.
During erasing operation, controller 200 can provide erasing order and ground to memory device 100' by channel C H
Location, and memory device 100' can wipe the data being stored in the region by address choice.
Memory device 100' can be by source selection line or leakage selection line grouping, and can make in different times corresponding
Group is floating, or applies different GIDL biasings to corresponding group.The GIDL electric current of some selection transistors can be made to increase, or
Person can prevent the deterioration of selection transistor.Therefore, the erasing operation characteristic and reliability of memory device 100' be can be improved.
Figure 10, which is shown, illustrates the block diagram of the configuration of the storage system 2000 according to embodiment.Referring to Fig.1 0, storage system
System 2000 may include memory device 2100 and controller 2200.
Memory device 2100 can be semiconductor devices and including multiple storage chip.Semiconductor memory chip can be drawn
It is divided into multiple groups.The multiple group can be communicated by first passage CH1 to kth channel C Hk with controller 2200.Storage chip
Each of can be carried out according to the mode substantially the same with the semiconductor devices 100 described above by reference to Fig. 1 configuration and
Operation.
Each group may be configured to be communicated by single common signal channel with controller 2200.Controller 2200 can be with
It is configured according to the mode substantially the same with the controller 200 described above by reference to Fig. 9, and can be configured as and pass through
Multiple storage chips of multiple channel C H1 to CHk control memory devices 2100.Storage system 2000 can be modified, so that individually
Storage chip can be connected to single channel.
Controller 2200 and memory device 2100 can be integrated in a semiconductor devices.According to embodiment, control
Device 2200 and memory device 2100 processed can be integrated into single semiconductor devices, to form storage card.For example, controller
2200 and memory device 2100 can be integrated into single semiconductor devices and form such as personal computer memory card state
Border association (PCMCIA), compact flash cards (CF), smart media card (SM or SMC), memory stick multimedia card (MMC, RS-MMC or
MMCmicro), storage card as SD card (SD, miniSD, microSD or SDHC), Common Flash Memory (UFS) etc..
Controller 2200 and memory device 2100 can be integrated into single semiconductor devices, to form solid state drive
(SSD).SSD may include for storing data in the memory device in memory.When storage system 2000 is used as SSD,
The operation rate for being connected to the host of storage system 2000 can be improved significantly.
In another example, storage system 2000 can be set to such as computer, super mobile PC (UMPC), work
Stand, net book, personal digital assistant (PDA), portable computer, web-tablet, radio telephone, mobile phone, smart phone,
E-book, portable media player (PMP), game console, navigation device, black box, digital camera, three-dimensional television,
Digital audio recorder, digital audio-frequency player, digital picture player, digital picture logger, digital video recorder, energy
It is enough to send/receive one of the device of information, the various devices for being used to form home network in wireless environments, be used to form
One of various electronic devices of computer network, one be used to form in the various electronic devices of teleprocessing network
Kind, in the various elements of electronic device as RFID device or be used to form in the various elements of computing system one etc.
One.
Figure 11, which is shown, illustrates the block diagram of the configuration of the computing system 3000 according to embodiment.Referring to Fig.1 1, calculate system
System 3000 may include central processing unit 3100, random access memory (RAM) 3200, user interface 3300, power supply 3400,
System bus 3500 and storage system 2000.
Storage system 2000 can pass through system bus 3500 and central processing unit 3100, RAM 3200, user interface
3300 and power supply 3400 be electrically connected.The data provided by user interface 3300 or the data handled by central processing unit 3100
It can be stored in storage system 2000.
Memory device 2100 can be coupled by controller 2200 with system bus 3500, or to be directly coupled to system total
Line 3500.When memory device 2100 is directly coupled to system bus 3500, the function of controller 2200 can be by central processing
Unit 3100 and RAM 3200 are executed.
Computing system 3000 may include storage system shown in storage system 2000 or Fig. 9 shown in Figure 10
1000.In addition, computing system 3000 may include above by reference to both Fig. 9 and Figure 10 storage systems 1000 and 2000 described.
According to embodiment, erasing operation characteristic can be improved, and can be improved reliability.
It will be apparent to those skilled in the art that can be the spirit or scope for not departing from this introduction the case where
Under above embodiment is carry out various modifications.Therefore, this introduction is intended to cover fall into the attached claims and its equivalent
In the range of all such modifications.
Embodiment of the present disclosure is described with reference to attached drawing.The specific term or word used in the de-scription should be according to
The spirit of the disclosure understands, without limiting its theme.It should be appreciated that many deformations and modification of introduction described herein are still
It will fall into the spirit and scope of the present disclosure limited in the attached claims and its equivalent.
Cross reference to related applications
This application claims the priority of the South Korea patent application No.10-2018-0052552 submitted on May 8th, 2018,
The full content of the South Korea patent application is incorporated herein by reference.
Claims (26)
1. a kind of semiconductor devices, the semiconductor devices include:
Memory string, the memory string are connected between common source line and bit line, the memory string include at least one
One selection transistor, multiple storage units and multiple second selection transistors；
Selection line, the selection line are individually connected to second selection transistor；And
Control logic circuit, the control logic circuit are configured as making the first group selection in the selection line at the first time
Line is floating, and is configured as making the second group selection in the selection line in the second time for being different from the first time
Line is floating.
2. semiconductor devices according to claim 1, wherein when the first group selection line is than the second group selection line
When closer to the common source line, before the first time appears in second time.
3. semiconductor devices according to claim 1, wherein when the first group selection line is than the second group selection line
When closer to the common source line, after the first time appears in second time.
4. semiconductor devices according to claim 1, wherein when the first group selection line is than the second group selection line
When closer to the bit line, before the first time appears in second time.
5. semiconductor devices according to claim 1, wherein when the first group selection line is than the second group selection line
When closer to the bit line, after the first time appears in second time.
6. semiconductor devices according to claim 1, wherein the control logic circuit makes the first group selection line
Keep the second group selection line floating after floating, and wherein, the second group selection line includes than first group selection
The few selection line of line.
7. semiconductor devices according to claim 1, wherein the control logic circuit makes the first group selection line
Keep the second group selection line floating after floating, and is applied to the grid induction drain leakage of the second group selection line
GIDL biasing is greater than the GIDL biasing for being applied to the first group selection line.
8. semiconductor devices according to claim 1, wherein the number including the selection line in the first group selection line
Mesh be different from include selection line in the second group selection line number.
9. semiconductor devices according to claim 1, wherein by delay make the second group selection line it is floating described in
Second time, Lai Zeng great is by the second selection corresponding with the second group selection line in the multiple second selection transistor
The grid induction drain leakage GIDL electric current that transistor generates.
10. semiconductor devices according to claim 1, wherein the control logic circuit is when erasing voltage increases
Keep the first group selection line and the second group selection line floating in section.
11. a kind of semiconductor devices, the semiconductor devices include:
Memory string, the memory string are connected between common source line and bit line, the memory string include at least one
One selection transistor, multiple storage units and multiple second selection transistors；And
Control logic circuit, the control logic circuit are configured as first group in the multiple second selection transistor
Two selection transistors apply first grid induced drain leakage GIDL biasing, and are configured as brilliant to the multiple second selection
Second group of second selection transistor in body pipe, which applies, biases different the 2nd GIDL biasings from the first GIDL.
12. semiconductor devices according to claim 11, wherein the first GIDL biasing indicates described first group second
Voltage difference between the gate terminal and source terminal of the second selection transistor in selection transistor, and wherein, described
Two GIDL biasing indicates the gate terminal and source terminal of the second selection transistor in second group of second selection transistor
Between voltage difference.
13. semiconductor devices according to claim 11, wherein the control logic circuit is when erasing voltage increases
Keep first group of second selection transistor and second group of second selection transistor floating in section.
14. semiconductor devices according to claim 13, wherein the control logic circuit makes described first group second
Keep second group of second selection transistor floating after selection transistor is floating, and wherein, the 2nd GIDL biasing is big
It is biased in the first GIDL.
15. semiconductor devices according to claim 13, wherein the control logic circuit makes described first group second
Keep second group of second selection transistor floating after selection transistor is floating, and wherein, second group of second selection
Transistor includes second selection transistor fewer than first group of second selection transistor.
16. semiconductor devices according to claim 11, wherein including in first group of second selection transistor
The number of second selection transistor is different from including the second selection transistor in second group of second selection transistor
Number.
17. a kind of method for operating semiconductor devices, which includes memory string, and the memory string is connected in
Between common source line and bit line, the memory string respectively include at least one first choice transistor, multiple storage units and
Multiple second selection transistors, method includes the following steps:
At least one into the common source line and the bit line applies erasing voltage；
At the first time, keep the first group selection line being individually connected in the selection line of second selection transistor floating；
And
In the second time for being different from the first time, make the selection line for being individually connected to second selection transistor
The second group selection line in the middle is floating.
18. according to the method for claim 17, wherein make to make described second group after the first group selection line is floating
Selection line is floating, and wherein, and the second group selection line includes the selection line fewer than the first group selection line.
19. according to the method for claim 17, wherein make to make described second group after the first group selection line is floating
Selection line is floating, and the grid induction drain leakage GIDL biasing for being applied to the second group selection line is described greater than being applied to
The GIDL of first group selection line is biased.
20. according to the method for claim 17, wherein the number including the selection line in the first group selection line is not
Be same as include selection line in the second group selection line number.
21. according to the method for claim 17, wherein applied by postponing the floating of the second group selection line to increase
The grid sense of the second selection transistor corresponding with the second group selection line in the multiple second selection transistor
Drain leakage GIDL is answered to bias.
22. according to the method for claim 17, wherein make the first group selection line in the period that erasing voltage increases
It is floating with the second group selection line.
23. according to the method for claim 17, wherein when the first group selection line is more leaned on than the second group selection line
When the nearly common source line, before the first time appears in second time.
24. according to the method for claim 17, wherein when the first group selection line is more leaned on than the second group selection line
When the nearly common source line, after the first time appears in second time.
25. according to the method for claim 17, wherein when the first group selection line is more leaned on than the second group selection line
When the nearly bit line, before the first time appears in second time.
26. according to the method for claim 17, wherein when the first group selection line is more leaned on than the second group selection line
When the nearly bit line, after the first time appears in second time.
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| KR102373845B1 (en) * | 2020-06-05 | 2022-03-14 | 한양대학교 산학협력단 | Three dimensional flash memory for performing memory operation based on hole injection by gidl |
| KR20210155663A (en) | 2020-06-16 | 2021-12-23 | 에스케이하이닉스 주식회사 | Memory device and operating method threrof |
| JP2022042297A (en) * | 2020-09-02 | 2022-03-14 | キオクシア株式会社 | Semiconductor storage device |
| KR20220031464A (en) | 2020-09-04 | 2022-03-11 | 에스케이하이닉스 주식회사 | Semiconductor device and operating method thereof |
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| US20190348121A1 (en) | 2019-11-14 |
| CN110459252B (en) | 2023-07-21 |
| TW201947583A (en) | 2019-12-16 |
| KR20190128403A (en) | 2019-11-18 |
| TWI768161B (en) | 2022-06-21 |
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