CN110430040A - A kind of extension of message circuit in low-power consumption SHA256 algorithm - Google Patents
A kind of extension of message circuit in low-power consumption SHA256 algorithm Download PDFInfo
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
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Abstract
The present invention provides the extension of message circuits in a kind of low-power consumption SHA256 algorithm, belong to digital integrated circuit technology field.Solve the problems, such as that extension of message circuit power consumption is excessively high in SHA256 circuit.A kind of its technical solution are as follows: the extension of message circuit in low-power consumption SHA256 algorithm, the extension of message circuit includes the message and displacement multiplexing register M of one group of 512bit, the comparator P1 of four groups of tri-state gates Gate1, Gate2, Gate3 and Gate4, one group of arithmetic logic circuit and one group of 6bit are constituted.The invention has the benefit that the present invention is using comparator and tri-state gate shutdown computing circuit input to save power consumption, to achieve the purpose that save power consumption.
Description
Technical field
The present invention relates to the message expansions in digital integrated circuit technology field more particularly to a kind of low-power consumption SHA256 algorithm
Open up circuit.
Background technique
Secure hash algorithm SHA (Secure Hash Algorithm) is U.S.National Security Agency (NSA) design, the U.S.
National standard and Institute for Research and Technology (NIST) publication a series of Cryptographic Hash Functions, including SHA-1, SHA-224, SHA-256,
The variants such as SHA-384 and SHA-512.It is primarily adapted for use in digital signature standard (DigitalSignature Standard DSS)
The Digital Signature Algorithm (Digital Signature Algorithm DSA) that the inside defines.The characteristics of SHA algorithm is cannot
Message is restored from eap-message digest, two different message will not generate same eap-message digest.
The application of SHA: file verification, password encryption, proof of work etc..
SHA256 is more common a kind of in secure hash algorithm.SHA256 is less than length 2^64 message,
SHA256 can generate one 256 eap-message digests.
Current Internet of Things is quickly grown, and the terminal of more and more pairs of sensitive power consumptions is added in network, the application of SHA algorithm
More and more extensive, traditional SHA algorithm is realized by software mode, the disadvantage is that arithmetic speed is slow, is occupied CPU, is passed through
Hardware circuit realizes that SHA algorithm can overcome these disadvantages, but hardware circuit is realized and equally brings severe power problems, In
To in the application environment of sensitive power consumption, higher requirement is proposed to the power consumption of hardware circuit.
Core algorithm is SHA256 algorithm in the application of block chain, wherein bit coin network more outstanding, american energy
One recent studies on of scholarly journal " joule " publication shows that the power consumption level of entire bit coin network may to the end of the year in 2018
Account for the 0.5% of global total amount.And main power consumption is from SHA256 operation in bit coin network, on July 15th, 2019,
Entire bit coin network 13620.00P SHA256 operation of operation per second, it is seen that low power dissipation design is carried out to SHA256 operation
Significance.
In SHA256 algorithm, to being described as follows for the generation of the message Wt of extension:
SHA256 needs 64 wheel operations, the operational parameter W of each roundtSuccessively from W0-W63.
Wherein, W0-W15 has when message M is written, then the 1st wheel operation W16, the 2nd wheel operation W17, with
This analogizes, and in the 48th wheel, W63 has generated, and takes turns in 64 wheels the 49th, and 2. formula no longer needs operation, still
Arithmetic logic circuit input required for realizing formula 2. can still be overturn.Produce unnecessary dynamic power consumption.Have in 64 wheels
16 wheel operations be it is invalid, produce the dynamic power consumption close to 33.3% more.
SHA256 algorithm it is more and more common, be increasingly partial to hardware realization in the case where, the circuit for saving power consumption is set
Meter is of great significance.
Summary of the invention
The object of the present invention is to provide the extension of message circuits in a kind of low-power consumption SHA256 algorithm, calculate in SHA256
The 49-64 of 64 wheel interative computations of method takes turns in invalid operation, cuts off the defeated of arithmetic logic by shutdown tri-state gate Gate1-Gate4
Enter, so that arithmetic logic circuit does not generate dynamic power consumption caused by logic overturning, 16 are taken turns not in 64 wheel interative computations
Operation saves about 25% dynamic power consumption.
The present invention is realized by following measure: the extension of message circuit in a kind of low-power consumption SHA256 algorithm, wherein
The extension of message circuit include one group of 512bit message and displacement multiplexing register M, four groups of tri-state gate Gate1, Gate2,
The comparator P1 of Gate3 and Gate4, one group of arithmetic logic circuit and one group of 6bit are constituted.
Scheme is advanced optimized as the extension of message circuit in a kind of low-power consumption SHA256 algorithm provided by the invention, institute
State the message and displacement multiplexing register M particular content of one group of 512bit are as follows: when needing to input new information, the value of M from
Message inputs M_in；In 64 wheel operations of SHA256 algorithm, each round operation message registers M moves right 32, highest
32, i.e. M [511:480] is from the output of arithmetic logic, and minimum 32, i.e. M [31:0] is extension of message circuit
As a result Wt is exported.
Scheme is advanced optimized as the extension of message circuit in a kind of low-power consumption SHA256 algorithm provided by the invention, institute
The input terminal for stating tri-state gate Gate1 is connected to the position 479-488 of message registers, is output to arithmetic logic；Tri-state gate Gate2's
Input terminal is connected to the position 319-288 of message registers, is output to arithmetic logic；The input terminal of tri-state gate Gate3, which is connected to, to disappear
The position 63-32 for ceasing register, is output to arithmetic logic；The input terminal of tri-state gate Gate4 is connected to the position 31-0 of message registers,
It is output to arithmetic logic；The enable end of Gate1, Gate2, Gate3 and Gate4 are commonly connected to the output EN, In of comparator P1
When EN signal is 1, Gate1, Gate2, Gate3 and Gate4 are opened, their output is equal to input, when EN signal is 0, it
Output be high-impedance state, export it is unrelated with input.This four groups of tri-state gates are the important components of low power dissipation design.
Scheme is advanced optimized as the extension of message circuit in a kind of low-power consumption SHA256 algorithm provided by the invention, institute
Four groups of inputs for stating arithmetic logic circuit are the output of tri-state gate Gate1, Gate2, Gate3 and Gate4 respectively, inside by different
Or door and adder are constituted, output is 32bit data, is connected to highest 32 of message registers M, it is contemplated that adder
It is delayed higher, is the critical path place of entire circuit, so using the carry save adder (CSA) of fast speed.
Scheme is advanced optimized as the extension of message circuit in a kind of low-power consumption SHA256 algorithm provided by the invention, institute
Two groups of inputs for stating comparator P1 are that current operation wheel number round and constant 48 compare when round is less than or equal to 48 respectively
It is 1 that device P1, which exports EN signal, and tri-state gate is enabled, and when round is greater than 48, it is 0 that comparator P1, which exports EN signal, and tri-state gate closes
It closes.
The present invention is in actual use: when a SHA256 operation starts, message is input to message registers M from M_in
In, in SHA256 inner wheel operation, each clock cycle M register moves to right 32bit, and the message Wt of extension is from the minimum of M
32bit output, the new Wt to be generated based on past Wt is from arithmetic logic circuit output and is stored in the highest of M register
32bit；The principle for saving power consumption, in SHA256 internal arithmetic wheel number 1-48 wheel, arithmetic logic circuit normal operation, In
When SHA256 internal arithmetic wheel number is greater than 48 wheel, the input of arithmetic logic circuit is turned off, to save 25% or so dynamic
Power consumption.
The invention has the benefit that the present invention is using comparator and tri-state gate shutdown computing circuit input to save
Power consumption, to achieve the purpose that save power consumption, the present invention is needed when the 49th takes turns to 64 wheel operation, and the input for turning off arithmetic logic comes
It avoids generating unnecessary dynamic power consumption, through comparator P1 when taking turns number input round less than or equal to 48, P1 exports EN=1,
Tri-state gate is enabled to be opened, so that arithmetic logic normal operation；When round is greater than 48, P1 exports EN=0, and tri-state gate is closed, patrolled
The input for collecting computing circuit no longer changes, and no longer overturns inside logical operation circuit, to save about 25% dynamic function
Consumption；Compared with extension of message circuit design in conventional SHA256 algorithm, increase to wheel number judgement, unnecessary operation when
The input for closing computing circuit is waited, power consumption is saved, in a large amount of intensive SHA256 operations, energy spending has been saved, has extended
Battery life, the service life for reducing chip fever simultaneously, can increase chip.
Detailed description of the invention
Fig. 1 is overall structure block diagram of the invention；
Fig. 2 is message registers M functional block diagram of the invention；
Fig. 3 is tri-state gate circuit functional block diagram of the invention；
Fig. 4 is arithmetic logic functional block diagram of the invention.
Specific embodiment
In order to clarify the technical characteristics of the invention, being illustrated below by specific embodiment to this programme.
Referring to Fig. 1 to Fig. 4, the present invention is: the extension of message circuit in a kind of low-power consumption SHA256 algorithm, wherein described
Extension of message circuit includes the message and displacement multiplexing register M, four groups of tri-state gates Gate1, Gate2, Gate3 of one group of 512bit
And Gate4, the comparator P1 composition of one group of arithmetic logic circuit and one group of 6bit.
Specifically, the message of one group of 512bit and displacement multiplexing register M particular content are as follows: newly disappear needing to input
When breath, the value of M inputs M_in from message；In 64 wheel operations of SHA256 algorithm, each round operation message registers M is right
Mobile 32, highest 32, i.e. M [511:480] is from the output of arithmetic logic, and minimum 32, i.e. M [31:0] is
The result of extension of message circuit exports Wt.
New disappear as shown in Fig. 2, the input signal M_in of the message and displacement multiplexing register M are used to be written one
Breath, input signal M [511:480] are used to when SHA256 takes turns operation, and the output of arithmetic logic circuit is written to message deposit
The highest of device M 32, the output end of the position 479-448 of output signal M [479:448] connection M register, and be connected to operation and patrol
The one of input terminal collected, the output end of the position 319-288 of output signal M [319:288] connection M register, and be connected to
One of input terminal of arithmetic logic, the output end of the position 63-32 of output signal M [63:32] connection M register, and connect
To one of input terminal of arithmetic logic, the output end of the position 31-0 of output signal M [31:0] connection M register, and connect
To one of input terminal of arithmetic logic, in new information write-in, new value is written from M_in in M register, and in wheel operation, M is posted
Storage each clock cycle moves to right 32.
Specifically, the input terminal of the tri-state gate Gate1 is connected to the position 479-488 of message registers, is output to operation
Logic；The input terminal of tri-state gate Gate2 is connected to the position 319-288 of message registers, is output to arithmetic logic；Tri-state gate
The input terminal of Gate3 is connected to the position 63-32 of message registers, is output to arithmetic logic；The input terminal of tri-state gate Gate4 connects
To the position 31-0 of message registers, it is output to arithmetic logic；The enable end of Gate1, Gate2, Gate3 and Gate4 connect jointly
To the output EN of comparator P1, when EN signal is 1, Gate1, Gate2, Gate3 and Gate4 are opened, their output is equal to
Input, when EN signal is 0, their output is high-impedance state, is exported unrelated with input.This four groups of tri-state gates are low power dissipation designs
Important component.
Four groups of tri-state gates Gate1, Gate2, Gate3 and Gate4 of the present invention, circuit is as shown in figure 3, share four groups
Tri-state gate, one group of tri-state gate are made of 32 tri-state gates, and wherein the input terminal of Gate1 group tri-state gate is connected to register M's
447-448, wherein the input terminal of Gate2 group tri-state gate is connected to the position 319-288 of register M, wherein Gate3 group tri-state gate
Input terminal be connected to the position 63-32 of register M, wherein the input terminal of Gate4 group tri-state gate is connected to the 31-0 of register M
Position, the enable end of each tri-state gate is the output of comparator, and the output of four groups of tri-state gates is connected to four groups of arithmetic logic circuit
Input input, in EN=1, tri-state gate output is equal to input；In EN=0, tri-state gate exports high-impedance state.
Specifically, four groups of inputs of the arithmetic logic circuit are tri-state gate Gate1, Gate2, Gate3 and Gate4 respectively
Output, inside be made of XOR gate and adder, output be 32bit data, be connected to the highest 32 of message registers M
Position.
It is made of inside the arithmetic logic circuit XOR gate and three groups of adders:
The XOR circuit logical description is as follows:
C0 (X)=ROTR7^ROTR18(X)^SHR3(X)
C1 (X)=ROTR17^ROTR19(X)^SHR10(X)
Wherein X is 32bit input, and ROTR is ring shift right, and SHR is to move to right, and subscript is shift amount, and " ^ " represents exclusive or
Operation.The sequence that shift operation passes through change 32bit signal in the hardware design is completed, and does not generate extra combinational logic, In
In C0 and C1, internal structure is the XOR gate of three groups of 32bit.
Three groups of adder logics are described as follows:
Y=X1+X2+C0+C1
Three groups of adders that the arithmetic logic circuit includes, it is contemplated that the delay of adder is higher, is entire circuit
Where critical path, so using the carry save adder (CSA) of fast speed.
Arithmetic logic circuit of the present invention, as shown in figure 4, four input terminals be respectively a group tri-state gate Gate1,
The output of Gate2, Gate3 and Gate4.Output is connected to the highest 32bit of M register.In SHA wheel operation 49-64 wheel input
It is turned off.
Specifically, two groups of inputs of the comparator P1 are current operation wheel number round and constant 48 respectively, work as round
When less than or equal to 48, it is 1 that comparator P1, which exports EN signal, and tri-state gate is enabled, and when round is greater than 48, comparator P1 exports EN
Signal is 0, and tri-state gate is closed.
The comparator P1, input terminal 1 are wheel number signal round, and input terminal 2 is constant 48, and output end EN is connected to four
The enable end of group tri-state gate Gate1, Gate2, Gate3 and Gate4, when round is less than or equal to 48, EN=1；It is big in round
When 48, EN=0.
Specific work process of the invention are as follows: when a SHA256 operation starts, message is input to message from M_in and posts
In storage M, in SHA256 inner wheel operation, each clock cycle M register moves to right 32bit, and the message Wt of extension is from M's
Minimum 32bit output, the new Wt to be generated based on past Wt is from arithmetic logic circuit output and is stored in the highest of M register
32bit；The principle for saving power consumption, in SHA256 internal arithmetic wheel number 1-48 wheel, arithmetic logic circuit normal operation, In
When SHA256 internal arithmetic wheel number is greater than 48 wheel, the input of arithmetic logic circuit is turned off, to save 25% or so dynamic
Power consumption.
Technical characteristic of the present invention without description can realize that details are not described herein by or using the prior art, certainly,
The above description is not a limitation of the present invention, and the present invention is also not limited to the example above, the ordinary skill of the art
The variations, modifications, additions or substitutions that personnel are made within the essential scope of the present invention also should belong to protection model of the invention
It encloses.
Claims (5)
1. the extension of message circuit in a kind of low-power consumption SHA256 algorithm, which is characterized in that the extension of message circuit includes one
The message of group 512bit and displacement multiplexing register M, four groups of tri-state gates Gate1, Gate2, Gate3 and Gate4, one group of operation are patrolled
The comparator P1 for collecting circuit and one group of 6bit is constituted.
2. the extension of message circuit in low-power consumption SHA256 algorithm according to claim 1, which is characterized in that described one group
The message and displacement multiplexing register M particular content of 512bit are as follows: when needing to input new information, the value of M is defeated from message
Enter Min；In 64 wheel operations of SHA256 algorithm, each round operation message registers M moves right 32, and highest 32,
That is M [511:480] is from the output of arithmetic logic, and minimum 32, i.e. M [31: 0] is the result output of extension of message circuit
Wt。
3. the extension of message circuit in low-power consumption SHA256 algorithm according to claim 1, which is characterized in that the tri-state
The input terminal of door Gate1 is connected to 479488 of message registers, is output to arithmetic logic；The input terminal of tri-state gate Gate2
It is connected to the position 319-288 of message registers, is output to arithmetic logic；The input terminal of tri-state gate Gate3 is connected to message deposit
The position 63-32 of device, is output to arithmetic logic；The input terminal of tri-state gate Gate4 is connected to the position 31-0 of message registers, is output to
Arithmetic logic；The enable end of Gate1, Gate2, Gate3 and Gate4 are commonly connected to the output EN of comparator P1, in EN signal
When being 1, Gatel, Gate2, Gate3 and Gate4 are opened, their output is equal to input, when EN signal is 0, they defeated
It is out high-impedance state.
4. the extension of message circuit in low-power consumption SHA256 algorithm according to claim 1, which is characterized in that the operation
Four groups of inputs of logic circuit are the output of tri-state gate Gatel, Gate2, Gate3 and Gate4 respectively, inside by XOR gate with
Three groups of adders are constituted, and arithmetic logic output is 32bit data, are connected to highest 32 of message registers M, described three groups add
Musical instruments used in a Buddhist or Taoist mass is carry save adder (CSA).
5. the extension of message circuit in low-power consumption SHA256 algorithm according to claim 1, which is characterized in that the comparison
Two groups of inputs of device P1 are current operation wheel number round and constant 48 respectively, and when round is less than or equal to 48, comparator P1 is defeated
EN signal is 1 out, and tri-state gate is enabled, and when round is greater than 48, it is 0 that comparator P1, which exports EN signal, and tri-state gate is closed.
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| WO2021233198A1 (en) * | 2020-05-20 | 2021-11-25 | 深圳比特微电子科技有限公司 | Circuit and method for executing hash algorithm |
| WO2023061456A1 (en) * | 2021-10-13 | 2023-04-20 | 清华大学 | Optoelectronic integrated circuit for message extension of message hash algorithm |
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