CN106528045B - A kind of reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate - Google Patents
A kind of reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate Download PDFInfo
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The present invention relates to a kind of reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate, which connect with 4 reversible carry lookahead adders；Further include 4 reversible control circuits, 4 reversible control circuits respectively with 4 reversible carry lookahead adders and 4 reversible control circuit connections；Its quantum cost QC=82+41+107=230, input/output pin 16；Input pin includes: a carry input Cin, a control terminal Ctrl, 6 constant input terminals are ' 0 ', and operand A, B each 4；Output pin includes: 10 rubbish output bits, 1 carry output Cout, a positive and negative flag bit sign ', 4 outputs ' and/poor '.The present invention can significantly reduce the power consumption of device, reduce delay, while having addition, subtraction function, and have the characteristics that quantum cost is low, transmission pin is few.
Description
Technical field
The present invention relates to the reversible plus/minus methods of digital combined logic circuit more particularly to a kind of 4 based on reversible logic gate
Device, i.e. digital circuit carry look ahead plus/minus musical instruments used in a Buddhist or Taoist mass.
Background technique
The rule of development of Moore prophesy integrated circuit follows exponential law, i.e. Moore's Law, according to data statistics Moore's Law
It is all approximate in decades to set up.But most of insiders think that Moore's Law will fail, main cause includes:
With the increase of device count in unit area, generating heat can be more and more, and the development of integrated circuit is caused to be affected.
Landauer proposes energy consumption problem earliest and is mainly derived from the irreversible of calculating, and points out that the irreversible information of each is wiped
It is thus reversible to be calculated as people except the heat (it is thermodynamic temperature that wherein k, which is Boltzmann constant, T) that can generate kTlg2 coke
Focus of attention.Adder, subtracter are the execution units of central processing unit, are the most important component parts of central processing unit.
Therefore adder, the performance of subtracter can largely represent the performance of entire computer.Addition is that numerical value calculates sum number
According to one of operation most common in analysis.Adder is one of common basic element circuit in electronic system, is widely used in
In Digital Signal Processing and Design of Digital System.Traditional carry lookahead adder can execute at a high speed add operation, can be avoided
The delay of carry step-by-step computation bring.Information bit erasing is had in the irreversible calculating process of conventional adders, and energy is caused to damage
Mistake and circuit power consumption.Low-power consumption and loss-free digital circuit research are current new academic frontier and research hotspot, for promoting
Ultra-large digital integration electronic system technology development plays a significant role.
A kind of carry lookahead adder disclosed in CN1128071 for addend to be added with summand, and generates final add
It closes, the addend, summand and final adduction are multidigit binary number, in column by hyte at the same level in addend and summand.
The adder has at least one data reduction grade, the adduction that it is finally simplified using addend and the summand generation simplified, and one
A synthesis/increase calculates grade and calculates adduction using simplified addend and summand and increase data.One carry synthesis grade utilizes conjunction
At least one carry is generated at increase data.Final adduction calculates the addend that grade utilization simplifies, summand and final carry
Calculate final adduction.But this carry lookahead adder power consumption is higher, reversible logic principle is not used, also not in electricity
Make lower power consumption using reversible logic gate in road.
A kind of reversible logic carry lookahead adder disclosed in CN 103235710A is added by 4 reversible carry look aheads of level Four
Musical instruments used in a Buddhist or Taoist mass cascade is constituted, and 4 reversible carry lookahead adders of every level-one calculate separately 4 one's own department or unit operation results of the same level and opposite
The carry-out answered by the first carry-out, the second carry-out, third carry-out input respectively next stage 4 it is reversible advanced
The corresponding carry input of carrier adder is inputted as its carry, and the 4th carry-out carry-out is reversible advanced as 16
The carry-out of carrier adder.It uses the design method of reversible logic, to realize 16 carry lookahead adders.It can
Circuit delay is greatly reduced.Simultaneously, it then follows the circuit design of reversible logic theory can reduce energy loss and even shut out completely
Exhausted circuit loss.But this reversible carry lookahead adder, due to the limitation of circuit synthesis technology, institute's generative circuit has amount
The disadvantages of filial generation valence is high, and input/output pin is more, circuit complexity is higher.
Therefore, there is further improved demands for existing reversible logic carry lookahead adder.
Summary of the invention
The present invention provides a kind of 4 based on reversible logic gate for the high defect of device power consumption in existing digital circuit can
Inverse plus/minus musical instruments used in a Buddhist or Taoist mass, can significantly reduce the power consumption of device, reduce delay, while having addition, subtraction function, and have amount
The feature that filial generation valence is low, transmission pin is few.
The reversible plus/minus musical instruments used in a Buddhist or Taoist mass in a kind of 4 based on reversible logic gate of the present invention, including one 4 reversible advanced
Carrier adder, it is characterized in that: further include 4 reversible digital comparators, 4 reversible digital comparators with described 4
Reversible carry lookahead adder connection；It further include 4 reversible control circuits, 4 reversible control circuits are respectively with described 4
The reversible carry lookahead adder in position and 4 reversible control circuit connections；Its quantum cost QC=82+41+107=230, input/
Output pin each 16；Input pin includes: a carry input Cin, a control terminal Ctrl, 6 constant input terminals are equal
It is ' 0 ', operand A, B each 4；Output pin includes: 10 rubbish output bits, 1 carry output Cout, a positive and negative mark
Will position sign ' (sign's negates), 4 outputs ' and/poor '.
Further, the reversible carry lookahead adder, by 7 CNOT gates, 9 3*3Toffoli, 4 Peres
Door, 3 4*4Toffoli gate leve connection are constituted, quantum cost QC=1*7+5*9+4*4+13*3=107, input/output pin
Each 14；Input pin includes: a carry input Cin, 5 constant input terminals are ' 0 ', and operand A, B each 4；It is defeated
Pin includes out: 9 rubbish output bit G, 1 carry output Cout, 4 output ' and ' S0, S1, S2, S3.
Further, 4 reversible comparators, by 8 NOT gates, 4 CNOT gates, 9 3*3Toffoli, 3
Peres, 1 4*4Toffoli gate leve connection composition, quantum cost QC=1*8+1*4+5*9+4*3+13*1=82, input/defeated
Each 14 of pin out, input pin includes: 6 constant input terminals are ' 0 ', and operand A, B each 4；Output pin includes:
Wherein 13 output ends are equal with corresponding input terminal, and 1 output end sign exports two binary number comparison results.
Further, 4 reversible control circuits, by 1 NOT gate, 8 3*3Toffoli gate leve connection are constituted, quantum generation
Valence QC=1*1+5*8=41, input/output pin each 10；Input pin includes: 1 input control Ctrl, 1 input control
Sign processed, operand A, B each 4；Output pin includes: 1 rubbish output, 1 ' poor ' positive and negative flag bit sign ', operand
A, each A ' of the negated result of B, B ' 4.
Beneficial effects of the present invention: have simultaneously due to being provided with one on the basis of 4 reversible carry lookahead adders
There are 4 reversible plus/minus musical instruments used in a Buddhist or Taoist mass of addition, subtraction operation function.It can be realized resource multiplex, reduce circuit complexity.And
And a transmission line to the operation of control selections addition/subtraction is provided in 4 reversible control circuits, draw control terminal
Mouth Ctrl, i.e. control terminal input ' 0 ' then carry out add operation, and control terminal input ' 1 ' then selects subtraction.
Since reversible carry lookahead adder carry at different levels generates independently of one another, only with input data and from low level
Carry is related, and at different levels carry cascades are broadcast to the delay for eliminating, therefore reducing carry generation.
Due to establishing on the basis of 4 reversible carry lookahead adders, benefit is taken by carrying out to lesser binary number
Code is added realization.Therefore, the present invention, which is provided with 4 reversible comparators and one, has 4 reversible controls for negating function
Circuit processed.Wherein, 4 conventional bit comparator functions are changed: retain the function of judgement " being less than ", casts out not
The arbitration functions of necessary ' being greater than ' ' being equal to ', thus simplify the complexity of circuit.
Due to being changed using part reversible logic gate to the output end function of circuit, realize except (Sig is whole by sign
Replaced with sign) end outside other output ends it is equal with input terminal, for next stage circuit use, to reduce rubbish
Output, reduces circuit input/output pin.
Due to making following change to 4 reversible comparators: 1) retaining the function of judgement " being less than ", cast out unnecessary ' big
In ', the arbitration functions of ' being equal to ', principle is: judging two binary operation number A, B sizes, the output end sign if A < B
=1, otherwise sign=0；2) the output end function of circuit is changed using part reversible logic gate, is made in addition to the end sign
Other output ends it is equal with input terminal, for next stage circuit use to reduce rubbish export, it is defeated to simplify circuit
Enter/output pin.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of NOT gate；
Fig. 2 is the structural schematic diagram of CNOT gate；
Fig. 3 is 3*3Toffoli structural schematic diagrams；
Fig. 4 is 4*4Toffoli structural schematic diagrams；
Fig. 5 is Peres structural schematic diagrams；
Fig. 6 is structural schematic diagram of the invention；
Fig. 7 is 4 reversible carry lookahead adder structure principle charts；
Fig. 8 is 4 reversible comparator configuration schematic diagrams；
Fig. 9 is 4 reversible control circuit structure schematic diagrams.
In figure: 1-NOT, 2-CNOT, 3-3*3Toffoli, 4-4*4Toffoli, 5-Peres, 6-
4 reversible digital comparators, 7-4 reversible control circuits, 8-4 reversible carry lookahead adders.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing.
Referring to Fig. 1 to Fig. 9, a kind of reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate is based on Toffoli
What race completed.It is related to: NOT gate 1, CNOT gate 2,3*3Toffoli door 3,4*4Toffoli door 4, Peres door 5.
The NOT gate 1 is the reversible door of single input/output, and quantum cost 1 has the function of to negate input, referring to
Fig. 1.
The CNOT gate 2 (also known as control NOT gate, control-not gate), is two input/output doors, quantum cost 1,
Comprising a control bit and a target position, target position is negated when control bit is 1, referring to fig. 2.
The 3*3Toffoli door 3, (also known as " control-control-is non-" door, controlled-controlled-not (CCNOT)
It gate), is three input/output doors, quantum cost 5 includes two control bits, a target position, target position when control all takes 1
It negates, referring to Fig. 3.
The 4*4Toffoli door 4, is four input/output doors, and quantum cost 13 includes three control bits, a mesh
Mark, target position negates when control all takes 1, referring to fig. 4.
The Peres door 5 is three input/output doors, quantum cost 4, by a CNOT gate and one Toffoli
It constitutes, CNOT gate and Toffoli functions can be achieved at the same time, referring to Fig. 5.
The reversible plus/minus musical instruments used in a Buddhist or Taoist mass (referring to Fig. 6) in a kind of 4 based on reversible logic gate of the present invention, including one 4
Reversible carry lookahead adder 8, substantive distinguishing features are: further including 4 reversible digital comparators 6,4 reversible numerical value
Comparator is connect with described 4 reversible carry lookahead adders 8；It further include 4 reversible control circuits 7, this 4 reversible
Control circuit is connect with described 4 reversible carry lookahead adder 8 and 4 reversible control circuits 7 respectively；Its quantum cost QC=
82+41+107=230, wherein the quantum cost of 4 reversible comparators is that the quantum cost of 82,4 reversible control circuits is
41, the quantum cost of 4 reversible carry lookahead adders is 107；Input/output pin each 16, input pin includes: one
Carry input Cin, a control terminal Ctrl, 6 constant input terminals are ' 0 ', and operand A, B each 4；Output pin packet
Contain: 10 rubbish output bits, 1 carry output Cout, a positive and negative flag bit sign ', 4 outputs ' and/poor '.
The reversible carry lookahead adder 8 (referring to Fig. 7), by 73,4,3*3Toffoli doors of CNOT gate 2,9
5,3 cascades of 4*4Toffoli door 4 of Peres door are constituted, quantum cost QC=1*7+5*9+4*4+13*3=107, input/defeated
Pin is each 14 out；Input pin includes: a carry input Cin, 5 constant input terminals are ' 0 ', operand A, B
Each 4；Output pin includes: 9 rubbish output bit G, 1 carry output Cout, 4 output ' and/poor ' S0, S1, S2,
S3,.
Reversible carry lookahead adder carry at different levels generates independently of one another, only with input data and from low level
Carry is related, and at different levels carry cascades are broadcast to the delay for eliminating, therefore reducing carry generation.
Subtracter of the invention is in foundation on the basis of 4 reversible carry lookahead adders, by lesser two
System number carries out that complement code is taken to be added realization, and carry input is set as ' 1 '.Therefore to realize that subtraction function also needs one 4
Reversible comparator and one have 4 reversible control circuits for negating function.Simultaneously for the addition function of stick holding circuit, need
4 reversible comparators and 4 reversible control circuit structures are handled.
4 reversible comparators 6 (referring to Fig. 8), by 8 CNOT gate 2,9 of NOT gate 1,4 3*3Toffoli doors 3,
3 Peres doors, 5,1 cascades of 4*4Toffoli doors 4 are constituted, quantum cost QC=1*8+1*4+5*9+4*3+13*1=82, defeated
Entering/output pin each 14, input pin includes: 6 constant input terminals are ' 0 ', and operand A, B each 4；Output pin packet
Contain: wherein 13 output ends are equal with corresponding input terminal, and 1 output end sign exports two binary number comparison results.
The present invention makes following change to 4 reversible comparators: 1) retaining the function of judgement " being less than ", cast out unnecessary
The arbitration functions of ' being greater than ', ' being equal to ', principle are: judging two binary operation number A, B sizes, the output end if A < B
Sign=1, otherwise sign=0, referring to fig. 4；2) the output end function of circuit is changed using part reversible logic gate, is made
Other output ends in addition to the end sign are equal with input terminal, for next stage circuit use, reduce rubbish output, simplify
Circuit input/output pin.
4 reversible control circuits (referring to Fig. 9) are made of, amount 1 NOT gate, 1,8 cascades of 3*3Toffoli door 3
Filial generation valence QC=1*1+5*8=41, input/output pin are each 10；Input pin includes: 1 input control Ctrl, and 1
Input control sign, operand A, B each 4；Output pin includes: 1 rubbish output, 1 ' poor ' positive and negative flag bit sign ',
Each A ' of the negated result of operand A, B, B ' 4.The function of 4 reversible control circuits is: according to input terminal Ctrl
Value decide whether to negate binary number；And after comparator work, selected according to the value at the end output end sign to the
One operand A takes complement code still to take complement code to second operand B.
The present invention has the function of selectively negating binary number to 4 reversible control circuits, by defeated
Enter to hold Ctrl, sign to judge to negate which operand, wherein the end Ctrl has priority, and Ctrl=1 is, it can be achieved that negate
Subtraction operation can be realized in work；Ctrl=0 can not realize inversion operation, add operation can be realized.The end Ctrl is entire
The addition/subtraction operating mode selection port of circuit.The end sign is connected with upper level 4 reversible comparator output sign,
In the case of Ctrl=1: sign=1, i.e. operand A < B negate A；Sign=1, i.e. operand A >=B, negate B.
Present invention will be further explained below with reference to specific examples.
The present invention is using ESOP (the Exclusive OR Sum of Product) synthesis for being suitble to the fairly large circuit of generation
Method, realizes the equation of function according to required for expression circuit, is mapped to reciprocal networks one by one for Toffoli, described 4
The reversible carry lookahead adder in position is by 73,4,3*3Toffoli door Peres doors of CNOT gate 2,9,5,3 4*4Toffoli
4 cascade of door is constituted.Wherein, 4 Peres doors 5 constitute 4 half adders, for realizing two 4 binary operation number one's own department or unit phases
Add；4 Peres doors 5,3 and 3, the 3*3Toffoli door 4*4Toffoli door 4 of first three CNOT gate 2,9 constitute 4 independences
The circuit of ' carry ' C0, C1, C2, Cout is solved, C0, C1, C2 without embodying in the output, so it is considered as rubbish output,
Four CNOT gates 2 are used to for one's own department or unit that half adder is asked ' and ' being added with low one ' carry ' afterwards, and the specific cascade system of circuit is joined
According to seeking the equation of ' and ' with ' carry '.
' and ' solve equation:
S0=A0 ⊕ B0 ⊕ Cin
S1=A1 ⊕ B1 ⊕ C0
S2=A2 ⊕ B2 ⊕ C1
S3=A3 ⊕ B3 ⊕ C2
' carry ' solves equation:
C0=A0B0 ⊕ (A0 ⊕ B0) Cin
C1=A1B1 ⊕ (A1 ⊕ B1) A0B0 ⊕ (A1 ⊕ B1) (A0 ⊕ B0) Cin
C2=A2B2 ⊕ (A2 ⊕ B2) A1B1 ⊕ (A2 ⊕ B2) (A1 ⊕ B1) A0B0
⊕(A2⊕B2)(A1⊕B1)(A0⊕B0)Cin
Cout=A3B3 ⊕ (A3 ⊕ B3) A2B2 ⊕ (A3 ⊕ B3) (A2 ⊕ B2) A1B1
⊕(A3⊕B3)(A2⊕B2)(A1⊕B1)A0B0
⊕(A3⊕B3)(A2⊕B2)(A1⊕B1)(A0⊕B0)Cin
4 reversible comparators are by 8 CNOT gates 2,93,3 Peres, 3*3Toffoli door of NOT gate 1,4
5,1 cascade of 4*4Toffoli door 4 is constituted, from left to right, by the CNOT gate 2,4 3*3Toffoli of preceding 4 NOT gates 1,1
3, circuit made of 3 Peres doors, 5,1 4*4Toffoli doors 4 cascade, for comparing whether operand A is less than B, specific grade
Linked method is referring to the equation for describing operand A < B.By the 3*3Toffoli door 3 of CNOT gate 2,5 of rear 4 NOT gates 1,3
Circuit made of cascade is changed for the output end function to circuit, make other output ends in addition to the end sign with it is defeated
People end is equal, and so that 4 reversible control circuits, 4 reversible carry lookahead adders reuse, principle is: 1) two
The input/output number of reversible logic gate is identical, and control bit is consistent with target position position, then claims the two reversible logic gates
For homotype reversible logic gate；2) any even (surprise) a homotype reversible logic gate series connection, output result are all the same.Odd number homotype can
Inverse door series connection is equal to the function of a homotype reversible logic gate, and the series connection of even number homotype reversible logic gate is equal to the free time.
' A < B ' solves equation:
4 reversible control circuits are made of 1 cascade of NOT gate 1 and 8 3*3Toffoli door 3,8 3*
3Toffoli 3 control bits of door are identical, respectively correspond two control ports sign and Ctrl, and for controlling, category is no to take operand
Instead, the corresponding positional operand in each 3 target position of 3*3Toffoli door, for being negated to operand.1 NOT gate 1 is to control terminal
Sign is negated, and is negated for distinguishing to that operand, i.e. when sign=1 negates 4 positional operand A, when sign=0 pair
Operand B goes to negate.
Claims (4)
1. a kind of reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate, including one 4 reversible carry lookahead adders (8),
It is characterized in that: further including 4 reversible digital comparators (6), 4 reversible digital comparators are reversible advanced with described 4
Carrier adder (8) connection；Further include 4 reversible control circuits (7), 4 reversible control circuits respectively with described 4
Reversible carry lookahead adder (8) and 4 reversible control circuit (7) connections；Its quantum cost QC=82+41+107=230, it is defeated
Enter/output pin each 16；Input pin includes: a carry input Cin, a control terminal Ctrl, 6 constant input terminals
It is ' 0 ', operand A, B each 4；Output pin includes: 10 rubbish output bits, 1 carry output Cout, one it is positive and negative
Flag bit sign ', 4 outputs ' and/poor '.
2. the reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate according to claim 1, it is characterized in that: described reversible super
Advanced potential adder (8), by 7 CNOT gates (2), 9 3*3Toffoli (3), 4 Peres (5), 3 4*4Toffoli
Door (4) cascade is constituted, quantum cost QC=1*7+5*9+4*4+13*3=107, and input/output pin is each 14；Input
Pin includes: a carry input Cin, 5 constant input terminals are ' 0 ', and operand A, B each 4；Output pin includes: 9
A rubbish output bit G, 1 carry output Cout, 4 output ' and/poor ' S0, S1, S2, S3.
3. the reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate according to claim 1, it is characterized in that: described 4 can
Inverse digital comparator (6), by 8 NOT gates (1), 4 CNOT gates (2), 9 3*3Toffoli (3), 3 Peres (5), 1
4*4Toffoli a (4) cascade is constituted, quantum cost QC=1*8+1*4+5*9+4*3+13*1=82, input/output pin
It is each 14, input pin includes: 6 constant input terminals are ' 0 ', and operand A, B each 4；Output pin includes: wherein 13
A output end is equal with corresponding input terminal, and 1 output end sign exports two binary number comparison results.
4. the reversible plus/minus musical instruments used in a Buddhist or Taoist mass in 4 based on reversible logic gate according to claim 1, it is characterized in that: described 4 can
Adverse control circuit, by 1 NOT gate (1), 8 3*3Toffoli (3) cascades are constituted, quantum cost QC=1*1+5*8=41,
Input/output pin is each 10；Input pin includes: 1 input control Ctrl, 1 input control sign, operand A, B
Each 4；Output pin includes: 1 rubbish output, 1 ' poor ' positive and negative flag bit sign ', the negated result of operand A, B
A ', B ' each 4.
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| CN107066234B (en) * | 2017-04-21 | 2020-05-26 | 重庆邮电大学 | Design method of quantum multiplier |
| CN108920837B (en) * | 2018-07-04 | 2023-04-07 | 卜登立 | Reversible circuit synthesis method for extracting common factors among ESOP product terms by using shared ZMODD |
| CN109032561B (en) * | 2018-07-20 | 2022-10-14 | 福州大学 | Reversible logic adder circuit with carry bypass output as carry selection |
| CN110045944A (en) * | 2019-04-23 | 2019-07-23 | 陈新豫 | Novel mimimum adder |
| CN111580782B (en) * | 2019-07-09 | 2022-07-15 | 沈阳工业大学 | Quantum n-bit full adder |
| CN112214200B (en) * | 2020-09-30 | 2023-12-15 | 本源量子计算科技（合肥）股份有限公司 | Quantum subtraction operation method, device, electronic device and storage medium |
| CN112162723B (en) * | 2020-09-30 | 2023-12-15 | 本源量子计算科技（合肥）股份有限公司 | Quantum subtraction operation method, device, electronic device and storage medium |
| CN112329380B (en) * | 2020-11-12 | 2024-01-19 | 南通大学 | Reversible gate equivalent transformation method for reversible circuit optimization |
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