CN108920837B - Reversible circuit synthesis method for extracting common factors among ESOP product terms by using shared ZMODD - Google Patents
Reversible circuit synthesis method for extracting common factors among ESOP product terms by using shared ZMODD Download PDFInfo
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- CN108920837B CN108920837B CN201810725176.1A CN201810725176A CN108920837B CN 108920837 B CN108920837 B CN 108920837B CN 201810725176 A CN201810725176 A CN 201810725176A CN 108920837 B CN108920837 B CN 108920837B
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Abstract
The invention discloses a reversible circuit synthesis method for extracting common factors among ESOP product terms by using a shared ZMODD, belonging to the technical field of reversible circuit synthesis and design; the method mainly comprises the following steps: and expressing the ESOP of the multi-output function by using the shared ZMODD, extracting common factors among ESOP product terms by using the shared ZMODD in an iterative mode, and performing reversible circuit synthesis according to the result of extracting the common factors. The ESOP cube set is represented by the shared ZMODD, the shared ZMODD is subjected to variable sorting by means of the existing variable sorting technology, common factors among cubes are extracted according to the sharing of input variable nodes, the common factors among cubes with the quantity larger than 2 can be extracted, and meanwhile, the maximum common factors among a plurality of cubes can be extracted as far as possible, so that the quantum cost and the quantum digit number are balanced, and the quantum cost of the comprehensively obtained reversible circuit is reduced.
Description
Technical Field
The invention relates to the technical field of reversible circuit synthesis and design, in particular to a reversible circuit synthesis method for extracting common factors among ESOP product terms by using a shared ZMODD.
Background
The reversible circuit is in a circuit form of an information lossless calculation mode, and can realize the approximate zero power consumption theoretically. Due to the inherent reversibility of quantum computing, a reversible circuit becomes a basic component of a quantum computer and a core part of a quantum circuit model. The reduction of the quantum cost of the reversible circuit is beneficial to reducing the computation complexity of the quantum circuit realization, and the reduction of the quantum bit number of the reversible circuit is beneficial to reducing the hardware complexity of the quantum circuit realization.
The Exclusive-or Sum (ESOP) Of the Products is a logical representation Of the function based on an AND-XOR operation, i.e., a representation in which a set Of product terms are connected by an XOR operation, often represented by a set Of cubes. Zero-suppressed Multiple-Output Decision Diagram (ZMODD), is a graphical representation of cubes, particularly multi-Output cubes, and if an ESOP cube is represented as a ZMODD, the set of ESOP cubes can be represented as a shared ZMODD.
The product term of ESOP can be directly mapped to a reversible logic gate with multiple control lines, so that the product term is often used as a representation model to synthesize a reversible circuit. In order to reduce the quantum cost of the reversible circuit obtained by ESOP synthesis, the conventional reversible circuit synthesis method based on ESOP usually adopts cube representation and extracts common factors among product terms through cube decomposition, and because the cube representation cannot directly reflect the structural similarity among the product terms, the method is not beneficial to the extraction of the common factors among the product terms and the reduction of the quantum cost of the reversible circuit obtained by ESOP synthesis.
The ESOP cube decomposition method adopted by Lukac M et al extracts only the common factor with a literal number of 2 between product terms. The method has the advantages that firstly, variable sequencing is not carried out on the input part of a cube, so that common factors among multiple product terms cannot be well extracted, and although the method can reduce the quantum cost of a reversible circuit obtained by ESOP synthesis to a certain extent, the quantum cost is still high relatively; secondly, the maximum common factor among product terms is not extracted, so that the quantum number of the reversible circuit obtained by synthesis is more. (Lukac M et al, 2011)
The ESOP cube decomposition method adopted by Parlapalli S P and the like only extracts common factors among 2 cubes, and although the maximum common factor among 2 product terms can be extracted, the quantum number of the reversible circuit obtained by synthesis is small, the quantum cost of the reversible circuit obtained by synthesis is high because common factors among cubes with the number larger than 2 are not extracted. (Parlapalli S P et al, 2017)
In summary, in the current reversible circuit synthesis method based on the ESOP cube decomposition, firstly, the quantum cost of the reversible circuit obtained by synthesis is high, and secondly, the quantum cost and the quantum bit number are not considered comprehensively, and the balance is carried out between the quantum cost and the quantum bit number, so that a new reversible circuit synthesis method is urgently needed to be found, the balance can be carried out between the quantum cost and the quantum bit number, and the quantum cost of the reversible circuit obtained by synthesis is reduced.
Reference documents:
Lukac M,Kameyama M,Perkowski M,Kerntopf P.Decomposition of reversible logic function based on cube-reordering[J].FACTA UNIVERSITATIS(NIS),2011,24(3):403-422.
Parlapalli S P,Vudadha C,Srinivas M B.An ESOP based cube decomposition technique for reversible circuits[A].In Proceedings of the 9th International Conference on Reversible Computation[C],Kolkata,India,2017:127-140.
disclosure of Invention
It is an object of the present invention to provide a reversible circuit synthesis method for extracting common factors between ESOP product terms using a shared ZMODD to solve the aforementioned problems in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
s1, representing ESOP of a multi-output function by using a shared ZMODD;
s2, extracting a common factor among ESOP product terms by the shared ZMODD in an iterative mode;
and S3, performing reversible circuit synthesis according to the result of the step S2.
Preferably, step S1 specifically includes:
s11, for a Boolean function with n inputs and m outputs, the ESOP cube c = [ i ] 0 ,i 1 ,…,i n-1 ,o 0 ,o 1 ,…,o m-1 ]，[i 0 ,i 1 ,…,i n-1 ]For the input part of the cube, corresponding to ESOP product terms
Respectively correspond to>
[o 0 ,o 1 ,…,o m-1 ]Is the output part of the cube, o k ∈{0,1}，o k Denotes the product term = 1->
Belonging to function f k ；
S12, mapping each ESOP cube to a ZMODD, and inputting i to the cube j ，i j Mapping it to ZMODD input variable x if =1 j ，i j If =0, it is mapped to ZMODD input variable
i j = time without mapping; output o for cube k ，o k Mapping it to ZMODD output variable f when =1 k ，o k No mapping is performed when = 0.
In the ZMODD, each node corresponds to one ZMODD variable except for constant nodes (constant 0 node and constant 1 node), and a path from the root node to the constant 1 node forms an ESOP cube, each node having 2 edges, the solid line edge indicating that the ZMODD variable appears in the cube, and the dashed line edge indicating that the ZMODD variable does not appear in the cube. The ZMODD output variables are at the top of the ZMODD, the input variables are at the bottom of the ZMODD, and no overlap of the input variables with the output variables occurs.
Preferably, step S2 specifically includes:
s21, performing variable sequencing on the shared ZMODD by means of the existing Sifting technology, then traversing the shared ZMODD in a depth-first mode, and extracting common factors among cube input parts, namely ESOP product terms according to whether input variable nodes are shared or not;
if an input variable node is shared by multiple ZMODs, it indicates that the product term (common factor) formed by the path from the node to the constant 1 node is shared by multiple ESOP product terms.
S22, when one input variable node is shared by a plurality of ZMODs, extracting common factors formed by paths from the input variable node to a constant 1 node by utilizing division operation; iterating the process until no input variable nodes in the ZMODD are shared;
and S23, when the ZMODD does not have the input variable node shared any more, traversing the shared ZMODD to obtain the ESOP cube set after the common factor extraction, and recording the common factors contained in each cube.
The more common factors are extracted, the more helpful is to reduce the quantum cost of the reversible circuit obtained by synthesis, but the quantum digit of the reversible circuit obtained by synthesis is increased, so that the number of the plaintext is reduced as much as possibleCommon factor (containing only one word, e.g. x) j Or alternatively
) The extraction of (1). For the common factor a of the single character, if the adjacent common factors are also common factors of the single character, combining the common factors of the single character until the number of characters of the next common factor b is more than 1; otherwise, the number of the characters of the common factor b adjacent to the single character common factor a is larger than 1, at this time, whether the common factor b is extracted or not is judged, if the common factor b is extracted, the common factors a and b are respectively extracted by using division operation, otherwise, the common factor after the a and b are combined is extracted.
By means of the single character common factor merging strategy, the maximum common factor among the cubes can be extracted as far as possible.
Preferably, step S3 specifically includes: sequentially synthesizing all cubes of the ESOP, and when one cube is synthesized, if the cube contains a public factor, synthesizing the public factor into a reversible logic gate, and then synthesizing the cube; and directly carrying out synthesis on cubes without common factors extracted, and cascading reversible logic gates obtained by synthesis into a reversible circuit.
Preferably, when the common factor is synthesized into the reversible logic gate, an auxiliary line having a value of constant 0 is used as a target line of the reversible logic gate obtained by the synthesis, then the auxiliary line is used as a control line to sequentially synthesize all cubes including the common factor, and after all cubes including the common factor are synthesized, the value of the auxiliary line is restored by using the reversible logic gate to be used for the synthesis of the remaining common factors.
The invention has the beneficial effects that:
the common factor extraction method in the patent of the invention represents an ESOP cube set by sharing a ZMODD, carries out variable sequencing on the shared ZMODD by means of the existing variable sequencing technology, extracts common factors among cubes according to the sharing of input variable nodes, and can extract the common factors among cubes with the quantity larger than 2 by adopting the iterative common factor extraction method, and can also extract the maximum common factors among a plurality of cubes as much as possible, thereby carrying out balance between quantum cost and quantum digit and reducing the quantum cost of the reversible circuit obtained by synthesis.
Drawings
FIG. 1 is a set of example functions ESOP cubes;
FIG. 2 is an initial shared ZMODD;
FIG. 3 shows the extraction of the common factor x 2 x 3 The post-shared ZMODD;
FIG. 4 is the final shared ZMODD;
FIG. 5 is a set of ESOP cubes after common factor extraction;
fig. 6 is the resultant reversible circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
This embodiment will take an example of an ESOP function with 4 inputs and 3 outputs, which has 5 cubes as shown in FIG. 1.
(1) ESOP for representing multiple output functions using shared ZMODDs
Mapping each cube to a ZMODD, and sorting the variables of the shared ZMODD by means of the existing Sifting technology to obtain the shared ZMODD as shown in FIG. 2 (the constant 0 node and the path to the constant 0 node are omitted for simplicity), wherein f 0 、f 1 And f 2 Represents the output variable node, x j And with
Representing ZMODD input variable nodes.
(2) Iterative extraction of communality factors between ESOP product terms from shared ZMODs
As can be seen from FIG. 2, c 1 ZMODD and c of 2 ZMODD of (1) shares a dashed ellipse2 input variable nodes surrounded by x 2 Node is x 3 The path from node to constant 1 node constitutes a common factor x 2 x 3 (ii) a Extracting a common factor x 2 x 3 Then, the shared ZMODDs are subjected to variable ordering by means of the existing Sifting technology, and the shared ZMODDs as shown in fig. 3 are obtained.
As can be seen from FIG. 3, c 1 ZMODD and c of 3 The ZMODD of (1) shares 2 input variable nodes surrounded by a dashed ellipse, by x 0 Node meridian x 1 The path from node to constant 1 node constitutes a common factor x 0 x 1 (ii) a Extracting a common factor x 0 x 1 After that, the shared ZMODDs are subjected to variable ordering by means of the existing Sifting technique, resulting in the shared ZMODDs as shown in fig. 4.
As can be seen from fig. 4, the ZMODDs of the 5 cubes no longer share any input variable nodes, and the co-factor extraction iteration process ends.
From fig. 4, the commonality factor extracted set of ESOP cubes shown in fig. 5 can be derived. The cube c can be known from the above process 1 And c 2 Sharing common factor x 2 x 3 Cube c 1 And c 3 Sharing common factor x 0 x 1 I.e. cube c 1 Including a common factor x 2 x 3 And x 0 x 1 Cube c 2 Including a common factor x 2 x 3 Cube c 3 Including a common factor x 0 x 1 ，c 4 And c 5 No common factor is extracted.
(3) The cubes in FIG. 5 are synthesized in turn based on the results of step (2).
In synthesis c 1 When, due to c 1 Including a common factor x 2 x 3 And x 0 x 1 Thus, first x 2 x 3 And x 0 x 1 Are combined into 1 st and 2 nd reversible logic gates as shown in fig. 6, and c is then added 1 To 3 rd and 4 th reversible logic gates as shown in fig. 6; similarly for c 2 And c 3 Reversible circuit synthesis is performed to obtain the 5 th to 8 th reversible logic gates and the 9th reversible logic gate in FIG. 6The inverse logic gate is used to restore the value on the 1 st line, and the 1 st and 2 nd lines in fig. 6 are auxiliary lines, the initial value of which is 0. Immediately after synthesis of c 4 And c 5 Due to c 4 And c 5 No common factors are extracted, so the 2 cubes are directly integrated, integrated c 4 The 10 th to 13 th reversible logic gates in FIG. 6 are obtained, the 14 th reversible logic gate is used to restore the value on the 2 nd line, and then c is synthesized 5 Resulting in the 15 th to 18 th reversible logic gates in fig. 6. The quantum cost of the reversible circuit is 46, and the number of quantum bits is 9.
Example 2
The embodiment applies the method in the invention to the functions in the citation document, extracts common factors among ESOP product terms for the functions, then carries out reversible circuit synthesis, calculates the quantum cost and the quantum digit number of the reversible circuit obtained by synthesis, and the result is shown in Table 1, wherein "N/A" indicates that the citation document does not give the result of the corresponding function.
TABLE 1 reversible circuit synthesis results
Citation of document [1]: lukac M, kameyama M, perkowski M, kerntopf P.composition of reversible logic function based on cup-reordering [ J ]. FACTA UNIVERSITATIS (NIS), 2011,24 (3): 403-422.
Citation of document [2]: parlapalli S P, vudadha C, srinivas M B. An ESOP based tube side reduction technique for Reversible circuits [ A ]. In Proceedings of the 9th International Conference on Reversible calculation [ C ], kolkata, india, 2017.
As can be seen from the results of table 1, although the number of quantum bits of the reversible circuit obtained by integrating the ESOPs of most functions is increased by the common factor extraction method between the ESOP product terms in the present invention, compared with the results in cited documents [1] and [2], the method in the present invention can reduce the quantum cost of the reversible circuit obtained by integrating the ESOPs for 77.42% of the functions. From a general perspective, the method of the present invention reduces the quantum cost of the reversible circuit integrated by ESOP by 31.86% compared to the best quantum cost results in cited documents [1] and [2 ].
Compared with the result of citation document [1], 63.33% of the 30 functions have lower quantum cost, 60% of the functions have lower quantum digits, and 33.33% of the functions have both lower quantum cost and lower quantum digits, because the common factor iterative extraction method based on shared ZMODD in the invention can better extract the common factors among multiple product terms by performing variable sorting on the input part of a cube and extracting the common factors among ESOP product terms by sharing input variable nodes, thereby being capable of reducing the quantum cost of the comprehensively obtained reversible circuit; the maximum common factor among the product terms is extracted as much as possible through a single character common factor merging strategy, so that the quantum digit of the reversible circuit obtained by synthesis can be reduced.
Compared with the result of the cited document [2], 87.76 percent of the 43 functions have lower quantum cost, because the common factor iterative extraction method based on the shared ZMODD in the invention can extract the maximum common factor among cubes with the quantity more than 2 by carrying out variable sequencing on the input part of the cube, utilizing the sharing of the input variable nodes to extract the common factor among ESOP product terms and combining a single character common factor combination strategy, thereby reducing the quantum cost of the reversible circuit obtained by synthesis.
By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:
the common factor extraction method in the patent of the invention represents an ESOP cube set by sharing a ZMODD, carries out variable sequencing on the shared ZMODD by means of the existing variable sequencing technology, extracts common factors among cubes according to the sharing of input variable nodes, can extract the common factors among cubes with the quantity larger than 2, and can also extract the maximum common factors among a plurality of cubes as much as possible, carries out balance between quantum cost and quantum digit, more importantly, reduces the quantum cost of the reversible circuit obtained comprehensively, and from the overall view, compared with the optimal quantum cost result in the citation document, the quantum cost of the reversible circuit is reduced by 31.86%.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. A reversible circuit synthesis method for extracting a common factor between ESOP product terms using a shared ZMODD, comprising the steps of:
s1, representing ESOP of a multi-output function by using a shared ZMODD;
s2, extracting common factors among ESOP product terms by the shared ZMODD in an iterative mode;
s3, reversible circuit synthesis is carried out according to the result of the step S2;
ESOP, exclusive-Sum-Of-Products, which represents the XOR Sum Of Products, is a logical representation Of a function based on AND-XOR operation, i.e. a representation form Of connecting a group Of product terms by XOR operation and adopting a cube set for representation; ZMODD, zero-suppressed Multiple-Output Decision Diagram, represents a Zero-suppressed Multiple-Output Decision Diagram, is a graphical representation of Multiple-Output cubes, and if an ESOP cube is represented as a ZMODD, then the set of ESOP cubes can be represented as a shared ZMODD;
the step S1 specifically includes:
s11, for a Boolean function with n inputs and m outputs, the ESOP cube c = [ i ] 0 ,i 1 ,…,i n-1 ,o 0 ,o 1 ,…,o m-1 ]，[i 0 ,i 1 ,…,i n-1 ]Is the input part of the cube, corresponding to ESOP multiplicationProduct term
i j Is e {0,1, - } corresponds to ∑ or ∑ respectively>
[o 0 ,o 1 ,…,o m-1 ]Is the output part of the cube, o k ∈{0,1}，o k The product term is expressed when =1
Belonging to function f k ；
S12, mapping each ESOP cube to a ZMODD, and inputting i to the cube j ，i j Mapping it to ZMODD input variable x if =1 j ，i j If =0, it is mapped to ZMODD input variable
i j = time without mapping; output o for cube k ，o k Mapping it to ZMODD output variable f when =1 k ，o k Mapping is not performed when = 0;
the step S2 specifically includes:
s21, performing variable sequencing on the shared ZMODD, then traversing the shared ZMODD in depth-first mode, and extracting common factors among cube input parts, namely ESOP product terms according to the fact whether input variable nodes are shared or not;
s22, when one input variable node is shared by a plurality of ZMODs, extracting a common factor formed by paths from the input variable node to a constant 1 node; iterating the process until no input variable nodes in the ZMODD are shared;
s23, traversing the shared ZMODD to obtain an ESOP cube set after common factor extraction when no input variable node is shared in the ZMODD any more, and recording common factors contained in each cube;
step S3 specifically includes:
sequentially synthesizing each cube of the ESOP, and when the synthesized cube contains a common factor, synthesizing the common factor contained in the cube into a reversible logic gate, and then synthesizing the cube; and directly carrying out synthesis on cubes without common factors extracted, and cascading reversible logic gates obtained by synthesis into a reversible circuit.
2. The reversible circuit synthesis method according to claim 1, wherein the variable sorting method in step S21 is a Sifting technique, and the common factor extracting operation in step S22 is performed by a division operation.
3. A reversible circuit synthesis method according to claim 1, characterized in that in synthesizing a common factor into a reversible logic gate, an auxiliary line having a value of constant 0 is used as a target line of the reversible logic gate obtained by the synthesis thereof, then all cubes containing the common factor are sequentially synthesized using the auxiliary line as a control line, and after all cubes containing the common factor are synthesized, the value of the auxiliary line is restored using the reversible logic gate for the synthesis of the remaining common factor.
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