CN112949862B - Novel reversible circuit synthesis method based on ESOP (extreme likelihood operation) representation model - Google Patents

Novel reversible circuit synthesis method based on ESOP (extreme likelihood operation) representation model Download PDF

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CN112949862B
CN112949862B CN202110189441.0A CN202110189441A CN112949862B CN 112949862 B CN112949862 B CN 112949862B CN 202110189441 A CN202110189441 A CN 202110189441A CN 112949862 B CN112949862 B CN 112949862B
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卜登立
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Abstract

The invention provides a novel reversible circuit comprehensive method based on an ESOP (extreme case operation) representation model, and relates to the technical field of reversible circuit and quantum circuit comprehensive design; the method comprises the steps of firstly, representing a multi-output Boolean function F by using SFDD, and identifying linear variables of each output function of the F; dividing the distribution linear variable for each output function by using a weighted bipartite graph, detecting the independence of the linear variable by using the SFDD, and sequencing the output functions of the distribution linear variable to determine the sequence of the integrated output functions; and according to the sequencing result, based on an MPMCT gate library, adopting ESOP to represent a model comprehensive reversible circuit. The invention solves the problem that the quantum bit number of the circuit obtained by the comprehensive reversible circuit based on the ESOP representation model is relatively high, and aims to reduce the quantum bit number of the circuit obtained by the comprehensive reversible circuit based on the ESOP representation model.

Description

Novel reversible circuit synthesis method based on ESOP (extreme likelihood operation) representation model
Technical Field
The invention relates to the technical field of reversible circuits and quantum circuit comprehensive design, in particular to a novel reversible circuit comprehensive method based on an ESOP (extreme case operation protocol) representation model.
Background
From the quantum computing application of the reversible logic, the reversible circuit has 2 technical indexes for measuring the quality, one is the quantum cost, and the other is the quantum digit. Reducing the quantum cost of a reversible circuit helps to reduce the fault-tolerant cost of its quantum circuit implementation. However, since qubits are a very precious hardware resource under current quantum processes, reducing the number of qubits is more conducive to the physical implementation of reversible circuits under current quantum processes.
The comprehensive reversible circuit based on the functional representation model and the ESOP (Exclusive-Sum-Of-Products) representation model can obtain a circuit with relatively less quantum bit number, and therefore, the comprehensive reversible circuit has more attention and application. For an irreversible Boolean function with n input numbers and m output numbers, the lower bound of the reversible realization of the required quantum bit number is max (n, m), and the upper bound is n + m. The comprehensive reversible circuit based on the functional representation model can follow the upper bound and the lower bound of the quantum digit, so that the quantum digit of the obtained circuit is relatively less, but the quantum cost is higher. Although the quantum cost of the circuit obtained by synthesizing the reversible circuit based on the ESOP representation model is relatively low, the obtained quantum bit number is relatively high because the quantum bit number only meets the upper bound constraint.
In summary, in order to promote the physical implementation of the reversible circuit under the current quantum process, it is necessary to find a new reversible circuit synthesis method based on the ESOP representation model, so as to reduce the quantum number of the obtained circuit while obtaining relatively low quantum cost.
Disclosure of Invention
The invention aims to provide a novel reversible circuit synthesis method based on an ESOP representation model, which can reuse the existing circuit lines in a circuit by identifying the linear variables of a function, thereby solving the problems in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a novel reversible circuit synthesis method based on ESOP representation model comprises the following steps:
s1, using the shared function decision graph SFDD to represent the multiple output boolean function F: {0,1}n→{0,1}mWhere n input variables form the set X ═ { X ═ X1,x2,…,xnF, m output functions form a set F ═ F1,f2,…,fm}; identifying each output function F of the multiple output Boolean function F according to the drawn SFDD graph G and the linear variable identification rulejLinear variable x ofiTo obtain a set of output functions
Figure BDA0002944791360000021
And linear variable set
Figure BDA0002944791360000022
And FLVAnd XLVThe relationship between
Figure BDA0002944791360000023
I.e. XLVIs at least FLVLinear variable of one of the functions, similarly, FLVContains at least one linear variable and the variable belongs to XLV；
The linear variable identification rule is specifically as follows:
given an SFDD graph G representing a multiple-output Boolean function F, an output function F is represented in the graph GjIs assumed by its root node
Figure BDA0002944791360000024
To node vkOf (2) a
Figure BDA0002944791360000025
Dominates the active pathway for the longest, and
Figure BDA0002944791360000026
to vkThere is no path between other nodes in the level of graph G, then when the path is
Figure BDA0002944791360000027
Using the variable xiLabeled node viWhen it is a linear node, xiIs fjA linear variable of (d);
for multiple output function F ═ F1,f2,…,fmH, each output function fjAll can use one FDD representation, assuming the representation fjThe root node of FDD is recorded as
Figure BDA0002944791360000028
In the SFDD graph G, the root node
Figure BDA0002944791360000029
And is prepared from
Figure BDA00029447913600000210
Reachable nodes and corresponding edges constitute the representation function fjThe FDD of (1); the SFDD graph G is divided into n +1 layers, node vkThe layer uses lev (v)k) Denotes, lev (v)k) Not less than 1; in the SFDD graph G, each node is labeled with one variable of the function F except for the terminal nodes at level n +1 which represent either constant 0 or constant 1, assuming that node vkUsing variable xiMarking, then node vkThe layers located in graph G also use lev (x)i) Denotes, lev (v)k)＝lev(xi) (ii) a If node vkIs node vjOne of the sub-nodes of (1), lev (v)k)＞lev(vj) And node vjAnd node vkThere is a directed edge between e (v) and usej,vk) Representing; for root node
Figure BDA0002944791360000031
And one is composed of
Figure BDA0002944791360000032
Reachable node vkAnd a set of nodes
Figure BDA0002944791360000033
If it is
Figure BDA0002944791360000034
Is that
Figure BDA0002944791360000035
The sub-nodes of (a) are,
Figure BDA0002944791360000036
is that
Figure BDA0002944791360000037
Sub-node (1 ≤ i ≤ l-1), vkIs that
Figure BDA0002944791360000038
The child node of (1), then the root node
Figure BDA0002944791360000039
And vkAnd an edge
Figure BDA00029447913600000310
And
Figure BDA00029447913600000311
form a strip of
Figure BDA00029447913600000312
To vkThe path of (1) is recorded as
Figure BDA00029447913600000313
If it is used
Figure BDA00029447913600000314
Is that
Figure BDA00029447913600000315
The 0-branch sub-node of (1),
Figure BDA00029447913600000316
is that
Figure BDA00029447913600000317
0 branch sub-node (1. ltoreq. i. ltoreq.l-1), vkIs that
Figure BDA00029447913600000318
0 branch of, then
Figure BDA00029447913600000319
Is an active pathway; if it is not
Figure BDA00029447913600000320
Or also
Figure BDA00029447913600000321
To vkIs the only path of
Figure BDA00029447913600000322
Is the dominant active pathway; if the path is to be
Figure BDA00029447913600000323
Elongation to vkA sub-node v oftNew path after
Figure BDA00029447913600000324
Is not an active pathway, or is not
Figure BDA00029447913600000325
To vtIs the only path of
Figure BDA00029447913600000326
Is the longest dominant active pathway;for a node viIf its 1-branch child node is a terminal node representing constant 1
Figure BDA00029447913600000339
And said node viTo the terminal node
Figure BDA00029447913600000340
If the edge of (1) is not a complementary edge, it is called viIs a linear node;
s2, using the weighted bipartite graph to combine the linear variables
Figure BDA00029447913600000338
Is allocated to at most a function set
Figure BDA00029447913600000327
To obtain an ordered function set
Figure BDA00029447913600000328
With ordered sets of variables
Figure BDA00029447913600000329
|FA|＝|XA|，FAAnd XAThere is a one-to-one mapping relationship between them;
s3, using SFDD graph G representing function F, the ordered function set obtained in step S2
Figure BDA00029447913600000330
The function of (1) is related to
Figure BDA00029447913600000331
Checking the independence of intermediate variables to determine ordered function sets
Figure BDA00029447913600000332
Middle function
Figure BDA00029447913600000333
The order in which they are combined is,obtaining an updated ordered function set
Figure BDA00029447913600000334
And updated set of ordered linear variables
Figure BDA00029447913600000335
|FL|＝|XL|，FLAnd XLThe relationship between them is still one-to-one mapping;
s4, according to the ordered function set obtained in the step S3
Figure BDA00029447913600000336
And ordered set of linear variables
Figure BDA00029447913600000337
Based on the MPMCT gate library, an ESOP representation model is adopted to synthesize a reversible circuit.
Preferably, step S2 specifically includes:
combining the SFDD graph G representing the multiple-output Boolean function F, the set F obtained in step S1LV、XLVAnd relationships
Figure BDA0002944791360000041
Drawing a bipartite graph, wherein the set XLVOf (1)
Figure BDA0002944791360000042
And set FLVFunction of (1)
Figure BDA0002944791360000043
Are all vertices in the bipartite graph; if it is not
Figure BDA0002944791360000044
Is that
Figure BDA0002944791360000045
Linear variable of (2), then vertex in bipartite graph
Figure BDA0002944791360000046
And vertex
Figure BDA0002944791360000047
A side is arranged between the two edges; if it is not
Figure BDA0002944791360000048
Is marked with
Figure BDA0002944791360000049
Root node of FDD
Figure BDA00029447913600000410
The weight of the edge is n, otherwise the weight is
Figure BDA00029447913600000411
Obtaining an ordered function set by using a Hungarian algorithm calculation
Figure BDA00029447913600000412
With ordered sets of variables
Figure BDA00029447913600000413
|FA|＝|XA|。
Preferably, step S3 specifically includes:
from the SFDD graph G representing the function F, first according to
Figure BDA00029447913600000414
Ascending pair of FAFunction of (1) and XAIf there are multiple root nodes
Figure BDA00029447913600000415
At the same level in graph G, according to
Figure BDA00029447913600000416
Descending order pair of FACorresponding function in (1) and XAThe respective variable in (1) is ordered;
order set
Figure BDA00029447913600000417
Collection of
Figure BDA00029447913600000418
For each one
Figure BDA00029447913600000419
Carrying out global independence check; i.e. if set
Figure BDA00029447913600000420
The function of the representation is independent of
Figure BDA00029447913600000421
Then order
Figure BDA00029447913600000422
Wherein' \\ is a set difference operation;
let FA＝FA\Fd，XA＝XA\Xd，
Figure BDA00029447913600000423
FbAnd XbIs an ordered set;
for each one
Figure BDA00029447913600000424
Local independence check was performed: if set
Figure BDA00029447913600000425
The function of the representation is independent of
Figure BDA00029447913600000426
Respectively to be provided with
Figure BDA00029447913600000427
And
Figure BDA00029447913600000428
appending to ordered set FbAnd XbAnd at the tail of
Figure BDA00029447913600000429
Figure BDA00029447913600000430
Up to FAAll of the functions in (1) depend on XAOne variable of (1);
for each one
Figure BDA00029447913600000431
Make an association with XAConditional independence check of medium variables: if in ordered set FAIs located in
Figure BDA00029447913600000432
A function after
Figure BDA00029447913600000433
Satisfy the requirement of
Figure BDA00029447913600000434
Depend on
Figure BDA00029447913600000435
And is
Figure BDA00029447913600000436
Then order
Figure BDA00029447913600000437
Let Fb＝Fb∪FA，Xb＝Xb∪XA；FL＝Fd∪Fb，XL＝Xd∪XbObtaining an ordered set FLAnd XL。
Preferably, in step S4, the model synthesis reversible circuit is represented by an ESOP:
n circuit lines are added, and the input variable set X of the multi-output boolean function F is used as { X }1,x2,…,xnMarking variables in the circuit lines, and calling the n circuit lines as input variable lines;
② if
Figure BDA0002944791360000051
Then the set F \ F is first alignedLESOP simplification is carried out on the expressed function to obtain the simplest ESOP expansion, and then | F \ F is addedLThe I auxiliary circuit line maps the product term in ESOP expansion into the cascade of MPMCT gates and uses the I F/F respectivelyLThe | F \ F is stored by | auxiliary circuit lineLThe calculation results of | functions;
③ ordered function set
Figure BDA0002944791360000052
Each function in
Figure BDA0002944791360000053
Firstly, ESOP simplification is carried out to obtain the simplest ESOP expansion, and then
Figure BDA0002944791360000054
Each of the ESOP product terms of (a) is mapped to a cascade of MPMCT gates and is referred to using the reference numeral
Figure BDA0002944791360000055
The input variable line of (2) stores the calculation result of the product term, and finally the label is used
Figure BDA0002944791360000056
Input variable line save function
Figure BDA0002944791360000057
The calculation result of (2).
The invention has the beneficial effects that:
the invention discloses a novel reversible circuit synthesis method based on an ESOP (extreme case resolution) representation model, which can reduce the quantum digit of a circuit obtained by synthesizing a reversible circuit based on the ESOP representation model. For function F with n variables and m outputs, the existing reversible circuit synthesis method based on ESOP representation modelThe quantum digit of the obtained circuit is n + m, and the quantum digit of the circuit obtained by the reversible circuit synthesis method based on the functional representation model follows the lower bound and the upper bound of the quantum digit: max (n, m) and n + m. The quantum digit of the circuit obtained by the method is n + m-FL|(0≤|FLMin (n, m)) and follows the upper and lower bound constraints of quantum digit, compared with the existing reversible circuit synthesis method based on ESOP representation model, the quantum digit of the circuit is reduced by | FL|。
Drawings
Fig. 1 is a schematic diagram of an FDD node provided in embodiment 1;
FIG. 2 is a SFDD representing the function mod5d2_17 in the embodiment in example 1;
FIG. 3 is a linear variable distribution diagram in a specific implementation of example 1;
fig. 4 is a reversible circuit resulting from the synthesis of the function mod5d2_17 in the embodiment of example 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
The embodiment provides a novel reversible circuit synthesis method based on an ESOP representation model, which comprises the following steps:
s1, using a shared function decision diagram SFDD to represent a multi-output Boolean function F: {0,1}n→{0,1}mWhere n input variables form the set X ═ { X ═ X1,x2,…,xnF, m output functions form a set F ═ F1,f2,…,fm}; identifying each output function F of the multiple output Boolean function F according to the drawn SFDD graph G and the linear variable identification rulejLinear variable x ofiTo obtain a set of output functions
Figure BDA0002944791360000061
And linear variable set
Figure BDA0002944791360000062
And FLVAnd XLVThe relationship between
Figure BDA0002944791360000063
Namely XLVIs at least FLVLinear variable of one of the functions, similarly, FLVContains at least one linear variable and the variable belongs to XLV；
The linear variable identification rule in the above steps is specifically as follows:
given an SFDD graph G representing a multiple-output Boolean function F, an output function F is represented in the graph GjFDD, assuming a root node from the FDD
Figure BDA0002944791360000064
To node vkOf (2) a
Figure BDA0002944791360000065
Dominates the active pathway for the longest, and
Figure BDA0002944791360000066
to lev (v) in FIG. Gk) No path exists between other nodes in the layer, then when the path is
Figure BDA0002944791360000067
Using the variable xiWhen the marked nodes are linear nodes, xiIs fjIs used as a linear variable.
The concepts and terms involved in the above linear variable recognition rules are explained in detail as follows:
the function decision graph FDD is a directed acyclic graph G ═ (V, E).
Figure BDA0002944791360000068
Is a set of nodes, where ^ t and ^ t
Figure BDA0002944791360000069
Terminal nodes, v, representing constants 0 and 1, respectivelykAre non-terminal nodes, each having 2 sub-nodes (a 0-branch sub-node and a 1-branch sub-node). E ═ EiI is more than or equal to 1 and less than or equal to E is taken as an edge set, if v iskIs vjSub-node of (v) thenjAnd vkDirected edge usage e (v) betweenj,vk)＝vj→vkAnd (4) showing. Node vkThe edge between its 0-branch sub-node uses a dashed line segment, and the edge between its 1-branch sub-node uses a real line segment.
For n variables X ═ X1,x2,…,xnF {0,1} ofn→ 0,1, the FDD representation is obtained by applying a positive or negative Davio decomposition to n variables in sequence, with one root node. The FDD is divided into n +1 layers, the root node is positioned at the 1 st layer, the terminal node is positioned at the n +1 st layer, and the node vkThe layer uses lev (v)k) And (4) showing. Except for the terminal nodes at the n +1 th level, the nodes at each level are labeled with a variable, assuming vkUsing xjMarking, then vkLayers located in FDD also use lev (x)j) Shows that lev (x) is clearly evidentj)＝lev(vk). If v iskIs vjThe child node of (c) has lev (v)j)＜lev(vk). Node vkCan represent a function using f (v)k) And (4) representing, namely a node function. For the terminal nodes, there are: f (t) is 0,
Figure BDA0002944791360000078
FIG. 1 shows a schematic diagram of a FDD node, as can be seen from FIG. 1, node v1There are 2 sub-nodes v2And v3(v2Or v3May be a terminal node), v2Is 0 branch child node, v3Is a 1-branch sub-node. Node v1Using variable x1And (4) marking. The hollow circle on an edge indicates that the edge is a complementary edge, and the meaning of the hollow circle is a function represented by a node of the end point of the edgeAnd (6) taking the inverse. For FIG. 1, assume x1Is a positive Davio decomposition, then
Figure BDA0002944791360000071
Multi-output boolean function F: {0,1}n→{0,1}mThe n (input) variables form a set X ═ X1,x2,…,xnF, m output functions form a set F ═ F1,f2,…,fm}. If an output function can be expressed as
Figure BDA0002944791360000072
Or
Figure BDA0002944791360000073
And the function g is independent of the variable xiThen call xiIs fjIs used as a linear variable.
For a multiple output Boolean function F, each output function FjAll can use one FDD representation, assuming the representation fjThe root node of FDD is recorded as
Figure BDA0002944791360000074
If the same variables all adopt the same decomposition type when constructing the FDDs of m output functions, the m FDDs form the SFDD representing the function F by sharing the subgraph and have m root nodes
Figure BDA0002944791360000075
In SFDD, the root node
Figure BDA0002944791360000076
And is composed of
Figure BDA0002944791360000077
Reachable nodes and corresponding edges constitute the representation function fjThe FDD of (1). Since the function F has n variables, its SFDD is divided into n +1 layers, and the terminal nodes are located at the n +1 th layer, except that it is possible that not all the root nodes are located at the 1 st layer.
There are two arbitrary nodes vjAnd vkAnd a set of nodes
Figure BDA0002944791360000081
Suppose lev (v)j)＜lev(vk) I.e. vkIn SFDD at vjAnd by node vjReachable node vk. If it is
Figure BDA0002944791360000082
Is vjThe sub-nodes of (a) are,
Figure BDA0002944791360000083
is that
Figure BDA0002944791360000084
Sub-node (1 ≤ i ≤ l-1), vkIs that
Figure BDA0002944791360000085
Is a sub-node of, then node vj、
Figure BDA0002944791360000086
And vkAnd an edge
Figure BDA0002944791360000087
And
Figure BDA0002944791360000088
form a strip consisting of vjTo vkThe path of (1) is recorded as
Figure BDA0002944791360000089
If it is used
Figure BDA00029447913600000810
Is vjThe 0-branch sub-node of (1),
Figure BDA00029447913600000811
is that
Figure BDA00029447913600000812
0 branch of (1 ≦ i ≦ l-1), vkIs that
Figure BDA00029447913600000813
0 branch of (3), then
Figure BDA00029447913600000814
Is an active pathway; if it is used
Figure BDA00029447913600000815
Or vjTo vkIs the only path of
Figure BDA00029447913600000816
Is the dominant active pathway. For the representation fjRoot node of FDD
Figure BDA00029447913600000817
And one is composed of
Figure BDA00029447913600000818
Reachable node vkKnown path of travel
Figure BDA00029447913600000819
Is dominant in the active pathway, if the pathway is
Figure BDA00029447913600000820
Addition of vkIs assumed to be vt) And an edge e (v)k,vt) New path
Figure BDA00029447913600000821
Is not an active pathway, or is not
Figure BDA00029447913600000822
To vtIs called the unique path
Figure BDA00029447913600000823
The longest dominant active pathway.
For node viIf its 1-branch child node is a terminal node representing constant 1
Figure BDA00029447913600000830
And v isiTo the terminal node
Figure BDA00029447913600000831
If the edge of (1) is not a complementary edge, it is called viAre linear nodes.
S2, distributing linear variables for output functions containing the linear variables by using a weighted bipartite graph
Combining the variables using a weighted bipartite graph
Figure BDA00029447913600000824
Is assigned to at most a function set
Figure BDA00029447913600000825
To obtain an ordered function set
Figure BDA00029447913600000826
With ordered sets of variables
Figure BDA00029447913600000827
|FA|＝|XA|，FAAnd XAThere is a one-to-one mapping relationship between them.
Distributing linear variables to output functions to obtain an ordered set FAAnd XAThe method specifically comprises the following steps:
combining the SFDD graph G representing the multi-output Boolean function F, and obtaining the function set F from the step S1LVVariable set XLVAnd relationships
Figure BDA00029447913600000828
Drawing a bipartite graph and a function set FLVFunction of (1)
Figure BDA00029447913600000829
And set of variables XLVOf (1)
Figure BDA0002944791360000091
The vertices in the bipartite graph are all; if variable
Figure BDA0002944791360000092
Is a function of
Figure BDA0002944791360000093
Linear variable of (2), then vertex in bipartite graph
Figure BDA0002944791360000094
And vertex
Figure BDA0002944791360000095
A side is arranged between the two edges; if it is not
Figure BDA0002944791360000096
Is marked with
Figure BDA0002944791360000097
Root node of FDD
Figure BDA0002944791360000098
The weight of the edge is n, otherwise the weight is
Figure BDA0002944791360000099
Mixing XLVIs assigned to at most FLVThe problem of one of the functions can be considered as a maximum weighted binary matching problem. Solving the problem using a Hungarian algorithm to solve the allocation problem, resulting in an ordered set of functions
Figure BDA00029447913600000910
With ordered sets of variables
Figure BDA00029447913600000911
|FA|＝|XA|。
And S3, utilizing the SFDD to carry out variable independence check on the output functions of the distributed linear variables, and determining the sequence of the output functions.
Using SFDD graph G representing function F, for
Figure BDA00029447913600000912
The function of (1) is related to
Figure BDA00029447913600000913
Checking for independence of intermediate variables, determining
Figure BDA00029447913600000914
The order of the medium functions is integrated to obtain an ordered function set
Figure BDA00029447913600000915
And ordered variable sets
Figure BDA00029447913600000916
|FL|＝|XL|，FLAnd XLThe relationship between them is still a one-to-one mapping.
The order in which the decision output functions are integrated, i.e. the ordered set F, is given belowLAnd XLThe steps of (1):
first, using SFDD graph G representing function F, the method follows
Figure BDA00029447913600000917
Ascending pair of FAFunction of (1) and XAIf there are multiple root nodes
Figure BDA00029447913600000918
At the same level in graph G, according to
Figure BDA00029447913600000919
Descending order pair of FACorresponding function in (1) and XAThe respective variable in (1) is ordered;
② order set
Figure BDA00029447913600000920
Collection
Figure BDA00029447913600000921
For each one
Figure BDA00029447913600000922
Performing a global independence check: i.e. if set
Figure BDA00029447913600000923
The function of the representation is independent of
Figure BDA00029447913600000924
Then order
Figure BDA00029447913600000925
Where "\\" is a set difference operation.
Fourthly, FA＝FA\Fd，XA＝XA\Xd，
Figure BDA00029447913600000926
FbAnd XbIs an ordered set.
For each one
Figure BDA00029447913600000927
Local independence check was performed: i.e. if set
Figure BDA00029447913600000928
The function of the representation is independent of
Figure BDA00029447913600000929
Respectively to be provided with
Figure BDA00029447913600000930
And
Figure BDA00029447913600000931
appending to an ordered setFbAnd XbAnd at the tail of
Figure BDA00029447913600000932
Up to FAAll of the functions in (1) depend on XAOne variable in (c).
For each
Figure BDA0002944791360000101
Make an association with XAConditional independence check of medium variables: if in ordered set FAIs located in
Figure BDA0002944791360000102
A function after
Figure BDA0002944791360000103
Satisfy the requirements of
Figure BDA0002944791360000104
Depend on
Figure BDA0002944791360000105
And is
Figure BDA0002944791360000106
Then order
Figure BDA0002944791360000107
Seventhly, firstly make Fb＝Fb∪FA，Xb＝Xb∪XA(ii) a Then order FL＝Fd∪Fb，XL＝Xd∪XbTo obtain an ordered set FLAnd XL。
And S4, according to the sequencing result, based on an MPMCT (Mixed-polar Multiple Control Toffoli) door library, adopting ESOP to represent the model comprehensive reversible circuit.
Adding n circuit lines, using X ═ X respectively1,x2,…,xnThe variables in the are labeled, and the n circuit lines are called input variable lines.
Determining F \ FLWhether or not it is empty, if
Figure BDA0002944791360000108
Directly entering the step III; otherwise, the step II is carried out;
② first to the set F \ FLESOP simplification is carried out on the expressed function to obtain the simplest ESOP expansion, and then | F \ F is addedLI auxiliary circuit lines map the product term in ESOP expansion to the cascade of MPMCT gates and use the I F \ F respectivelyLThe | F \ F is saved by | auxiliary circuit linesLThe result of the computation of | functions.
③ ordered function set
Figure BDA0002944791360000109
Each function in (1)
Figure BDA00029447913600001010
ESOP simplification is firstly carried out to obtain the simplest ESOP expansion, and then the minimum ESOP expansion is carried out
Figure BDA00029447913600001011
Each of the ESOP product terms of (a) is mapped to a cascade of MPMCT gates and is referred to using the reference numeral
Figure BDA00029447913600001012
The input variable line of (2) stores the calculation result of the product term, and finally the label is used
Figure BDA00029447913600001013
Input variable line save function
Figure BDA00029447913600001014
The calculation result of (2).
For the synthesis of the functions, the existing circuit lines are reused, and no additional auxiliary circuit line is needed, so that the quantum bit number required by the circuit is reduced.
The specific implementation mode is as follows:
the present embodiment specifically explains the present invention by taking the RevLib function mod5d2_17 as an example.
1) Identification of linear variables for individual output functions using SFDD
The SFDD representing the function mod5d2_17 is shown in FIG. 2, where in the SFDD shown in FIG. 2, node v is1～v5Are respectively the output function f1～f5A root node of, wherein v1、v3And v4At layer 1 of the SFDD. Route of travel
Figure BDA0002944791360000111
And
Figure BDA0002944791360000112
respectively, represent the output function f1～f4The longest dominant active path of FDD, denoted f5The longest dominant active path of FDD of (1) comprises only the root node v5。
From the definition of the linear nodes, the node v in FIG. 22～v6And v9Are all linear nodes and are respectively positioned in the 5 longest dominant active paths. Knowing x from linear variable identification rules1Is f1Linear variable of x2And x3Is f2Linear variable of x3And x4Is f3Linear variable of (a), x4And x5Is f4Linear variable of x5Is f5Of linear variable, i.e. FLV＝{f1,f2,f3,f4,f5}，XLV＝{x1,x2,x3,x4,x5} relationship between two sets
Figure BDA0002944791360000113
As previously described.
2) A linear variable is assigned to an output function including the linear variable by using a weighted bipartite graph.
Set F obtained according to the previous stepLV＝{f1,f2,f3,f4,f5}，XLV＝{x1,x2,x3,x4,x5And the relationship between the two sets
Figure BDA0002944791360000114
The weighted bipartite graph shown in FIG. 3(a) may be drawn in conjunction with the SFDD of FIG. 2. Solving the maximum weighted binary matching problem using the Hungarian algorithm to solve the assignment problem can result in a linear variable assignment result as shown in fig. 3(b), thereby obtaining an ordered set FA＝{f2,f4,f5,f1,f3}，XA＝{x2,x4,x5,x1,x3And the relationship between the two sets is one-to-one mapping.
3) With SFDD, a variable independence check is performed on the output functions to which the linear variables have been assigned, and the order in which these output functions are integrated is determined.
First, the SFDD map G shown in FIG. 2 is used to follow
Figure BDA0002944791360000115
Ascending pair of FAFunction of (1) and XADue to the root node v1、v3And v4At the same level in graph G, according to lev (x)3)、lev(x1) And lev (x)4) Sequence of (1) to (f)3、f1And f4Sorting to obtain updated ordered set FA＝{f3,f1,f4,f2,f5}，XA＝{x3,x1,x4,x2,x5}。
② order set
Figure BDA0002944791360000116
Collection
Figure BDA0002944791360000117
Checking the global independence of variables: due to the function FA\{f1}＝{f2,f4,f5,f3Independent of x1Obtaining Fd＝{f1}，Xd＝{x1}。
Fourthly, FA＝FA\Fd＝{f3,f4,f2,f5}，XA＝XA\Xd＝{x3,x4,x2,x5}，
Figure BDA0002944791360000121
FbAnd XbIs an ordered set.
Checking local independence of variables: known as FA＝{f3,f4,f2,f5}，XA＝{x3,x4,x2,x5}. For variable x2Due to the function FA\{f2}＝{f3,f4,f5Independent of x2Obtaining Fb＝{f2}，Xb＝{x2}；FA＝{f3,f4,f5}，XA＝{x3,x4,x5}. For variable x3Due to the function FA\{f3}＝{f4,f5Independent of x3Obtaining Fb＝{f2,f3}，Xb＝{x2,x3}；FA＝{f4,f5}，XA＝{x4,x5}. Due to the function f4And f5All depend on x5The local independence check of the variables ends.
Condition independence examination of variables: known as FA＝{f4,f5}，XA＝{x4,x5}; for function f4Function f5After but due to f5Independent of x4Thus F isA＝{f4,f5}，XA＝{x4,x5}。
Seventhly, firstly make Fb＝Fb∪FA，Xb＝Xb∪XA(ii) a Then order FL＝Fd∪Fb，XL＝Xd∪XbFinally, an ordered function set F can be obtainedL＝{f1,f2,f3,f4,f5X and set of ordered linear variablesL＝{x1,x2,x3,x4,x5}。
4) And according to the sequencing result, based on the MPMCT gate library, adopting ESOP to represent the model comprehensive reversible circuit.
Adding 5 circuit lines, using x1,x2,x3,x4,x5Variables in the are labeled and referred to as input variable lines, as shown in FIG. 4.
② because
Figure BDA0002944791360000122
Go directly to the next step.
Pair ordered function set FL＝{f1,f2,f3,f4,f5Each function in f is ESOP simplified to obtain the simplest ESOP expansion, and then f is expandedjEach of the ESOP product terms of (a) is mapped to a cascade of MPMCT gates and is referred to using the reference numeral
Figure BDA0002944791360000123
The input variable line of (a) holds the result of the product term. 5 existing circuit lines in the circuit are reused in the step, and no auxiliary circuit line is additionally arranged; the result is a reversible circuit as shown in fig. 4.
The number of quantum bits of the circuit is 5 (the number of quantum bits is the same as the number of circuit lines in the circuit), the quantum cost realized by the NCV quantum circuit is 31, and the quantum cost 'T-depth' realized by the Clifford + T quantum circuit is 12.
The above embodiment is only representative of a number of functions, and the method of the present invention can be applied to many other functions, with the following results:
(1) compared with the results of the existing reversible circuit synthesis method based on ESOP representation model
The reversible circuit synthesis methods in citations [1] and [2] are the latest reversible circuit synthesis methods based on ESOP representation models with better results, and the 2 citations all use quantum bit numbers and quantum cost realized by NCV quantum circuits of reversible circuits to evaluate the advantages and disadvantages of the reversible circuits. Reversible circuit synthesis of a set of functions using the method of the present invention was performed and compared with the results of the methods of cited documents [1] and [2], as shown in table 1.
The "optimum results of citations [1] and [2] in table 1" are derived from citations [1] and [2], which results are the optimum results of the circuit in these 2 citations in view of quantum cost. In addition, "n" represents the variable number of the function, "m" represents the output function number of the function, "QB" represents the quantum bit number, "QC" represents the quantum cost realized by the NCV quantum circuit of the reversible circuit, and "improvement" represents the percentage of reduction in the quantum bit number and the quantum cost of the result obtained by the method of the present invention with respect to "the optimal result of citations [1] and [2 ].
As can be seen from Table 1, the method of the present invention can obtain fewer quanta for the 18 functions, and the number of quanta is reduced by 41.18% at the maximum (function 5xp1) and 0.77% at the minimum (function e64) compared with the "optimal results of citations [1] and [2 ]. Because some of the 18 functions have linear variables, the method of the present invention is able to identify these linear variables and reuse the circuit lines labeled with these linear variables. Regarding the quantum cost, the method of the present invention reduces the quantum cost with only partial functions, as compared with "the optimal results of cited documents [1] and [2 ]. However, from an average point of view, the method of the present invention reduces the quantum bit number and the quantum cost by 5.96% and 3.17%, respectively, as compared with "the best results of cited documents [1] and [2 ].
Table 1 comparison of the results with analogous methods
Figure BDA0002944791360000141
Reference is made to the document [1] Parlapalli S P, Vudadha C, Srinivas M.B. an ESOP based cup computing technique for converting circuits, International Conference on converting computing, 2017, pp.127-140.
Reference is made to Bandyopadhyay C.Parekh S.Rahaman H.improved circuit synthesis for explicit-sum-of-product-based reproducible circuits IET Computers & Digital Techniques,2018,12(4): 167-175.
(2) Comparison of results with a reversible circuit synthesis method based on a functional representation model
The reversible circuit synthesis method in citation [3] is the latest reversible circuit synthesis method based on a functional representation model, and evaluates the quality of a reversible circuit using the quantum bit number and a quantum cost metric realized by the Clifford + T quantum circuit of the reversible circuit. Reversible circuit synthesis of a set of functions was performed using the method of the present invention and compared with the results of the method in cited document [3], as shown in table 2. In table 2, "QB" represents the quantum bit number, and "T-depth" is the quantum cost metric achieved by the Clifford + T quantum circuit of the reversible circuit.
As can be seen from table 2, in the 63 functions, compared with the results of the method in cited document [3], there are 54 functions, the method of the present invention can obtain the same quantum bit number, and there are 5 functions, the method of the present invention can obtain fewer quantum bits, only 4 functions, and the method of the present invention can obtain more quantum bits. From the quantum cost measure "T-depth", the method of the invention can obtain lower quantum cost for all 63 functions. From the overall average perspective, the method of the invention can obtain the quantum digit number basically equivalent to that of the method in the citation document [3], but reduces the quantum cost by 2 orders of magnitude.
Table 2 comparison of the results with different classes of methods
Figure BDA0002944791360000151
Figure BDA0002944791360000161
Figure BDA0002944791360000171
Reference is made to Zulehner A, Wille R.one-pass Design of reversible Circuits, combining and synthesizing for reversible Circuits, IEEE Transactions on Computer-aid Design of Integrated Circuits and Systems,2018,37(5): 996-1008.
By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:
for a function F with n variables and m outputs, the quantum bit number of the circuit obtained by the existing reversible circuit synthesis method based on the ESOP representation model is n + m, and the quantum bit number of the circuit obtained by the reversible circuit synthesis method based on the function representation model follows the lower bound and the upper bound of the quantum bit number: max (n, m) and n + m. The quantum digit of the circuit obtained by the method described in the invention is n + m-FLCompared with the existing reversible circuit synthesis method based on ESOP representation model, the quantum bit number of the circuit is reduced by FLL. In addition, | FLMin (n, m), the quantum digit of the circuit obtained by the method is max (n, m); in the worst case, | FLThe quantum digit of the circuit obtained by the method is n + m, and the lower bound and the upper bound of the quantum digit are also followed: max (n, m) and n + m.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.

Claims (1)

1. A novel reversible circuit synthesis method based on ESOP representation model is characterized by comprising the following steps:
s1, representing multiple output Boolean by using shared function decision diagram SFDDFunction F: {0,1}n→{0,1}mWhere n input variables form the set X ═ { X ═ X1,x2,…,xnH, m output function constituent sets F ═ F1,f2,…,fm}; identifying each output function F of the multi-output Boolean function F according to the drawn SFDD graph G and the linear variable identification rulejLinear variable x ofiTo obtain a set of output functions
Figure FDA0003602929800000011
And linear variable set
Figure FDA0003602929800000012
And FLVAnd XLVThe relationship between
Figure FDA0003602929800000013
Namely XLVIs at least FLVLinear variable of one of the functions, similarly, FLVContains at least one linear variable and the variable belongs to XLV；
The linear variable identification rule is specifically as follows:
given an SFDD graph G representing a multiple-output Boolean function F, an output function F is represented in the graph GjIs assumed by its root node
Figure FDA0003602929800000014
To node vkOf (2) a
Figure FDA0003602929800000015
Dominates the active pathway for the longest, and
Figure FDA0003602929800000016
to vkIf there is no path between other nodes in the level of graph G, then the path is not present
Figure FDA0003602929800000017
Using the variable xiLabeled node viWhen it is a linear node, xiIs fjA linear variable of (d);
for multiple output function F ═ F1,f2,…,fmH, each output function fjAll can use one FDD representation, assuming the representation fjThe root node of FDD is recorded as
Figure FDA0003602929800000018
In the SFDD graph G, the root node
Figure FDA0003602929800000019
And is composed of
Figure FDA00036029298000000110
Reachable nodes and corresponding edges constitute the representation function fjThe FDD of (1); the SFDD graph G is divided into n +1 layers, node vkThe layer uses lev (v)k) Denotes, lev (v)k) Not less than 1; in the SFDD graph G, each node is labeled with one variable of the function F except for the terminal nodes at level n +1 which represent either constant 0 or constant 1, assuming that node vkUsing variable xiMarking, then node vkThe layers located in graph G also use lev (x)i) Denotes, lev (v)k)＝lev(xi) (ii) a If node vkIs node vjOne of the sub-nodes of (1), lev (v)k)＞lev(vj) And node vjAnd node vkThere is a directed edge between e (v) and usej,vk) Represents; for root node
Figure FDA00036029298000000111
And one is composed of
Figure FDA00036029298000000112
Reachable node vkAnd a set of nodes
Figure FDA00036029298000000113
If it is
Figure FDA00036029298000000114
Is that
Figure FDA00036029298000000115
The sub-nodes of (a) are,
Figure FDA00036029298000000116
is that
Figure FDA00036029298000000117
I is more than or equal to 1 and less than or equal to l-1, vkIs that
Figure FDA00036029298000000118
The child node of (1), then the root node
Figure FDA0003602929800000021
And vkAnd an edge
Figure FDA0003602929800000022
And
Figure FDA0003602929800000023
form a strip of
Figure FDA0003602929800000024
To vkThe path of (1) is recorded as
Figure FDA0003602929800000025
If it is not
Figure FDA0003602929800000026
Is that
Figure FDA0003602929800000027
The 0-branch sub-node of (1),
Figure FDA0003602929800000028
is that
Figure FDA0003602929800000029
0 branch sub-node 1 is more than or equal to i and less than or equal to l-1, vkIs that
Figure FDA00036029298000000210
0 branch of, then
Figure FDA00036029298000000211
Is an active pathway; if it is not
Figure FDA00036029298000000212
Or also
Figure FDA00036029298000000213
To vkIs the only path of
Figure FDA00036029298000000214
Is the dominant active pathway; if the path is to be
Figure FDA00036029298000000215
Elongation to vkA sub-node v oftNew path after
Figure FDA00036029298000000216
Is not an active pathway, or is not
Figure FDA00036029298000000217
To vtIs the only path of
Figure FDA00036029298000000218
Is the longest dominant active pathway; for a node viIf its 1-branch child node is a terminal node representing constant 1
Figure FDA00036029298000000232
And said node viTo the terminal node
Figure FDA00036029298000000233
If the edge of (1) is not a complementary edge, it is called viIs a linear node;
s2, using the weighted bipartite graph to combine the linear variables
Figure FDA00036029298000000219
Is assigned to at most a function set
Figure FDA00036029298000000220
To obtain an ordered function set
Figure FDA00036029298000000221
With ordered sets of variables
Figure FDA00036029298000000222
|FA|＝|XA|，FAAnd XAThere is a one-to-one mapping relationship between them;
s3, using SFDD graph G representing function F, the ordered function set obtained in step S2
Figure FDA00036029298000000223
Is about
Figure FDA00036029298000000224
Checking independence of intermediate variables to determine ordered function sets
Figure FDA00036029298000000225
Middle function
Figure FDA00036029298000000226
The order in which they are combined is,obtaining an updated ordered function set
Figure FDA00036029298000000227
And updated set of ordered linear variables
Figure FDA00036029298000000228
|FL|＝|XL|，FLAnd XLThe relationship between them is still one-to-one mapping;
s4, according to the ordered function set obtained in the step S3
Figure FDA00036029298000000229
And ordered set of linear variables
Figure FDA00036029298000000230
Based on an MPMCT gate library, an ESOP representation model comprehensive reversible circuit is adopted;
step S2 specifically includes:
combining the SFDD graph G representing the multiple-output Boolean function F, the set F obtained in step S1LV、XLVAnd relationships
Figure FDA00036029298000000234
Drawing a bipartite graph, wherein the set XLVOf (1)
Figure FDA00036029298000000231
And set FLVFunction of (1)
Figure FDA0003602929800000031
Are all vertices in the bipartite graph; if it is not
Figure FDA0003602929800000032
Is that
Figure FDA0003602929800000033
Linear variable of (2), top of bipartite graphDot
Figure FDA0003602929800000034
And vertex
Figure FDA0003602929800000035
A side is arranged between the two edges; if it is not
Figure FDA0003602929800000036
Is marked with
Figure FDA0003602929800000037
Root node of FDD
Figure FDA0003602929800000038
The weight of the edge is n, otherwise the weight is
Figure FDA0003602929800000039
Obtaining an ordered function set by using a Hungarian algorithm calculation
Figure FDA00036029298000000310
With ordered sets of variables
Figure FDA00036029298000000311
|FA|＝|XA|；
Step S3 specifically includes:
from the SFDD graph G representing the function F, first according to
Figure FDA00036029298000000312
Ascending pair of FAFunction of (1) and XAIf there are multiple root nodes
Figure FDA00036029298000000313
At the same level in graph G, according to
Figure FDA00036029298000000314
In descending order of FACorresponding function in (1) and XAThe respective variable in (1) is ordered;
order set
Figure FDA00036029298000000315
Collection
Figure FDA00036029298000000316
For each one
Figure FDA00036029298000000317
Carrying out global independence check; i.e. if set
Figure FDA00036029298000000318
The function of the representation is independent of
Figure FDA00036029298000000319
Then order
Figure FDA00036029298000000320
Wherein' \\ is a set difference operation;
let FA＝FA\Fd，XA＝XA\Xd，
Figure FDA00036029298000000321
FbAnd XbIs an ordered set;
for each one
Figure FDA00036029298000000322
Local independence check was performed: if set
Figure FDA00036029298000000323
The function of the representation is independent of
Figure FDA00036029298000000324
Respectively to be provided with
Figure FDA00036029298000000325
And
Figure FDA00036029298000000326
appending to ordered set FbAnd XbAnd at the tail of
Figure FDA00036029298000000327
Figure FDA00036029298000000328
Up to FAAll of the functions in (1) depend on XAOne variable of (1);
for each one
Figure FDA00036029298000000329
Make an association with XAConditional independence check of medium variables: if in ordered set FAIs located in
Figure FDA00036029298000000330
A function after
Figure FDA00036029298000000331
Satisfy the requirement of
Figure FDA00036029298000000332
Depend on
Figure FDA00036029298000000333
And is
Figure FDA00036029298000000334
Then order
Figure FDA00036029298000000335
Let Fb＝Fb∪FA，Xb＝Xb∪XA；FL＝Fd∪Fb，XL＝Xd∪XbObtaining an ordered set FLAnd XL；
In step S4, an ESOP representation model synthesis reversible circuit is used:
adding n circuit lines, and using input variable set X of multiple output Boolean function F as { X }1,x2,…,xnMarking variables in the circuit lines, and calling the n circuit lines as input variable lines;
② if
Figure FDA0003602929800000041
Then the set F \ F is first alignedLESOP simplification is carried out on the expressed function to obtain the simplest ESOP expansion, and then | F \ F is addedLI auxiliary circuit lines map the product term in ESOP expansion to the cascade of MPMCT gates and use the I F \ F respectivelyLThe | F \ F is stored by | auxiliary circuit lineLThe calculation results of | functions;
③ ordered function set
Figure FDA0003602929800000042
Each function in
Figure FDA0003602929800000043
Firstly, ESOP simplification is carried out to obtain the simplest ESOP expansion, and then
Figure FDA0003602929800000044
Each of the ESOP product terms of (a) is mapped to a cascade of MPMCT gates and is referred to using the reference numeral
Figure FDA0003602929800000045
The input variable line of (2) stores the calculation result of the product term, and finally the label is used
Figure FDA0003602929800000046
Is transported byIn-variable line save function
Figure FDA0003602929800000047
The calculation result of (2).
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