CN110428862A - A kind of shift register circuit and its driving method and display device - Google Patents
A kind of shift register circuit and its driving method and display device Download PDFInfo
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- CN110428862A CN110428862A CN201910703620.4A CN201910703620A CN110428862A CN 110428862 A CN110428862 A CN 110428862A CN 201910703620 A CN201910703620 A CN 201910703620A CN 110428862 A CN110428862 A CN 110428862A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a kind of shift register circuit and its driving method and display devices, comprising: the shift register of multi-stage cascade；Shift register includes: input module, pull-up module, pull-down module, output module and reseting module；Input module is electrically connected with first node N1, second node N2 and input terminal respectively, pull-up module is electrically connected with the first clock end and N2 respectively, pull-down module is electrically connected with second clock end and N2 respectively, output module is electrically connected with N1, N2, second clock end and scanning output end respectively, and reseting module is electrically connected with reset terminal and N1 respectively；First stage pulls up the current potential of N1 and N2；Second stage pulls down the current potential of N2 and pulls up the current potential of N1 again, and control scanning output end exports effective impulse；Phase III, the current potential of N1 is pulled down, control scanning output end exports idler Pulse；Fourth stage, pulls down the current potential of N1, and control scanning output end keeps output idler Pulse.In the present invention, output abnormality phenomenon is improved.
Description
Technical field
The present embodiments relate to shift register technique more particularly to a kind of shift register circuit and its driving method with
And display device.
Background technique
Shift register is used for registered data, be also used to make under the action of clock signal data therein successively move to left or
It moves to right.
Existing shift register is applied in display panel, for driving the scan line of display panel.Each shift LD
Device has an input signal, and input signal includes at least a high level/low level, when input signal becomes high electricity by low level
Usually, the reset signal of shift register becomes low level by high level.After output signal becomes low level by high level,
The reset signal of shift register becomes high level by low level.
The driving method of shift register driving capability in the display panel of TED structure is insufficient, leads to output abnormality.
Summary of the invention
The embodiment of the present invention provides a kind of shift register circuit and its driving method and display device, different to solve output
Normal problem.
The embodiment of the invention provides a kind of shift register circuits, comprising: the shift register of multi-stage cascade；
The shift register includes: input module, pull-up module, pull-down module, output module and reseting module；
The input module is electrically connected with first node, second node and input terminal respectively, the pull-up module respectively with
First clock end and second node electrical connection, the pull-down module are electrically connected with second clock end and the second node respectively
It connects, the output module is electrically connected with the first node, the second node, the second clock end and scanning output end respectively
It connects, the reseting module is electrically connected with reset terminal and the first node respectively；
For shift register described in level-one, first stage, in the input module received signal and the upper drawing-die
The current potential at the first node and at the second node is pulled up under the control of block received signal；Second stage, described
The current potential at the second node is pulled down under the control of pull-down module received signal and pulls up the electricity at the first node again
Position, while controlling the scanning output end output effective impulse；Phase III, in the control of the pull-down module received signal
The current potential at the first node is pulled down, while controlling the scanning output end output idler Pulse；Fourth stage, described
The current potential at the first node is pulled down under the control of reseting module received signal to be resetted, while controlling the scanning
Output end keeps output idler Pulse.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display devices, including shift as described above
Register circuit.
Based on the same inventive concept, described the embodiment of the invention also provides a kind of driving method of shift register circuit
Shift register circuit includes the shift register of multi-stage cascade；The shift register includes: input module, pull-up module, under
Drawing-die block, output module and reseting module；The input module is electrically connected with first node, second node and input terminal respectively,
The pull-up module is electrically connected with the first clock end and the second node respectively, the pull-down module respectively with second clock end
With the second node be electrically connected, the output module respectively with the first node, the second node, the second clock
End and scanning output end electrical connection, the reseting module are electrically connected with reset terminal and the first node respectively；
The driving method include: for driving level-one described in shift register,
First stage pulls up under the control of the input module received signal and the pull-up module received signal
Current potential at the first node and at the second node；
Second stage pulls down the current potential at the second node and again under the control of the pull-down module received signal
The current potential at the first node is pulled up, while controlling the scanning output end output effective impulse；
Phase III pulls down the current potential at the first node, together under the control of the pull-down module received signal
When control scanning output end output idler Pulse；
Fourth stage, pulled down under the control of the reseting module received signal current potential at the first node with into
Row resets, while controlling the scanning output end and keeping output idler Pulse.
In the embodiment of the present invention, there is no interconnection between N1 node and N2 node, there is independent signal to supply, therefore N1
It will not generate and influence each other between node and N2 node, the current potential of N1 node and N2 node is controlled by each signal end respectively, no
Can be at floating state, so node potential drain conditions are not present, current potential has enough energy power drive output modules, will not
There is output abnormality problem, improves panel driving charging ability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to do one simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the schematic diagram of shift register circuit provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 3 is the schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 4 is the schematic diagram of the driver' s timing of shift register provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of the driver' s timing of shift register provided in an embodiment of the present invention；
Fig. 6 is the schematic diagram of the driver' s timing of shift register circuit provided in an embodiment of the present invention；
Fig. 7 is the schematic diagram of the driver' s timing of shift register circuit provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to attached in the embodiment of the present invention
Figure, clearly and completely describes technical solution of the present invention by embodiment, it is clear that described embodiment is the present invention one
Section Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
Refering to what is shown in Fig. 1, being the schematic diagram of shift register circuit provided in an embodiment of the present invention.In the present embodiment, displacement
Register circuit includes: the shift register 10 of multi-stage cascade.Optional shift register circuit is applied in display panel, as grid
Shift register circuit drives scan line, wherein the output end OUT of level-one shift register 10 and a scan line (not shown) electricity
Connection, and to scan line transmission scanning signal to drive the corresponding one-row pixels of the scan line.
In the shift register 10 of multi-stage cascade, the input terminal IN of chopped-off head shift register 10 directly receives driving chip
(not shown) transmission control signal STV and the work that is triggered under the control of control signal STV, when chopped-off head shift register
When 10 output end OUT1 exports effective impulse, a corresponding scan line drives corresponding a line picture under effective impulse signal control
Element is shown.The input terminal IN of second level shift register 10 is electrically connected with the output end OUT1 of upper level shift register 10
It connects, when the output end OUT1 of upper level shift register 10 exports effective impulse, second level shift register 10 is triggered work
Make；When the output end OUT3 of second level shift register 10 exports effective impulse, a corresponding scan line is believed in effective impulse
Number control is lower drives corresponding one-row pixels to be shown, while triggering the work of third level shift register 10.And so on, it is multistage
The cascade electrical connection of shift register 10 and successively time-sharing work.
It is appreciated that the odd-numbered line that grid shift register circuit can be used for driving in display panel as shown in Figure 1 scans
Line, then the first horizontal scanning line in the output end OUT1 electrical connection display panel of chopped-off head shift register 10, second level displacement are posted
The output end OUT3 of storage 10 is electrically connected third horizontal scanning line, the output end OUT5 electrical connection the 5th of third level shift register 10
The output end OUT7 of horizontal scanning line, fourth stage shift register 10 is electrically connected the 7th horizontal scanning line, and so on, multi-stage cascade
Shift register 10 drives each odd number horizontal scanning line 20 in display panel.
In other embodiments, also optional grid shift register circuit can be used for driving even number horizontal scanning line, then chopped-off head
The output end of shift register is electrically connected the second horizontal scanning line, the output end electrical connection fourth line scanning of second level shift register
The output end of line, third level shift register is electrically connected the 6th horizontal scanning line, and so on, the shift register of multi-stage cascade drives
Each even number horizontal scanning line in dynamic display panel.It should be noted that the mark serial number table of the output end OUT of every grade of shift register
Sign is that the line number of its scan line driven then can should if the output end of shift register is electrically connected the second horizontal scanning line
The output end of shift register is labeled as OUT2.
In other embodiments, also optional grid shift register circuit can be used for each row in sequence driving display panel
Scan line, then the output end of chopped-off head shift register is electrically connected the first horizontal scanning line, the output end electricity of second level shift register
The second horizontal scanning line is connected, the output end of third level shift register is electrically connected third horizontal scanning line, and so on, multi-stage cascade
Shift register driving display panel in each horizontal scanning line.
Refering to what is shown in Fig. 2, being the schematic diagram of shift register provided in an embodiment of the present invention.Displacement described in the present embodiment
Register is any level-one shift register in shift register circuit shown in Fig. 1, it should be noted that wherein chopped-off head shift LD
The input terminal of device is directly electrically connected with driving chip, and the output end of final stage shift register does not trigger next stage shift register.
Shift register includes: input module 1 in the present embodiment, pull-up module 2, pull-down module 3, output module 4 and multiple
Position module 5；Input module 1 is electrically connected with first node N1, second node N2 and input terminal IN respectively, pull-up module 2 respectively with
First clock end CKB and second node N2 electrical connection, pull-down module 3 are electrically connected with second clock end CK and second node N2 respectively
It connects, output module 4 is electrically connected with first node N1, second node N2, second clock end CK and scanning output end OUT respectively, multiple
Position module 5 is electrically connected with reset terminal CKR and first node N1 respectively；For level-one shift register, first stage, in input mould
The electricity at first node N1 and at second node N2 is pulled up under the control of 2 received signal of 1 received signal of block and pull-up module
Position；Second stage pulls down the current potential at second node N2 under the control of 3 received signal of pull-down module and pulls up first segment again
Current potential at point N1, while controlling scanning output end OUT output effective impulse；Phase III, in 3 received signal of pull-down module
Control under drop-down first node N1 place current potential, while control scanning output end OUT export idler Pulse；Fourth stage, In
The current potential at first node N1 is pulled down under the control of 5 received signal of reseting module to be resetted, while controlling scanning output
OUT is held to keep output idler Pulse.
In the present embodiment, input module 1 is electrically connected with first node N1, second node N2 and input terminal IN respectively, input
Module 1 is also electrically connected with the first power end VDD.Input terminal IN transmits input signal to input module 1 to control the first power end
Whether VDD is connected with the signal transmission path of first node N1 and second node N2.Specifically, the input letter of input terminal IN input
Number be effective impulse when, VDD is connected with the signal transmission path of first node N1, the first power end VDD pass through input module 1 give
First node N1 charging；Meanwhile VDD is connected with the signal transmission path of second node N2, the first power end VDD passes through input mould
Block 1 charges to second node N2.
In the present embodiment, pull-up module 2 is electrically connected with the first clock end CKB and second node N2 respectively, and pull-up module 2 is also
It is electrically connected with the first power end VDD.CKB pulls up module 2 and transmits first control signal to control the first power end VDD and second
Whether the signal transmission path conducting of node N2.Specifically, when the first control signal of CKB input is effective impulse, VDD and the
The signal transmission path of two node N2 is connected, and the first power end VDD is charged by pull-up module 2 to second node N2.
In the present embodiment, pull-down module 3 is electrically connected with second clock end CK and second node N2 respectively, pull-down module 3
One end is also grounded.CK pulls down module 3 and transmits second control signal to control the signal transmission path of second node N2 and the earth
Whether conducting.Specifically, the signal of second node N2 and the earth transmits road when the second control signal of CK input is effective impulse
Diameter conducting, second node N2 pass through the ground connection electric discharge of pull-down module 3.
In the present embodiment, output module 4 is defeated with first node N1, second node N2, second clock end CK and scanning respectively
Outlet OUT electrical connection.First node N1 control second clock end CK and scanning output end OUT signal transmission path conducting with
It is no.Specifically, when the control of Electric potentials output module 4 of first node N1 is connected, the letter of second clock end CK and scanning output end OUT
The conducting of number transmission path, scanning output end OUT output are pulse signal identical with second clock end CK.The one of output module 4
End is also grounded.Whether second node N2 control scanning output end OUT is connected with the signal transmission path of the earth.Specifically, second
When the control of Electric potentials output module 4 of node N2 is connected, scanning output end OUT is connected with the signal transmission path of the earth, scans defeated
Outlet OUT output is low level pulse signal identical with the earth.
In the present embodiment, reseting module 5 is electrically connected with reset terminal CKR and first node N1 respectively, one end of reseting module 5
Also it is grounded.CKR transmits reseting controling signal to reseting module 5 and is connected with controlling first node N1 with the signal transmission path of the earth
Whether.Specifically, when the reseting controling signal of CKR input is effective impulse, the signal transmission path of first node N1 and the earth
Conducting, first node N1 pass through the ground connection electric discharge of reseting module 5.
In the present embodiment, for level-one shift register, the course of work is divided into 4 working stages, successively includes the
One stage t1, second stage t2, phase III t3 and fourth stage t4.Combine herein Fig. 3 and shift register shown in Fig. 4 and
Its timing diagram is described.
First stage t1 pulls up first under the control of 2 received signal of 1 received signal of input module and pull-up module
Current potential at node N1 and at second node N2.1 received signal of input module is the input signal of input terminal IN transmission, on
2 received signal of drawing-die block is the first control signal of the first clock end CKB transmission.The signal of IN becomes high electricity from low level
Flat, the signal of CKB becomes high level from low level, then input module 1 and pull-up module 2 simultaneously turn on, and VDD can pass through input
Module 1 charges to N1 and N2 respectively, meanwhile, VDD is charged by pull-up module 2 to N2.Therefore the current potential of N2 is become from low level
The current potential of high level, N1 is raised into high level.
Second stage t2, under the control of 3 received signal of pull-down module pull down second node N2 at current potential and again on
The current potential at first node N1 is drawn, while controlling scanning output end OUT output effective impulse.3 received signal of pull-down module
For the second control signal of second clock end CK transmission.The signal of IN becomes low level from high level, and the signal of CKB is by high level
Become low level, then input module 1 and pull-up module 2 are ended simultaneously；The signal of CK becomes high level from low level, then descends drawing-die
Block 3 is connected, and N2 is discharged and is pulled low as low level by pull-down module 3；Meanwhile N1 can be filled by the capacitor in output module 4
Electricity is to more high potential, then output module 4 is connected, and the transmission path conducting of second clock end CK and scanning output end OUT scan defeated
Outlet OUT exports high level signal identical with CK.It is high level signal in the effective impulse of this OUT terminal output.
Phase III t3 pulls down the current potential at first node N1, same time control under the control of 3 received signal of pull-down module
Scanning output end OUT processed exports idler Pulse.3 received signal of pull-down module is the second control of second clock end CK transmission
Signal.Input module 1 and pull-up module 2 keep cut-off；The signal of CK becomes low level from high level, then pull-down module 3 is ended,
Scanning output end OUT exports low level signal identical with CK simultaneously；N1 is returned to high level by the capacitor in output module 4.
It is low level signal in the idler Pulse of this OUT terminal output.
Fourth stage t4 pulls down the current potential at first node N1 under the control of 5 received signal of reseting module to carry out
It resets, while controlling scanning output end OUT and keeping output idler Pulse.4 received signal of reseting module is reset terminal CKR biography
Defeated reseting controling signal.CKR becomes high level from low level, then reseting module 5 is connected so that the signal of N1 and the earth transmits
Path conducting, the current potential of N1 node are pulled down to low level, and OUT terminal maintains output idler Pulse, that is, low level signal.
In the present embodiment, when the signal at the end IN becomes high level from low level, the current potential of N2 node becomes high level；In
When the signal at the end IN becomes low level from high level, the current potential of N2 node becomes low level.Obviously, the current potential of N2 node always with
The variation of IN, CKB and CK signal and change, do not influenced by panel load size, also be not present delay phenomenon, node potential
It can keep and leakproof.When signal at the end IN becomes high level from low level, the current potential of N1 node becomes high level；In IN
After the signal at end becomes low level from high level, the signal at the end CK becomes high level from low level, at this time the current potential quilt of N1 node
It is pulled to more high level；When signal at the end CK becomes low level from high level, the current potential of N1 node is pulled down to high level, and ties up
Hold high potential；Fourth stage, that is, reseting stage, the current potential of the N1 node module 5 that is reset are pulled down to low level.Obviously, N1 node
Current potential changes with the variation of IN and CKR signal always, is not influenced by panel load size, and delay phenomenon is also not present,
Node potential can be kept and leakproof.
In the present embodiment, there is no interconnection between N1 node and N2 node, there is independent signal to supply, therefore N1 node
It will not generate and influence each other between N2 node, the current potential of N1 node and N2 node is controlled by each signal end respectively, will not be located
In floating state, so node potential drain conditions are not present, current potential has enough energy power drive output modules, is not in
Output abnormality problem improves panel driving charging ability.
Illustratively, based on the above technical solution, optional input module 1 includes the first transistor as shown in Figure 3
T1 and the 7th transistor T7；The control terminal of the first transistor T1 and the 7th transistor T1 are electrically connected with input terminal IN, and first is brilliant
The input terminal of body pipe T1 and the 7th transistor T7 are electrically connected with power end VDD, the output end and first segment of the first transistor T1
Point N1 electrical connection, the output end of the 7th transistor T7 are electrically connected with second node N2.Optional T1 and T7 is NMOS.
The signal of first stage, IN become high level from low level, then T7 is connected so that power end VDD and second node N2
Signal transmission path conducting, while T1 conducting so that power end VDD is connected with the signal transmission path of first node N1.Then
VDD is charged by T1 to N1 node and VDD is charged by T7 to N2 node.
Second stage and later, the signal of IN becomes low level from high level, then T7 and T1 end simultaneously.VDD and N1 is saved
The signal transmission path of point and N2 node is each turned off.
Optional pull-up module 2 as shown in Figure 3 includes the 6th transistor T6, the second capacitor C2 and third capacitor C3；6th is brilliant
The control terminal of body pipe T6 is electrically connected with the first clock end CKB, and the input terminal of the 6th transistor T6 is electrically connected with power end VDD, the
The output end of six transistor T6 is electrically connected with second node N2, the first end of the second capacitor C2 and the input terminal of the 6th transistor T6
Electrical connection, the second end ground connection of the second capacitor C2, the first end of third capacitor C3 are electrically connected with the output end of the 6th transistor T6,
The second end of third capacitor C3 is grounded.Optional T6 is NMOS.
The signal of first stage, CKB become high level from low level, then T6 conducting is so that power end VDD and second node
The signal transmission path of N2 is connected.Then VDD charges to capacitor C2, also gives capacitor C3 and node N2 to charge respectively by T6.
Second stage and later, the signal of CKB becomes low level from high level, then T6 ends so that power end VDD and the
The signal transmission path of two node N2 disconnects.
Optional pull-down module 3 as shown in Figure 3 includes the 5th transistor T5；The control terminal and second clock of 5th transistor T5
CK electrical connection is held, the input terminal of the 5th transistor T5 is electrically connected with second node N2, the output end ground connection of the 5th transistor T5.It can
Selecting T5 is NMOS.
The signal of second stage, CK becomes high level from low level, then the letter so that the earth and second node N2 is connected in T5
The conducting of number transmission path.Then second node N2 is discharged by T5.
Phase III and later, the signal of CK becomes low level from high level, then T5 ends so that the earth and second node
The signal transmission path of N2 disconnects.
Optional output module 4 as shown in Figure 3 includes second transistor T2, third transistor T3 and first capacitor C1；Second
The control terminal of transistor T2 is electrically connected with first node N1, and the input terminal of second transistor T2 is electrically connected with second clock end CK,
The output end of second transistor T2 is electrically connected with scanning output end OUT, and first end and the first node N1 of first capacitor C1 is electrically connected
It connects, the second end of first capacitor C1 is electrically connected with scanning output end OUT, control terminal and second node the N2 electricity of third transistor T3
Connection, the input terminal of third transistor T3 are electrically connected with scanning output end OUT, the output end ground connection of third transistor T3.It is optional
T2 and T3 is NMOS.
First stage, first node N1 and second node N2 are high level, CK be low level, then T2 and T3 be connected so that
The signal transmission path of CK, scanning output end OUT and the earth are connected.Then scanning output end OUT exports low level signal.
Second stage, first node N1 be high level, second node N2 be low level, CK is high level, then T2 conducting and
T3 cut-off, then CK is connected with the signal transmission path of scanning output end OUT.Then scanning output end OUT exports height identical with CK
Level signal.
Phase III, first node N1 are high level, and second node N2 maintains low level, and CK is low level, then T2 is connected
And T3 keeps cut-off, then scanning output end OUT exports low level signal identical with CK.
Fourth stage, first node N1 are low level, and second node N2 maintains low level, then sweeps under the stabilization of capacitor C1
It retouches output end OUT and persistently exports low level signal.
Optional reseting module 5 as shown in Figure 3 includes the 4th transistor T4；The control terminal and reset terminal of 4th transistor T4
CKR electrical connection, the input terminal of the 4th transistor T4 are electrically connected with first node N1, the output end ground connection of the 4th transistor T4.T4
For NMOS.
Fourth stage, CKR become high level from low level, then T4 is connected so that the signal of first node N1 and the earth transmits
Path conducting.Then N1 node is pulled down to low level.
The circuit structure of input module 1 as shown in connection with fig. 3, pull-up module 2 and pull-down module 3 it is found that
The signal of first stage, IN become high level from low level, and the signal of CKB becomes high level from low level, then T1,
T6 and T7 are simultaneously turned on, and VDD makes capacitor C1 store charge by T1 to the charging of N1 node, and VDD is filled by T6 and T7 to N2 node
Electricity makes capacitor C3 store charge, and VDD returns capacitor C2 charging.Therefore capacitor C1, C2 and C3 store charge, N1 and N2 be raised for
High level.
The signal of second stage, IN becomes low level from high level, and the signal of CKB becomes low level from high level, CK's
Signal becomes high level from low level, then T1, T6 and T7 end simultaneously, and T5 conducting, capacitor C1 is stored with charge so that first segment
Point N1 is pulled to more high potential, and capacitor C3 is discharged by second node N2 and T5, then it is low that capacitor C3 electric discharge, which is pulled low N2,
Level, T3 cut-off.Meanwhile first node N1 is that T2 is connected in high level, then scanning output end OUT output is identical with CK high electric
Ordinary mail number.N2 is that low level ends T3, and the signal that charge and CK are stored in capacitor C1 is high level, so that first
Node N1 will not leak electricity, while the current potential of first node N1 is impacted by CK signal to more high potential, ensure that scanning output end
Current potential.
The signal of phase III, CK become low level from high level, then T5 ends, and the other end ground connection of capacitor C3 makes second
Node N2 is maintained at low level, and first node N1 is pulled down to high level and is kept under the stabilization of capacitor C1.Meanwhile first node
N1 is that high level is held on T2, then scanning output end OUT exports low level signal identical with CK, and stablizing for CK signal is defeated
It ensure that the current potential of scanning output end OUT out.
The signal of fourth stage, CKR becomes high level from low level, then T4 is connected, and the charge of capacitor C1 passes through first segment
Point N1 and discharge, then first node N1 becomes low level from high level.N1 and N2 is the cut-off of low level, then T2 and T3, scanning
Output end persistently exports low level signal under the stabilization of capacitor C1.
It is optional for level-one shift register as shown in Figure 5 further include: between first stage t1 and second stage t2
The first sub-stage t1', the first sub-stage t1', in the control of input module received signal and pull-up module received signal
The lower current potential maintained at first node and at second node.Its timing according to Fig. 3 and Fig. 5 are as follows:
T1 stage, input signal (IN) become high level from low level, and CKB is drawn high simultaneously, and node N2 is become from low level
High level, N1 are raised into high level simultaneously；T1' stage, IN&CKB pull into low level simultaneously, and N2 maintains high level constant, N1
Also maintain high level constant；T2 stage, IN&CKB maintain low level, and CK is drawn as high level, and N2 is pulled low into low level, N1 meeting
It is pulled to more high potential, while OUT exports high level；T3 stage, CK are pulled to low level by high level, and OUT exports low level,
N1 is drawn back into high level；T4 stage, CKR become high level from low level, and N1 is drawn back into low level, and OUT maintains low level
It is constant.
Optional shift register circuit as shown in Figure 1 further include: the 1st clock cable CKV1, the 1st clock cable CKV1 with
The first clock end CKB electrical connection of 4m+1 grades of shift registers 10, also the reset terminal CKR electricity with 4m+3 grades of shift registers
Connection, is also electrically connected with the second clock end CK of 4m+4 grades of shift registers；2nd clock cable CKV2, the 2nd clock signal
Line CKV2 is electrically connected with the first clock end CKB of 4m+2 grades of shift registers, the also reset with 4m+4 grades of shift registers
CKR electrical connection is held, is also electrically connected with the second clock end CK of 4m+1 grades of shift registers；3rd clock cable CKV3, the 3rd
Clock cable CKV3 is electrically connected with the first clock end CKB of 4m+3 grades of shift registers, also with 4m+1 grades of shift LDs
The reset terminal CKR of device is electrically connected, and is also electrically connected with the second clock end CK of 4m+2 grades of shift registers；4th clock cable
CKV4, the 4th clock cable CKV4 are electrically connected with the first clock end CKB of 4m+4 grades of shift registers, also with 4m+2 grades
The reset terminal CKR of shift register is electrically connected, and is also electrically connected with the second clock end CK of 4m+3 grades of shift registers；Wherein, m
For integer and m is more than or equal to 0；1st clock cable CKV1, the 2nd clock cable CKV2, the 3rd clock cable CKV3 and the 4th
The output effective impulse of clock cable CKV4 periodicity and timesharing.
In the present embodiment, the 1st clock cable CKV1 respectively with the first clock end CKB of chopped-off head shift register 10, the 5th
The CKB of grade shift register, the 9th grade of shift register CKB ..., the first clock end CKB of 4m+1 grade shift registers it is electric
Connection.1st clock cable CKV1 also respectively with the reset terminal CKR of 3rd level shift register 10, the 7th grade of shift register
CKR, the 11st grade of shift register CKR ..., the reset terminal CKR electrical connections of 4m+3 grades of shift registers.1st clock signal
Line CKV1 also respectively with the second clock end CK of the 4th grade of shift register 10, the CK of the 8th grade of shift register, the 12nd grade of displacement
The CK of register ..., the second clock end CK electrical connections of 4m+4 grades of shift registers.
2nd clock cable CKV2 respectively with the first clock end CKB of the 2nd grade of shift register 10, the 6th grade of shift LD
The CKB of device, the 10th grade of shift register CKB ..., the first clock end CKB electrical connections of 4m+2 grades of shift registers.2nd
Clock cable CKV2 also respectively with the reset terminal CKR of the 4th grade of shift register 10, the CKR of the 8th grade of shift register, the 12nd
The CKR of grade shift register ..., the reset terminal CKR of 4m+4 grade shift registers is electrically connected.2nd clock cable CKV2 is also
Respectively with the second clock end CK of chopped-off head shift register 10, the CK of the 5th grade of shift register, the 9th grade of shift register
CK ..., the second clock end CK electrical connections of 4m+1 grades of shift registers.
3rd clock cable CKV3 respectively with the first clock end CKB of 3rd level shift register 10, the 7th grade of shift LD
The CKB of device, the 11st grade of shift register CKB ..., the first clock end CKB electrical connections of 4m+3 grades of shift registers.3rd
Clock cable CKV3 also respectively with the reset terminal CKR of chopped-off head shift register 10, the CKR of the 5th grade of shift register, the 9th grade
The CKR of shift register ..., the reset terminal CKR electrical connections of 4m+1 grades of shift registers.3rd clock cable CKV3 also divides
Not with the second clock end CK of the 2nd grade of shift register 10, the CK of the 6th grade of shift register, the 10th grade of shift register
CK ..., the second clock end CK electrical connections of 4m+2 grades of shift registers.
4th clock cable CKV4 respectively with the first clock end CKB of the 4th grade of shift register 10, the 8th grade of shift LD
The CKB of device, the 12nd grade of shift register CKB ..., the first clock end CKB electrical connections of 4m+4 grades of shift registers.4th
Clock cable CKV4 also respectively with the reset terminal CKR of the 2nd grade of shift register 10, the CKR of the 6th grade of shift register, the 10th
The CKR of grade shift register ..., the reset terminal CKR of 4m+2 grade shift registers is electrically connected.4th clock cable CKV4 is also
Respectively with the second clock end CK of 3rd level shift register 10, the CK of the 7th grade of shift register, the 11st grade of shift register
CK ..., the second clock end CK electrical connections of 4m+3 grades of shift registers.
It is illustrated in figure 6 the timing diagram of the 1st~the 4th clock cable.The effective impulse of optional CKV1~CKV4 is height
Level signal.CKV1~CKV4 is sequentially output effective impulse.Fig. 6 show shift register circuit driving odd number horizontal scanning line when
Sequence figure.Wherein, VSR1 is chopped-off head shift register, and VSR2 is the 2nd grade of shift register, and so on.The received STV letter of VSR1
Number be IN signal.The timing control process of every grade of shift register is as described above, details are not described herein.
In the present embodiment, when the signal at the end IN becomes high level from low level, the current potential of N2 node becomes high level；In
When the signal at the end IN becomes low level from high level, the current potential of N2 node becomes low level.It is not deposited between N1 node and N2 node
It is interconnecting, is thering is independent signal to supply, therefore will not generate and influence each other between N1 node and N2 node, N1 node and N2 section
The current potential of point is controlled by each signal end respectively, is not at floating state, so node potential drain conditions are not present, electricity
There are enough energy power drive output modules in position, is not in output abnormality problem, improves panel driving charging ability.
Optionally, the shift register of multi-stage cascade is correspondingly arranged with multi-strip scanning line, the scanning output of shift register
End is electrically connected with corresponding scan line.In the present embodiment, shift register circuit is for sequentially driving the multi-strip scanning of display panel
Line.Then chopped-off head shift register drives the first horizontal scanning line, and the 2nd grade of shift register drives the second horizontal scanning line, and so on.
It is illustrated in figure 7 the driver' s timing figure of shift register circuit.The effective impulse of optional CKV1~CKV4 is high level signal.
CKV1~CKV4 is sequentially output effective impulse.As shown in fig. 7, shift register circuit successively drives fine scanning line.Every grade of displacement
The timing control process of register is as described above, details are not described herein.
Optionally, the shift register of multi-stage cascade is electrically connected with multi-strip scanning line, and multi-strip scanning line is driving odd number
Row and the scan line of sequence arrangement.Wherein, the first sub-stage multiplexing of the level-one shift register of an odd number horizontal scanning line is driven
For the first stage of the level-one shift register of the next even number horizontal scanning line of driving.Its driver' s timing is refering to what is shown in Fig. 6, herein not
It repeats again.The shift register of also optional multi-stage cascade is electrically connected with multi-strip scanning line in other embodiments, multi-strip scanning line
It is the scan line for driving even number line and sequence arrangement.The timing control process of every grade of shift register is as described above, herein not
It repeats again.
Interconnection is not present in shift register circuit provided in this embodiment between the N1 node and N2 node of shift register,
There is independent signal to supply, therefore will not generate and influence each other between N1 node and N2 node, the electricity of N1 node and N2 node
Position is controlled by each signal end respectively, is not at floating state, so node potential drain conditions are not present, current potential has foot
Enough energy power drive output modules, are not in output abnormality problem, improve panel driving charging ability.
Based on the same inventive concept, the embodiment of the present invention also provides a kind of display device, including any embodiment as above institute
The shift register circuit stated.Optional display device is organic light-emitting display device.
The shift register circuit of the display device includes the shift register of multi-stage cascade；Shift register includes: input
Module, pull-up module, pull-down module, output module and reseting module；Input module respectively with first node, second node and defeated
Enter end electrical connection, pull-up module is electrically connected with the first clock end and second node respectively, pull-down module respectively with second clock end
It is electrically connected with second node, output module is electrically connected with first node, second node, second clock end and scanning output end respectively
It connects, reseting module is electrically connected with reset terminal and first node respectively.
The driving method of the shift register circuit of the display device include: for drive level-one shift register,
First stage pulls up first node under the control of input module received signal and pull-up module received signal
Current potential at place and second node；
Second stage pulls down the current potential at second node under the control of pull-down module received signal and pulls up first again
Current potential at node, while controlling scanning output end output effective impulse；
Phase III pulls down the current potential at first node under the control of pull-down module received signal, while control is swept
Retouch output end output idler Pulse；
Fourth stage, under the control of reseting module received signal pull down first node at current potential to be resetted,
Scanning output end is controlled simultaneously keeps output idler Pulse.
Optionally for level-one shift register, further includes:
The first sub-stage between first stage and second stage, the first sub-stage, in the received letter of input module
Number and pull-up module received signal control under maintain first node at and second node at current potential.
In the present embodiment, for level-one shift register, the course of work is divided into 4 working stages, successively includes the
One stage t1, second stage t2, phase III t3 and fourth stage t4.It can refer to figure 3 above and shift register shown in Fig. 4
And its description of sequential organization, this is no longer going to repeat them.
In the present embodiment, the shift register circuit of display device, wherein interconnection is not present between N1 node and N2 node,
There is independent signal to supply, therefore will not generate and influence each other between N1 node and N2 node, the electricity of N1 node and N2 node
Position is controlled by each signal end respectively, is not at floating state, so node potential drain conditions are not present, current potential has foot
Enough energy power drive output modules, are not in output abnormality problem, improve panel driving charging ability.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts, be combined with each other and substitutes without departing from protection scope of the present invention.Therefore, although by above embodiments to this
Invention is described in further detail, but the present invention is not limited to the above embodiments only, is not departing from present inventive concept
In the case of, it can also include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (14)
1. a kind of shift register circuit characterized by comprising the shift register of multi-stage cascade；
The shift register includes: input module, pull-up module, pull-down module, output module and reseting module；
The input module is electrically connected with first node, second node and input terminal respectively, and the pull-up module is respectively with first
Clock end and second node electrical connection, the pull-down module are electrically connected with second clock end and the second node respectively,
The output module is electrically connected with the first node, the second node, the second clock end and scanning output end respectively,
The reseting module is electrically connected with reset terminal and the first node respectively；
For shift register described in level-one, first stage, in the input module received signal and pull-up module institute
Receive the current potential pulled up at the first node and at the second node under the control of signal；Second stage, in the drop-down
The current potential at the second node is pulled down under the control of module received signal and pulls up the current potential at the first node again, together
When control scanning output end output effective impulse；Phase III, under the control of the pull-down module received signal under
The current potential at the first node is drawn, while controlling the scanning output end output idler Pulse；Fourth stage, in the reset
The current potential at the first node is pulled down under the control of module received signal to be resetted, while controlling the scanning output
End keeps output idler Pulse.
2. shift register circuit according to claim 1, which is characterized in that the input module include the first transistor and
7th transistor；
The control terminal of the first transistor and the 7th transistor is electrically connected with the input terminal, the first transistor
It is electrically connected with power end with the input terminal of the 7th transistor, the output end of the first transistor and the first node
Electrical connection, the output end of the 7th transistor are electrically connected with the second node.
3. shift register circuit according to claim 1, which is characterized in that the pull-up module include the 6th transistor,
Second capacitor and third capacitor；
The control terminal of 6th transistor is electrically connected with first clock end, the input terminal and power supply of the 6th transistor
End electrical connection, the output end of the 6th transistor are electrically connected with the second node, the first end of second capacitor and institute
State the input terminal electrical connection of the 6th transistor, the second end ground connection of second capacitor, the first end of the third capacitor and institute
State the output end electrical connection of the 6th transistor, the second end ground connection of the third capacitor.
4. shift register circuit according to claim 1, which is characterized in that the pull-down module includes the 5th transistor；
The control terminal of 5th transistor is electrically connected with the second clock end, the input terminal and described second of the 5th transistor
Node electrical connection, the output end ground connection of the 5th transistor.
5. shift register circuit according to claim 1, which is characterized in that the output module include second transistor,
Third transistor and first capacitor；
The control terminal of the second transistor is electrically connected with the first node, the input terminal of the second transistor and described the
The electrical connection of two clock ends, the output end of the second transistor is electrically connected with the scanning output end, and the of the first capacitor
One end is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the scanning output end, the third
The control terminal of transistor is electrically connected with the second node, and the input terminal of the third transistor is electrically connected with the scanning output end
It connects, the output end ground connection of the third transistor.
6. shift register circuit according to claim 1, which is characterized in that the reseting module includes the 4th transistor；
The control terminal of 4th transistor is electrically connected with the reset terminal, the input terminal and the first node of the 4th transistor
Electrical connection, the output end ground connection of the 4th transistor.
7. according to the described in any item shift register circuits of claim 2-6, which is characterized in that the transistor is NMOS.
8. shift register circuit according to claim 1, which is characterized in that further include:
First clock end of 1st clock cable, the 1st clock cable and 4m+1 grades of shift registers is electrically connected
It connects, is also electrically connected with the reset terminal of 4m+3 grades of shift registers, also described second with 4m+4 grades of shift registers
Clock end electrical connection；
First clock end of 2nd clock cable, the 2nd clock cable and 4m+2 grades of shift registers is electrically connected
It connects, is also electrically connected with the reset terminal of 4m+4 grades of shift registers, also described second with 4m+1 grades of shift registers
Clock end electrical connection；
First clock end of 3rd clock cable, the 3rd clock cable and 4m+3 grades of shift registers is electrically connected
It connects, is also electrically connected with the reset terminal of 4m+1 grades of shift registers, also described second with 4m+2 grades of shift registers
Clock end electrical connection；
First clock end of 4th clock cable, the 4th clock cable and 4m+4 grades of shift registers is electrically connected
It connects, is also electrically connected with the reset terminal of 4m+2 grades of shift registers, also described second with 4m+3 grades of shift registers
Clock end electrical connection；
Wherein, m is integer and m is more than or equal to 0；
1st clock cable, the 2nd clock cable, the 3rd clock cable and the 4th clock cable
The output effective impulse of periodicity and timesharing.
9. shift register circuit according to claim 8, which is characterized in that the shift register of multi-stage cascade is swept with a plurality of
It retouches line to be correspondingly arranged, the scanning output end of the shift register is electrically connected with the corresponding scan line.
10. shift register circuit according to claim 1, which is characterized in that for shift register described in level-one, also wrap
It includes:
The first sub-stage between the first stage and the second stage, first sub-stage, in the input
It is maintained under the control of module received signal and the pull-up module received signal at the first node and second section
Current potential at point.
11. shift register circuit according to claim 10, which is characterized in that the shift register of multi-stage cascade with it is a plurality of
Scan line electrical connection, the multi-strip scanning line is to drive the scan line of odd-numbered line and sequence arrangement, alternatively, the multi-strip scanning
Line is the scan line for driving even number line and sequence arrangement；
The first sub-stage of the level-one shift register of an odd number horizontal scanning line is driven to be multiplexed with the next even number horizontal scanning line of driving
Level-one shift register first stage.
12. a kind of display device, which is characterized in that including such as described in any item shift register circuits of claim 1-11.
13. a kind of driving method of shift register circuit, which is characterized in that the shift register circuit includes the shifting of multi-stage cascade
Bit register；The shift register includes: input module, pull-up module, pull-down module, output module and reseting module；Institute
Input module is stated to be electrically connected with first node, second node and input terminal respectively, the pull-up module respectively with the first clock end
It is electrically connected with the second node, the pull-down module is electrically connected with second clock end and the second node respectively, described defeated
Module is electrically connected with the first node, the second node, the second clock end and scanning output end respectively out, described multiple
Position module is electrically connected with reset terminal and the first node respectively；
The driving method include: for driving level-one described in shift register,
First stage, under the control of the input module received signal and the pull-up module received signal described in pull-up
Current potential at first node and at the second node；
Second stage pulls down the current potential at the second node under the control of the pull-down module received signal and pulls up again
Current potential at the first node, while controlling the scanning output end output effective impulse；
Phase III pulls down the current potential at the first node, same time control under the control of the pull-down module received signal
Make the scanning output end output idler Pulse；
Fourth stage pulls down the current potential at the first node under the control of the reseting module received signal to be answered
Position, while controlling the scanning output end and keeping output idler Pulse.
14. driving method according to claim 13, which is characterized in that for shift register described in level-one, further includes:
The first sub-stage between the first stage and the second stage, first sub-stage, in the input
It is maintained under the control of module received signal and the pull-up module received signal at the first node and second section
Current potential at point.
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| CN110619858A (en) * | 2019-10-29 | 2019-12-27 | 上海中航光电子有限公司 | Shift register, grid drive circuit and display panel |
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