CN110427223A - A kind of method and system based on host computer PC IE bus dynamically load multi-core DSP - Google Patents
A kind of method and system based on host computer PC IE bus dynamically load multi-core DSP Download PDFInfo
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- CN110427223A CN110427223A CN201910587781.1A CN201910587781A CN110427223A CN 110427223 A CN110427223 A CN 110427223A CN 201910587781 A CN201910587781 A CN 201910587781A CN 110427223 A CN110427223 A CN 110427223A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
Disclose a kind of method based on host computer PC IE bus dynamically load multi-core DSP, which comprises make multi-core DSP and host computer communication connection；By program transportation to the multi-core DSP；PCIE MSI interrupt is triggered, so that the multi-core DSP runs described program；Wherein, the multi-core DSP receives data from the host computer by PCIE dma mode, and the operation result for running described program is returned to the host computer.According to the method for the present invention with system cost is smaller, power consumption is lower, and system bulk is small easy to carry, can be detached from outfield and quickly carry out related commissioning；It is flexible in application due to that can realize that the quick load of program starts in the case where system is not restarted, save debug time；And system data transmission efficiency is higher, and due to using PCIE2.0 agreement, actual transmissions efficiency is much higher than common gigabit network interface.
Description
Technical field
The invention belongs to fields of communication technology, and in particular to one kind is based on host computer PC IE bus dynamically load multi-core DSP
Method and system.
Background technique
To complete the implementation means that radar digital signal detection is taken with information extraction function.The reflection echo of object is
Faint high-frequency signal (connects by the analog signal that the processing such as frequency conversion, amplification and filtering become to have some strength on the time
It is continuous, can be any real number value in amplitude).Digital processing must use analogue-to-digital converters, and analog signal is converted into number
Signal (discrete on the time, amplitude higher slice), then carries out various operations and processing.
In face of the military requirement background of radar and the fast development of signal processing support technology, in order to accelerate radar system
Development progress, shorten the development cycle of radar system, need that quickly new Radar Signal Processing algorithm is developed and tested
Card.The verifying of new algorithm carries out generally in field trial at present, for external field of radar test to organize and coordinate difficulty big, largely
Human and material resources and the status that is consumed of time, face a need and urgently solve the problems, such as, that is, ensure that system operates normally
In the case where how by high efficiency, low cost in a manner of verify Radar Signal Processing new algorithm.
Effective design process is to obtain a large amount of target measured datas by data apparatus for acquiring and storing first, then sharp
Off-line verification new algorithm performance with the following methods: the data of storage are exported into progress data simulation analysis in computer, and will
Measured data imports half physical varification that DSP equipment carries out new algorithm from computer.And how will largely be surveyed on computer
It is the technological difficulties for needing to solve that data, which quickly import equipment,.
Summary of the invention
It is an object of the present invention to provide one kind measured data a large amount of on computer quickly can be imported equipment
Method and system.
According to an aspect of the invention, there is provided a kind of side based on host computer PC IE bus dynamically load multi-core DSP
Method, which comprises
Make multi-core DSP and host computer communication connection；By program transportation to the multi-core DSP；And in triggering PCIE MSI
It is disconnected, so that the multi-core DSP runs described program；Wherein, the multi-core DSP passes through PCIE dma mode from the host computer
Data are received, and the operation result for running described program is returned into the host computer.
According to one embodiment, the multi-core DSP is via PCIE interchanger and the host computer communication connection or described
Multi-core DSP is via PCIE golden finger and host computer communication connection.
According to one embodiment, the multi-core DSP is C6678 board.
According to one embodiment, described program is transmitted to each core of the multi-core DSP by the host computer.
According to one embodiment, a core of the multi-core DSP jumps to automatically after receiving the PCIE MSI interrupt
Program operation address simultaneously starts, and after the core is triggered, the IPC of other cores is interrupted.
According to one embodiment, this method further include: the host computer enumerates the multi-core DSP and is the multi-core DSP
Resource is distributed, the mapping of PCIE bus address is carried out.
The multicore is reinitialized if the host computer enumerates the multi-core DSP failure according to one embodiment
DSP。
According to one embodiment, program is reloaded if necessary, then DSP is by warm reset, and the host computer is by journey
Sequence is re-loaded to most multi-core DSPs.
Basic another aspect of the present invention provides a kind of based on host computer PC IE bus dynamically load multi-core DSP
System, comprising: multi-core DSP is configured as carrying out operation to data are imported according to program, and returns the result；And host computer, quilt
It is configured to enumerate and start the multi-core DSP, the multi-core DSP is imported data to by PCIE interface, wherein the host computer
By PCIE dma mode to importing data to the multi-core DSP, and the operation result of described program will be run back to described
Host computer.
Host computer enumerates board by PCIE bus in the present invention, and DSP startup program is passed by this interface
It is defeated by DSP and triggers its starting, host computer passes through this interface again and imports data to DSP, convenient to carry out related operation by it.The party
Method supports to carry out repeating load to equipment when host computer is not restarted and data are transmitted.
The advantage of the system according to the present invention is mainly reflected in:
1) cost is smaller, power consumption is lower, and system bulk is small easy to carry, can be detached from outfield and quickly carry out related commissioning；
2) flexible in application due to that can realize that the quick load of program starts in the case where system is not restarted, it saves
Debug time；
3) system data transmission efficiency is higher, and due to using PCIE2.0 agreement, actual transmissions efficiency is much higher than common thousand
Million network interfaces.
With reference to attached drawing, according to the description of exemplary embodiment, other features of the invention be will be apparent below.
Detailed description of the invention
The structure chart of Fig. 1 system thus；
Fig. 2 is the method PCIE dynamically load flow chart；And
Fig. 3 is working-flow figure.
Specific embodiment
Hereinafter, being described with reference to the drawings according to an embodiment of the invention, it is understood that description below is only example
Property, and not to limit the invention to following embodiment.
Method and apparatus according to the invention are vulnerable to perhaps diverse influence, the brief description in order to clear, method and
Many descriptions of equipment are simplified.Many structures and term for describing to have used specific criteria.However, disclosed method and
Equipment can be applied even more extensively.
It will be apparent to one skilled in the art that the various illustrative logics in conjunction with described in disclosed embodiments
Frame, module, unit and algorithm steps can be often implemented as the combination of electronic hardware, computer software or both.In order to clear
This interchangeability for showing to Chu hardware and software, below for various illustrative components, frame, module and step with regard to its function
Whole description is carried out.Such function is implemented as hardware or software, depending on being applied to system on the whole specific
Constraint.Technical staff can implement described function, but such reality for each specific system in different ways
The mode decision of applying should not be interpreted as causing a departure from the scope of the present invention.In addition, unit, module, the grouping of the function of frame or step
It is simple in order to describe.Specific function or step from unit, a module or can frame shift out, without departing from the present invention.
Disclosed embodiment is described below in offer, so that any person skilled in the art can complete or make
With the present invention.The various modifications of these embodiments will be apparent for those skilled in the art, and described herein
General Principle can be applied to other embodiments, without departing from the spirit or scope of the present invention.Therefore, this technology is not limited to
Specific example discussed below.Thus, it will be appreciated that the description and the appended drawings provided herein represent the currently preferred reality of the present invention
Mode is applied, and therefore represents the theme widely conceived by the present invention.Further, it should be understood that the scope of the present invention is fully
It may be obvious embodiment comprising other couples of those skilled in the art, and therefore, the scope of the present invention is only by appended
Claim limitation.
To solve the problems, such as that outfield measured data quickly introduces DSP, the present invention provides a kind of based on host computer PC IE bus
The method and system of dynamically load multi-core DSP.Specifically, the concrete measure taken according to the method for the present invention is as follows:
1) after system electrification, board carries out initialization and PCIE link training.
2) host computer is enumerated board and resource allocation.
3) program is transmitted to DSP by PCIE interface and triggers its operation by host computer.
4) data are transmitted to DSP by PCIE dma mode by host computer.
5) result is returned into host computer after DSP is calculated.
6) host computer reloads board program, repeats 3~5 process.
Specific embodiments of the present invention will be described in detail with reference to the accompanying drawing.
As shown in Figure 1, being the system construction drawing of the method, it can be seen that system is mainly by PC host and C6678 board group
At being connected between the two by PCIE interchanger.C6678 board is directly inserted into PC host by PCIE golden finger, with PC
Machine is interconnected.Although in the present example embodiment, describing DSP equipment by taking C6678 board as an example, the present invention is unlimited
In this, and DSP equipment can be other kinds of apply for card.
In the present invention, using PC host computer dynamically load using C6678 as the dsp board card of core, and measured data is fast
Speed imports and wherein carries out corresponding operation, has preferable flexibility and reliability.C6678 board is 8 nuclear plate cards.The core of board
Number is not limited to 8, and can be any other suitable quantity.
In the present example embodiment, PC machine is responsible for enumerating and starting dsp board card, and is imported data to by PCIE interface
DSP.DSP is responsible for carrying out related operation to importing data, and result is returned to PC host computer.Herein, term " enumerating " has
There is the meaning of identification, mark.That is, PC machine identifies dsp board card, and identify each core of dsp board card.
Next, describing the PCIE dynamically load process of DSP with reference to Fig. 2.
After PC machine enumerates the DSP that initialization is completed, DSP startup program is converted to program load table by certain format,
It is put into the specific position of such as 0 core and other cores, i.e. program runs address.In the present invention, for example can be will be in DSP for program
The new algorithm run in equipment.
After program is loaded into each core of DSP, a PCIE MSI interrupt is triggered, after DSP0 core receives interruption
Program operation address is jumped to automatically and is started, and the IPC that other cores are triggered after the starting of 0 core is interrupted, so that other cores are transported
Row.
Next, describing the work flow diagram of the system according to the present invention with reference to Fig. 3, specific work process is as follows:
Step 1, system electrification；
Step 2, dsp board card initialization go forward side by side line link training；
Step 3, host computer enumerate dsp board card；
Step 4, the system reboot if enumerating failure, PC issue reset signal, return to step 2, successful then enter step 5；
Step 5 is enumerated successfully and distributes resource for DSP, and the mapping of PCIE bus address is carried out；
Step 6, host computer by program transportation to DSP and trigger the starting of DSP multicore；
Step 7, DSP receive data by PCIE dma mode, carry out related operation, and operation result are returned upper
Machine；Specifically, the dma controller at the host computer operation end DSP is stored in host computer to read and write the memory of host computer to read
Data in memory.
If desired step 8 reloads application program, then start DSP warm reset, and return step 6 re-executes DSP and opens
Dynamic, operational process, otherwise process terminates.
One or more embodiments of the invention can also in storage medium, (it can also be by more completely by reading and executing
Referred to as ' non-transitory computer-readable storage medium ') on the computer executable instructions (for example, one or more program) that record
To execute the function of one or more embodiments in above-described embodiment and/or include for executing one in above-described embodiment
One or more circuits (for example, specific integrated circuit (ASIC)) of the function of multiple embodiments system or device calculating
Machine realizes, and by the computer by system or device for example can by reading and executing computer from storage media
It executes instruction to execute the function of one or more embodiments in above-described embodiment and/or control one or more circuits
Method is performed to execute the functions of one or more embodiments in above-described embodiment to realize.Computer may include one
A or multiple processors (for example, central processing unit (CPU), microprocessing unit (MPU)) and may include for reading simultaneously
Execute the independent computer of computer executable instructions or the network of separate processor.Computer executable instructions can for example from
Network or storage medium are provided to computer.Storage medium may include such as hard disk, random access memory (RAM),
Read-only memory (ROM), the storage device of distributed computing system, CD (such as compact disk (CD), digital multi-purpose disk
(DVD) or Blu-ray disc (BD)TM), flash memory device, one or more of storage card etc..
The embodiment of the present invention can also be realized by following method, that is, pass through network or various storage mediums
The software (program) for executing the function of above-described embodiment is supplied to system or device, the computer of the system or device or in
The method that Central Processing Unit (CPU), microprocessing unit (MPU) read and execute program.
Although describing the present invention by reference to exemplary embodiment, it should be appreciated that, the present invention is not limited to disclosed
Exemplary embodiment.Scope of the appended claims should be endowed broadest explanation to cover all such modifications and wait
Same structure and function.
Claims (9)
1. a kind of method based on host computer PC IE bus dynamically load multi-core DSP, which is characterized in that the described method includes:
Make multi-core DSP and host computer communication connection；
By program transportation to the multi-core DSP；
PCIE MSI interrupt is triggered, so that the multi-core DSP runs described program；
Wherein, the multi-core DSP receives data, and the fortune that will run described program from the host computer by PCIE dma mode
It calculates result and returns to the host computer.
2. the method according to claim 1 based on host computer PC IE bus dynamically load multi-core DSP, wherein described more
Core DSP is via PCIE interchanger and the host computer communication connection or the multi-core DSP via PCIE golden finger and host computer
Communication connection.
3. the method according to claim 1 based on host computer PC IE bus dynamically load multi-core DSP, wherein described more
Core DSP is C6678 board.
4. the method according to claim 1 based on host computer PC IE bus dynamically load multi-core DSP, wherein on described
Described program is transmitted to each core of the multi-core DSP by position machine.
5. the method according to claim 4 based on host computer PC IE bus dynamically load multi-core DSP, wherein described more
A core of core DSP jumps to program operation address after receiving the PCIE MSI interrupt automatically and starts, and in the core
After being triggered, the IPC of other cores is interrupted.
6. the method according to claim 1 based on host computer PC IE bus dynamically load multi-core DSP, further includes: described
Host computer enumerates the multi-core DSP and distributes resource for the multi-core DSP, carries out the mapping of PCIE bus address.
7. the method according to claim 6 based on host computer PC IE bus dynamically load multi-core DSP, if described upper
Machine enumerates the multi-core DSP failure, then reinitializes the multi-core DSP.
8. the method according to claim 1 based on host computer PC IE bus dynamically load multi-core DSP, if necessary to again
Loading procedure, then DSP is by warm reset, and program is re-loaded to most multi-core DSPs by the host computer.
9. a kind of system based on host computer PC IE bus dynamically load multi-core DSP, comprising:
Multi-core DSP is configured as carrying out operation to data are imported according to program, and returns the result；And
Host computer, is configured as enumerating and starting the multi-core DSP, imports data to the multi-core DSP by PCIE interface,
Wherein, the host computer and will run described program by PCIE dma mode to importing data to the multi-core DSP
Operation result returns to the host computer.
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| CN201910587781.1A CN110427223A (en) | 2019-07-02 | 2019-07-02 | A kind of method and system based on host computer PC IE bus dynamically load multi-core DSP |
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| CN201910587781.1A CN110427223A (en) | 2019-07-02 | 2019-07-02 | A kind of method and system based on host computer PC IE bus dynamically load multi-core DSP |
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2019
- 2019-07-02 CN CN201910587781.1A patent/CN110427223A/en active Pending
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| US20120254647A1 (en) * | 2011-03-30 | 2012-10-04 | Symbol Technologies, Inc. | Dynamic allocation of processor cores running an operating system |
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| CN107241591A (en) * | 2017-06-30 | 2017-10-10 | 中国航空工业集团公司雷华电子技术研究所 | A kind of embedded 3D video image display methods of airborne radar and system |
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