CN110417559B

CN110417559B - Ethernet power supply equipment and detection method

Info

Publication number: CN110417559B
Application number: CN201810403210.3A
Authority: CN
Inventors: 付世勇; 庄艳; 许享恩; 董歧; 潘厚源; 华睿
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-04-28
Filing date: 2018-04-28
Publication date: 2022-10-11
Anticipated expiration: 2038-04-28
Also published as: CN110417559A

Abstract

A Power over Ethernet (PoE) device and a detection method are disclosed. The method comprises the following steps: and when the PoE equipment outputs PoE detection potential to the detection line pair in the first line pair group of the Ethernet port, the switch connected with the return line pair in the second line pair group is disconnected. Since the switch circuit of the return line pair in the second line pair group is turned off when the PoE detection potential is output to the line pair in the first line pair group, the current generated by the PoE detection potential cannot flow back from the return line pair in the second line pair group, thereby preventing PoE detection failure caused by a short circuit of a load in a power receiving device (PD). The PoE equipment and the detection method can be compatible with the PD which is not completely isolated between two groups of line pairs.

Description

Ethernet power supply equipment and detection method

Technical Field

The present application relates to the field of communications, and in particular, to an ethernet power supply device and a detection method.

Background

A Power over Ethernet (PoE) system includes a PSE (Power sourcing equipment) device and a PD (powered device). The PSE device provides power to the PD while communicating with the PD via the ethernet twisted pair. The ethernet twisted pair comprises 8 wires, numbered 1 to 8. Where

lines

1 and 2 are paired,

lines

3 and 6 are paired,

lines

4 and 5 are paired, and

lines

7 and 8 are paired. The two wires in a pair are twisted together. The widely used gigabit Ethernet uses 1,2 wire pair and 3,6 wire pair for communication, and 4,5 wire pair and 7,8 wire pair are vacant. Thus, 1,2 and 3,6 wire pairs are one set, 4,5 and 7,8 wire pairs are the other set. Early ethernet power supplies typically used pairs of data lines (1, 2 pairs and 3,6 pairs) to supply power. The new power over ethernet may use two sets of wire pairs to power together. Fig. 1 and 2 show two designs of circuitry within a PD. In fig. 1, the data line pair group and the idle line pair group have respective full-bridge rectifier circuits, so that the data line pair group and the idle line pair group are completely isolated. In fig. 2, the data line pair has a full-bridge rectifier circuit, while the idle line pair does not, so that there is a connection between 1,2 line pair and 7,8 line pair.

As shown in fig. 3, if only 1 set of line pairs is used to supply power, the connection 201 between 1,2 and 7,8 pairs, or between 3,6 and 4,5 pairs, does not adversely affect the power supply of the PSE device 10 to the PD 20 since the idle pair set of the PSE device 10 may not be grounded. Thus, early PDs have widely adopted a circuit design as shown in fig. 2 or similar.

As shown in fig. 4, the return current pair (RTN in the figure) in the two pairs of lines of the new PSE device 10 is grounded, and a loop is formed between the-54 volt (V) power terminal of the 1,2 pair and the ground terminal of the 7,8 pair in the PSE device 10 via the connection 201 in the PD 20. This loop causes the load in the PD to be shorted. Therefore, PDs that support two wire-pair power typically employ a circuit design such as that shown in fig. 1 or similar.

However, since PDs employing circuit designs such as that shown in fig. 2 or similar are widely used, new PSE devices are not compatible with PDs employing such designs.

Disclosure of Invention

The present application provides a PoE device to accommodate PDs that do not have complete isolation between the two sets of wire pairs.

In a first aspect, a PoE device is provided, comprising: the power supply management circuit comprises a power supply management circuit, an Ethernet port and a first switch circuit. The ethernet port includes a first set of contacts and a second set of contacts. The first set of contacts includes a first pair of contacts and a second pair of contacts of the ethernet port. The second contact pair is a return contact pair in the first contact set. The second contact set includes a third contact pair and a fourth contact pair of the ethernet port. The fourth contact pair is a return contact pair in the second contact set. The fourth contact pair is connected to the first switch circuit. The power supply management circuit is configured to disconnect the first switch circuit when outputting the PoE detection potential to the first contact pair.

Since the return contact pairs in the second contact set are grounded via the switching circuit, rather than directly, disconnecting the switching circuit when outputting the PoE detection potential to the contact pairs in the first contact set can avoid forming a loop between the first contact pair and the return contact pair in the second contact set. The PoE device avoids PoE detection failure caused by short circuit of a load in the PD, so that the PD which is not completely isolated between two groups of line pairs is compatible.

With reference to the first aspect, in a first implementation of the first aspect, the PoE device further includes a second switch circuit, where the second contact pair is connected to the second switch circuit, and the power supply management circuit is further configured to turn on the second switch circuit when outputting a PoE detection potential to the first contact pair, and turn on the first switch circuit and turn off the second switch circuit when outputting a PoE detection potential to the third contact pair.

While a PD that does not have complete isolation between two sets of pairs typically employs a design such as that shown in fig. 2, there may be other designs or other ways of connecting two sets of pairs of a PD due to line aging. Thus, both contact pair sets are grounded via a switching circuit, rather than being directly grounded, to more fully accommodate PDs that do not have complete isolation between the two sets of wire pairs.

With reference to the first aspect or the first implementation of the first aspect, in a second implementation of the first aspect, the first contact pair is connected to a first detection end of the power supply management circuit. The second contact pair is connected to a first end of the second switching circuit. The third contact pair is connected with the second detection end of the power supply management circuit. The fourth contact pair is connected to the first end of the first switch circuit. And the second end of the second switch circuit is connected with the second reflux end of the power supply management circuit. And the second end of the first switch circuit is connected with the first return end of the power supply management circuit. And the control end of the second switch circuit is connected with the second control end of the power supply management circuit. And the control end of the first switch circuit is connected with the first control end of the power supply management circuit.

With reference to the second implementation of the first aspect, in a third implementation of the first aspect, the power supply management circuit includes a PSE chip, a first control circuit, and a second control circuit. The first detection end of the power supply management circuit is a first detection pin of the PSE chip. And a second detection terminal of the power supply management circuit is a second detection pin of the PSE chip. And the second control end of the power supply management circuit is one end of the second control circuit. The other end of the second control circuit is connected with the first detection pin. The second control circuit is configured to output a PoE detection potential to the control terminal of the second switch circuit in response to the first detection pin outputting the PoE detection potential. The first control end of the power supply management circuit is one end of the first control circuit. The other end of the first control circuit is connected with the second detection pin. The first control circuit is used for responding to the second detection pin to output PoE detection potential and outputting conducting potential to the control end of the first switch circuit.

With reference to the second implementation of the first aspect, in a fourth implementation of the first aspect, the power supply management circuit includes a processing circuit and a PSE chip. The processing circuit is connected with the PSE chip. The first detection end of the power supply management circuit is a first detection pin of the PSE chip. And a second detection terminal of the power supply management circuit is a second detection pin of the PSE chip. The second control end of the power supply management circuit is the first end of the processing circuit. The first control end of the power supply management circuit is the second end of the processing circuit. The processing circuit is used for sending an instruction for executing detection by using the first detection pin to the PSE chip and maintaining output conduction potential to the first end. Wherein a duration of outputting the on potential to the first terminal is at least sufficient for the PSE chip to perform detection with the first detection pin. Sending an instruction to perform detection with the second detection pin to the PSE chip after stopping outputting the on potential to the first terminal, and maintaining outputting the on potential to the second terminal. Wherein a duration of outputting the on potential to the second terminal is at least sufficient for the PSE chip to perform detection with the second detection pin.

With reference to the first aspect or any one of the first to fourth implementation manners of the first aspect, in a fifth implementation manner of the first aspect, the power supply management circuit is further configured to turn on the first switch circuit when the isolation detection potential is output to the first contact pair. This allows detection of isolation between the two sets of pairs of PDs.

With reference to the first aspect or any one of the first to fifth implementations of the first aspect, in a sixth implementation of the first aspect, the power supply management circuit is further configured to turn on the second switch circuit when the isolation detection potential is output to the third contact pair. This allows detection of isolation between the two sets of pairs of PDs.

In a second aspect, a PoE detection method is provided, including a PoE device outputting PoE detection potential to a detection line pair in a first line pair group of an ethernet port, opening a switch connected to a return line pair in a second line pair group. Since the switch circuit of the return line pair in the second line pair group is disconnected when the PoE detection potential is output to the line pair in the first line pair group, the current generated by the PoE detection potential cannot flow back from the return line pair in the second line pair group, thereby avoiding the failure of PoE detection caused by the short circuit of the load in the PD. This approach may be compatible with PDs that do not have complete isolation between the two sets of pairs.

With reference to the second aspect, in a first implementation of the second aspect, the method further includes: when the PoE equipment outputs PoE detection potential to a detection line pair in a first line pair group of the Ethernet port, a switch connected with a return line pair in the first line pair group is conducted. And when the PoE equipment outputs PoE detection potential to a detection line pair in a second line pair group of the Ethernet port, switching on a switch connected with the return line pair in the second line pair group, and switching off the switch connected with the return line pair in the first line pair group.

With reference to the second aspect or the first implementation of the second aspect, in a second implementation of the second aspect, the method further includes: and when the PoE equipment outputs the isolated detection potential to the detection line pair in the first line pair group, the switch connected with the return line pair in the second line pair group is switched on.

With reference to the second aspect, the first implementation of the second aspect, or the second implementation of the second aspect, in a third implementation of the second aspect, the method further includes: and when the PoE equipment outputs the isolated detection potential to the detection line pair in the second line pair group, the switch connected with the return line pair in the first line pair group is switched on.

In a fifth aspect, a computer-readable medium is provided. The computer readable medium stores a program executable by a computer. The program comprising instructions for carrying out the method of the second aspect or any implementation thereof.

Drawings

FIG. 1 is a circuit design of a PD;

FIG. 2 is another circuit design of a PD;

FIG. 3 is a block diagram of a PoE system;

FIG. 4 is a block diagram of another PoE system;

FIG. 5 is a block diagram of a PoE system in an embodiment of the present invention;

fig. 6 shows a PoE detection method according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention are described below with reference to fig. 5-6.

Fig. 5 is a block diagram of a PoE system according to an embodiment of the present invention. Where PoE device 10 is a PSE device and PoE device 20 is a PD. PoE device 10 can also include PD circuitry to draw power from other PoE devices. PoE device 20 may also include PSE circuitry to power other PoE devices. A PoE device that includes both PSE circuitry and PD circuitry may be referred to as a cascaded PoE device. Fig. 5 shows only one circuit design in an embodiment of the invention, in which some elements may be omitted or replaced.

The PSE device 10 includes a power management circuit 110, an ethernet port 120, a first switching circuit 140 and a second switching circuit 130. The ethernet port 120 includes 8 contacts, numbered 1-8, for connection to lines 1-8, respectively, of the ethernet lines.

The power management circuitry includes a PSE chip 11010, a first control circuit 11030, a second control circuit 11020, and a processing circuit 11040. These elements are not essential in the power management circuit. The PSE chip is configured to perform a PoE protocol specified detection operation to determine whether the ethernet port 120 is connected to a PD or an ethernet device that does not support PoE.

The 8 contacts of the ethernet port 120 belong to a first contact group and a second contact group, respectively. The first contact set includes a

first contact pair

1,2 and a

second contact pair

3,6. The

first contact pair

1,2 is a power supply contact pair.

Second contact pair

3,6 is a reflow contact pair. The

second contact pair

3,6 is connected to the second switch circuit 130, and is grounded via the second switch circuit 130, not directly.

The

first contact pair

1,2 is connected to the first detection terminal 1110 of the power management circuit. The

second contact pair

3,6 is connected to a first terminal of a second switching circuit 130. A second terminal of the second switching circuit 130 is connected to the second return terminal 1130 of the power management circuit 110. The second return 1130 is connected to ground. The control terminal of the second switching circuit 130 is connected to the second control terminal 1150 of the power management circuit 110.

The second contact set includes a

third contact pair

4,5 and a

fourth contact pair

7,8. The

third contact pair

4,5 is a power supply contact pair.

Fourth contact pair

7,8 is a reflow contact pair. The

fourth contact pair

7,8 is connected to the first switch circuit 140, and is grounded via the first switch circuit 140, not directly.

The

third contact pair

4,5 is connected to the second detection terminal 1120 of the power management circuit. The

fourth contact pair

7,8 is connected to the first terminal of the first switch circuit 140. The second terminal of the first switch circuit 140 is connected to the first return terminal 1140 of the power management circuit 110. The first return 1140 is grounded. The control terminal of the first switch circuit 140 is connected to the first control terminal 1160 of the power management circuit 110.

The wires of the ethernet wires connected to the respective contact pairs belong to one wire pair. Two line pairs connecting one contact group belong to one line pair group.

The roles of the above-described supply contact pair and return contact pair may be interchanged. For example, the

fourth contact pair

7,8 is a supply contact pair, and the

third contact pair

4,5 is a return contact pair.

A power supply management circuit 110 for outputting the PoE detection potential to the power supply contact pair (the

first contact pair

1,2 or the third contact pair 4, 5). PoE detection potential refers to potential that PSE chip 11010 outputs when performing detection operation and/or classification operation specified by PoE protocol. The corresponding PoE detection includes detection operations and/or classification operations. The first detection terminal 1110 of the power management circuit 110 is a first detection pin 11011 of the PSE chip 11010. The second detection terminal 1120 of the power management circuit 110 is a second detection pin 11012 of the PSE chip 11010. The first detection pin 11011 and the second detection pin 11012 are detection pins (D) of the PSE chip 11010, and may belong to the same PoE channel or different PoE channels. The PoE detection potentials are output by the detection pins 11011, 11012 of the PSE chip 11010 to the pair of supply contacts. PSE chip 11010 additionally has a sense pin (S), not shown, to measure current on the contact pair to implement a sense operation or a classification operation.

To enable the PSE device 10 to accommodate PDs that do not have complete isolation between the two sets of wire pairs (i.e., there is a connection 201), the PSE device 10 disconnects the return wire pairs in one set of wire pairs when performing PoE detection on the other set of wire pairs. This operation is performed by the power management circuit 110 controlling the second switching circuit 130 or the first switching circuit 140. For example, in the PoE detection method shown in fig. 6: in step 610, when the pse device 10 outputs PoE detection potential to the

detection line pair

1,2 in the first line pair group of the ethernet port 120, the second switch circuit 130 connected to the

return line pair

3,6 in the first line pair group is turned on, and the first switch circuit 140 connected to the

return line pair

7,8 in the second line pair group is turned off. For another example, when the PSE device 10 outputs PoE detection potential to the

detection line pair

4,5 in the second line pair group of the ethernet port 120, the first switch circuit 140 connected to the

return line pair

7,8 in the second line pair group is turned on, and the second switch circuit 130 connected to the

return line pair

3,6 in the first line pair group is turned off.

Since PDs that do not have complete isolation between the two sets of pairs typically employ a design as shown in fig. 2, the PSE device may omit the second switching circuit 130 and its control circuitry. The reflow contact pair in the first contact group (the second contact pair 3,6) may be directly grounded without passing through a switch circuit. Since the reflow contact pairs in the first contact set are directly grounded, step 610 is: when the PSE device 10 outputs PoE detection potential to the

detection line pair

1,2 in the first line pair group of the ethernet port 120, the first switch circuit 140 connected to the

return line pair

7,8 in the second line pair group is turned off.

If the pair of return contacts of the first line pair group and the second line pair group are both grounded via the switch circuit, the power supply management circuit 110 turns on the second switch circuit 130 and turns off the first switch circuit 140 when outputting the PoE detection potential to the

first contact pair

1,2. For example, the power supply management circuit 110 turns on the second switch circuit 130 with the second control terminal 1150 and turns off the first switch circuit 140 with the first control terminal 1160 when outputting the PoE detection potential with the first detection terminal 1110.

When the power supply management circuit 110 outputs the PoE detection potential to the

third contact pair

4,5, the first switch circuit 140 is turned on, and the second switch circuit 130 is turned off. For example, the power supply management circuit 110 turns off the second switch circuit 130 with the second control terminal 1150 and turns on the first switch circuit 140 with the first control terminal 1160 when outputting the PoE detection potential with the second detection terminal 1120.

PSE chips typically have multiple modes of operation. For example, the PSE chip may be in an automatic (auto) mode, a semi-automatic (semi-auto or semi) mode, or a manual (manual) mode. The PSE chip in autonomous mode automatically attempts PoE detection and automatically powers the ethernet port 120 after successful detection. And the PSE chip in the semi-automatic mode automatically tries PoE detection after the detection is enabled, and records the detection result. And the PSE chip in the manual mode tries one-time PoE detection after the detection is enabled, and records the detection result. The processor reads the detection result recorded by the PSE chip in the semi-automatic mode or the manual mode. If the detection result is successful, the processor instructs the PSE chip to supply power to the ethernet port 120 or instructs the conversion circuit to turn on the switch between the power supply contact pair to supply power to the ethernet port 120. As shown in fig. 3 or fig. 4, a gate (G) pin of the PSE chip is connected to a control terminal of the switching circuit. When the power is supplied to the ethernet port 120, the gate pin of the PSE chip controls the switch circuit to be turned on. The switching circuit may also be integrated within the PSE chip. The power supply pins of the PSE chip are connected to pairs of power supply contacts of the ethernet port 120. When power is supplied to the ethernet port 120, the power pin of the PSE chip directly supplies power (the power pin of the PSE chip serves as a power source). Although the power source is shown as-54V, the potential of the power source may be anywhere between-50V to-57V, or anywhere between +50V to + 57V. If the potential value of the power supply is positive, the connection relationship between the power supply and the ground and the contact pairs in the contact group can be reversed. For example,

contact pair

1,2 is grounded (directly or via a switch) and

contact pair

3,6 is connected to a power supply (directly or via a switch). At this time,

contact pair

1,2 is a reflow contact pair.

The design of fig. 5 has the second switching circuit 130 and the first switching circuit 140 turned off by default. Therefore, when the first detection pin 11011 or the second detection pin 11012 outputs the PoE detection potential, the corresponding switch circuit is turned on. If the second switching circuit 130 and the first switching circuit 140 are closed by default, the switching circuit connected to another set of contact pairs is opened when the PoE detection potential is output at the first detection pin 11011 or the second detection pin 11012.

The first detection pin 11011 and the second detection pin 11012 may be directly connected to the control terminal of the second switch circuit 130 and the control terminal of the first switch circuit 140, respectively, to turn on the corresponding switch circuits. However, the PoE detection potential may not be sufficient to turn on the switching circuit. And the values of the PoE detection potential differ in the detection phase and the classification phase, it may be difficult to adapt the individual switching circuits. Therefore, the first detection pin 11011 may be connected to one end of the second control circuit 11020, and the other end of the second control circuit 11020 may be connected to the control terminal of the second switch circuit 130. The second detection pin 11012 is connected to one end of the first control circuit 11030, and the other end of the first control circuit 11030 is connected to a control end of the first switch circuit 140. The second control circuit 11020 is configured to output a PoE detection potential to a control terminal of the second switch circuit 130 in response to the first detection pin 11011 outputting the PoE detection potential. The first control circuit 11030 is configured to output a PoE detection potential to a control terminal of the first switch circuit 140 in response to the second detection pin 11012 outputting the PoE detection potential. The second control circuit 11020 and the first control circuit 11030 may be a signal processor including, for example, a signal amplifier and a voltage regulator.

If the PSE chip 11010 is not in the autonomous mode, the processor may control the lines detected by the PSE chip 11010 and thus may output control signals to the control terminal of the second switching circuit 130 and the control terminal of the first switching circuit 140 by the processing circuit 11040 including the processor and the switching circuit. The first terminal 11041 of the processing circuit 11040 is connected to the control terminal of the second switching circuit 130. A second terminal 11042 of the processing circuit 11040 is connected to a control terminal of the first switching circuit 140. The conversion circuit may be an integrated circuit for receiving an instruction of the processor and outputting the on potential to the control terminal of the switch circuit based on the received instruction.

The processor sends an instruction to PSE chip 11010 to perform detection with the first detection pin 11011. At the same time or earlier, the processor instructs the conversion circuit to maintain the output turn-on potential with the first terminal 11041 of the processing circuit 11040. The duration of the on potential output to the first terminal 11041 is at least sufficient for the PSE chip 11010 to perform detection with the first detection pin 11011. The processor instructs the conversion circuit to stop outputting the on potential to the first terminal 11041 before sending an instruction to the PSE chip to perform detection with the second detection pin 11012. After stopping outputting the on potential to the first terminal 11041, and at the same time or earlier when the processor sends an instruction to the PSE chip to perform detection with the second detection pin 11012, the processor instructs the conversion circuit and maintains outputting the on potential with the second terminal 11042 of the processing circuit 11040. The duration of the on potential output to the second terminal 11042 is at least long enough for the PSE chip 11010 to perform detection with the second detection pin 11012.

Since both the PSE chip and the processing circuitry can control the control terminal of the second switching circuit 130 and the control terminal of the first switching circuit 140, the PSE device may optionally have one or similar circuit configurations to accommodate PDs that do not have complete isolation between the two sets of wire pairs. PSE devices may also include both or similar circuit configurations.

The PSE device 10 may measure isolation between two sets of pairs of the PD. E.g., the power management circuit 110, is also used to output the isolated detection potential to the

first contact pair

1,2. When the isolation detection potential is output, the power supply management circuit 110 turns on the first switch circuit 140 and turns off the second switch circuit 130. The isolation detection potential may be output by a circuit in the power supply management circuit 110 not shown in fig. 5. If the power management circuit 110 detects that the isolation sensing potential is producing current, it indicates that there is no isolation between the

first pair

1,2 and the

fourth pair

7,8 of the PD. For example, the power supply management circuit 110, is further configured to output the isolation detection potential to the

third contact pair

4,5. When the isolation detection potential is output, the power supply management circuit 110 turns on the second switch circuit 130 and turns off the first switch circuit 140. If the power management circuit 110 detects that the isolated sense potential produces a current, it indicates that the

third wire pair

4,5 and the

second wire pair

3,6 of the PD are not isolated. Measuring isolation between two sets of pairs of PD pairs may also be performed by a Connection Check (CC) of PoE. Accordingly, the isolation detection potential is a potential generated for performing the CC operation. When performing CC operation, the PSE chip 11010 outputs an isolated detection potential with the first detection pin 11011 and the second detection pin 11012. The power management circuit 110 turns on the first switching circuit 140 and the second switching circuit 130. If the result of the CC operation is a short circuit and the PSE device 10 does not detect a short circuit in the first pair of lines or the second pair of lines, it indicates no isolation between the two pairs of the PD.

If the isolation detection passes, i.e., the two sets of pairs of the PD 20 are isolated from each other, the PSE device 10 may supply power to the PD 20 using either 2 pairs or 4 pairs of lines. If the isolation detection fails, i.e., the two sets of pairs of the PD 20 are not isolated from each other, then the PSE device 10 can only supply power to the PD 20 using 2 pairs of lines.

If the PSE device 10 is supplying power to the PD 20 using only 2 pairs of lines, the PSE device 10 turns off the switching circuitry for the return pair of the other 2 pairs of lines. When the PSE device 10 supplies power to the

first contact pair

1,2, the second switch circuit 130 is turned on and the first switch circuit 140 is turned off. When the PSE device 10 supplies power to the

third contact pair

4,5, the first switch circuit 140 is turned on and the second switch circuit 130 is turned off. Control of the switching circuit may be accomplished by the power management circuit 110.

In the above embodiments, it may be entirely or partially implemented by software, hardware, or a combination thereof. When implemented in software, or in a combination of software and hardware, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a storage medium or transmitted from one storage medium to another. For example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wire (e.g., coaxial cable, twisted pair, or fiber optic) or wirelessly (e.g., infrared, wireless, microwave, etc.). The storage medium may be any available medium that can be accessed by a computer or a data storage device comprising one or more integrated media, servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., optical disk), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A Power over Ethernet (PoE) device for powering a Powered Device (PD), wherein,

the PoE device includes a power management circuit, an ethernet port and a first switching circuit,

wherein the content of the first and second substances,

the Ethernet port comprises a first contact group and a second contact group;

the first contact group comprises a first contact pair and a second contact pair of the Ethernet port, and the second contact pair is a backflow contact pair in the first contact group;

the second contact group comprises a third contact pair and a fourth contact pair of the Ethernet port, the fourth contact pair is a backflow contact pair in the second contact group, and the fourth contact pair is connected with the first switch circuit;

the power supply management circuit is used for switching off the first switch circuit when the PoE detection potential is output to the first contact pair;

the first contact pair is connected with a first detection end of the power supply management circuit;

the fourth contact pair is connected with the first end of the first switch circuit;

the second end of the first switch circuit is connected with the first return end of the power supply management circuit;

the control end of the first switch circuit is connected with the first control end of the power supply management circuit;

wherein the content of the first and second substances,

the power supply management circuit is further configured to turn on the first switch circuit when the first contact pair outputs the isolation detection potential;

the PoE device further includes a second switch circuit, the second contact pair is connected to the second switch circuit, and the power supply management circuit is further configured to turn on the second switch circuit when outputting a PoE detection potential to the first contact pair, and turn on the first switch circuit and turn off the second switch circuit when outputting a PoE detection potential to the third contact pair;

wherein, the first and the second end of the pipe are connected with each other,

the second contact pair is connected with the first end of the second switch circuit;

the third contact pair is connected with the second detection end of the power supply management circuit;

the second end of the second switch circuit is connected with the second reflux end of the power supply management circuit;

and the control end of the second switch circuit is connected with the second control end of the power supply management circuit.

2. A PoE device as recited in claim 1 wherein the power management circuit comprises a Power Sourcing Equipment (PSE) chip, a first control circuit and a second control circuit;

a first detection end of the power supply management circuit is a first detection pin of the PSE chip;

a second detection end of the power supply management circuit is a second detection pin of the PSE chip;

the second control end of the power supply management circuit is one end of the second control circuit, the other end of the second control circuit is connected with the first detection pin, and the second control circuit is used for responding to the first detection pin to output PoE detection potential and outputting conduction potential to the control end of the second switch circuit;

the first control end of the power supply management circuit is one end of the first control circuit, the other end of the first control circuit is connected with the second detection pin, and the first control circuit is used for responding to the second detection pin to output PoE detection potential and outputting breakover potential to the control end of the first switch circuit.

3. A PoE device as recited in claim 1 wherein the power management circuitry comprises processing circuitry and a PSE chip, the processing circuitry being connected to the PSE chip;

the second control end of the power supply management circuit is the first end of the processing circuit, and the first control end of the power supply management circuit is the second end of the processing circuit;

the processing circuit is used for sending an instruction of executing detection by using the first detection pin to the PSE chip and maintaining output of a conducting potential to the first end, wherein the duration of outputting the conducting potential to the first end is at least enough for the PSE chip to execute detection by using the first detection pin, the processing circuit is used for sending the instruction of executing detection by using the second detection pin to the PSE chip after stopping outputting the conducting potential to the first end and maintaining output of the conducting potential to the second end, and the duration of outputting the conducting potential to the second end is at least enough for the PSE chip to execute detection by using the second detection pin.

4. A PoE device according to any one of claims 1 to 3,

the power supply management circuit is further configured to turn on the second switch circuit when the isolation detection potential is output to the third contact pair.

5. A power over ethernet (PoE) detection method applied to a PoE device as claimed in any one of claims 1 to 4, the method comprising: when the PoE equipment outputs PoE detection potential to the detection line pair in the first line pair group of the Ethernet port, a switch connected with the return line pair in the second line pair group is disconnected.

6. The method of claim 5, further comprising:

when PoE equipment outputs PoE detection potential to a detection line pair in a first line pair group of an Ethernet port, a switch connected with a return line pair in the first line pair group is switched on;

and when the PoE equipment outputs PoE detection potential to a detection line pair in a second line pair group of the Ethernet port, switching on a switch connected with the return line pair in the second line pair group, and switching off the switch connected with the return line pair in the first line pair group.

7. The method of claim 5 or 6, further comprising:

and when the PoE equipment outputs the isolated detection potential to the detection line pair in the first line pair group, the switch connected with the return line pair in the second line pair group is switched on.

8. The method of any of claims 5 to 6, further comprising:

and when the PoE equipment outputs the isolated detection potential to the detection line pair in the second line pair group, the switch connected with the return line pair in the first line pair group is switched on.

9. The method of claim 7, further comprising: