CN110417509A - An all-parallel SCMA decoder architecture and its application method - Google Patents

Abstract

The present invention proposes an all-parallel SCMA decoder architecture and its usage method. In the all-parallel SCMA decoder architecture, the input end of the first functional node update module is used as the first input end of the processing unit, and the input end of the register is used as the first input end of the processing unit. The second input terminal of the unit and store the residual initialization result, the output terminal of the first functional node update module is connected with the input terminal of the variable node update module, and the output terminal of the variable node update module is used as the first output terminal of the processing unit and The first input end of the second processing unit is connected, and the output end of the register is connected to the second input end of the adjacent second processing unit as the second output end of the processing unit; the output end of the residual initialization module is connected to the first processing unit The first and second input terminals of the last processing unit are respectively connected to the input terminals of the second functional node update module, and the output terminal of the second functional node update module is connected to the log likelihood ratio Compute module input connections.

Description

An all-parallel SCMA decoder architecture and its application method

technical field

The present invention relates to the technical field of wireless communication, and more specifically, relates to an all-parallel SCMA decoder architecture and a usage method thereof.

Background technique

Non-Orthogonal Multiple Access (NOMA) technology is considered to be one of the most critical technologies in 5G mobile communications. NOMA technology is different from traditional orthogonal transmission. It adopts non-orthogonal transmission at the sending end, and allocates one resource block to multiple users, so that multiple users can simultaneously transmit data in the same resource block, thus greatly improving Spectrum resource utilization. NOMA technology actively introduces multi-user interference at the sending end, so multi-user joint demodulation is required at the receiving end to eliminate interference, for example, serial interference cancellation technology is used to eliminate multiple access interference. In order to minimize multi-user interference, two mainstream NOMA access methods are mainly used at present: non-orthogonal multiple access technology (Power Domain Non-Orthogonal Multiple Access, PD-NOMA) based on power domain multiplexing and Sparse Code Multiple Access (SCMA) based on code domain multiplexing.

SCMA technology is an air interface technology that realizes non-orthogonal access through code domain multiplexing. Its core concept is to perform multi-dimensional modulation through the superposition of code domain non-orthogonal extensions to accommodate more resources under the same number of resource blocks. There are many business users, and the low-complexity multi-user detection technology is adopted at the receiving end to greatly improve the throughput of the communication network under the premise of ensuring the communication quality.

At present, the SCMA algorithm uses a factor graph-based Message Passing Algorithm (MPA) for user detection at the receiving end. Although the MPA algorithm uses the sparse coding characteristics of the SCMA algorithm to reduce the complexity of the detection algorithm, its factor iterative decoding The method still has a relatively high algorithm complexity. The complexity of the MPA algorithm limits the throughput of the SCMA system, and it will also bring a large delay in the hardware implementation process.

Contents of the invention

In order to overcome the defects of low SCMA system throughput and long time delay caused by high algorithm complexity in the prior art, the present invention provides an all-parallel SCMA decoder architecture and its usage method.

In order to solve the problems of the technologies described above, the technical solution of the present invention is as follows:

An all-parallel SCMA decoder architecture, comprising a residual initialization module, at least two sequentially connected processing units consisting of a first functional node update module, a variable node update module, registers, a second function node update module, logarithmic Likelihood ratio calculation module;

Wherein, the input end of the first function node update module is used as the first input end of the processing unit, the input end of the register is used as the second input end of the processing unit, the output end of the first function node update module and the input end of the variable node update module Connection, the output terminal of the variable node update module is used as the first output of the processing unit to connect to the first input terminal of the adjacent next processing unit, and the output terminal of the register is used as the second output terminal of the processing unit to connect to the adjacent next processing unit The second input terminal of the processing unit is connected; the output terminal of the residual initialization module is connected with the first input terminal and the second input terminal of the first processing unit, and the first output terminal and the second output terminal of the last processing unit are respectively connected with the first The input terminal of the second functional node update module is connected, the output terminal of the second functional node update module is connected to the input terminal of the logarithmic likelihood ratio calculation module, and the output terminal of the logarithmic likelihood ratio calculation module is used as the output terminal of the architecture to output decoding result.

In this technical solution, the signal to be decoded is divided into several signal groups and input to the residual initialization module in sequence, and the signal group that completes the residual initialization is input to the first processing unit for signal group data update processing, wherein the residual The initialized signal group is input into the first function node update module to update the function node, and the signal group whose residual initialization is completed is stored in the register, and then the signal group whose function node is updated is input into the variable node update module to update the variable node, That is, the signal group update process of the processing unit is completed; after the first processing unit completes the signal group update process, the processing unit transmits the signal group that has completed the update process and the residual initialization result of the signal group to the adjacent second processing unit for further processing. Processing until the signal group is transmitted to the last processing unit and the processing is completed, the signal group that has completed the update process and the residual initialization result of the signal group are input into the second function node update module for function node update processing, and then the output The signal group is input into the log-likelihood ratio calculation module for log-likelihood ratio calculation, and the final output is the decoding result.

This technical solution converts the iterative process of updating function nodes and variable nodes in the serial architecture into multiple parallel function node update modules and variable node update modules, so that multiple sets of signal data can be placed in the architecture at the same time In the framework of the present invention, function node update and variable node update are performed, wherein the structure of the first function node update module is consistent with that of the second function node update module; by setting a plurality of registers, the residual initialization processing results are stored in each processing unit In the register, the complete expansion of the iterative process is realized to form a pipeline structure.

Preferably, the initialization residual module, the first function node module, the second function node update module, the variable node update module, the register, and the logarithmic likelihood ratio calculation module respectively work according to their preset clock cycles.

Preferably, the number of processing units is 2-5, where the number of processing units is determined according to the number of iterations required for the signal to be decoded.

The present invention also proposes a method for using an all-parallel SCMA decoder architecture, applying the above-mentioned all-parallel SCMA decoder architecture, comprising the following steps:

Divide the signal to be decoded into several signal groups and input them to the residual initialization module in sequence, and input the signal group with residual initialization to the first processing unit for processing, wherein the signal group with residual initialization is input to the first function node The function node is updated in the update module, and the signal group input register of the residual initialization is completed for storage, and then the signal group of the function node update is completed and the variable node is updated in the variable node update module, that is, the signal group update process of the processing unit is completed ;After the first processing unit completes the signal group update process, the processing unit will transfer the updated signal group and the residual initialization result of the signal group to the adjacent second processing unit for processing until the signal group is sent to the last processing unit After the signal group update process is completed in the unit, the signal group and the residual initialization result of the signal group are input into the second function node update module for function node update processing, and then the output signal group is input into the log likelihood ratio calculation module The logarithmic likelihood ratio is calculated, and the final output is the decoding result.

Preferably, the signal group is input according to preset clock cycles in the residual initialization module, the first functional node updating module, the variable node updating module, the register, the second functional node updating module, and the logarithmic likelihood ratio calculation module.

Preferably, the signal to be decoded includes received signal, channel condition, noise power, and codebook input signal.

Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

(1) The throughput of the SCMA algorithm hardware system can be effectively improved by expanding the serial iterative structure into a parallel multi-layer functional node update module and variable node update module architecture;

(2) Input the signal to be decoded according to the clock cycle, and realize that different groups of signals to be decoded are simultaneously decoded on the function node update module and the variable node update module at different levels, further reducing the time delay;

(3) The decoder architecture adopting parallel design can update the update modules and variable nodes of each layer in the architecture, simplify the operation process of each module, reduce the amount of calculation, and further improve the throughput of the system.

Description of drawings

FIG. 1 is a schematic diagram of an all-parallel SCMA decoder architecture of this embodiment.

FIG. 2 is a flowchart of a method for using the fully parallel SCMA decoder architecture of this embodiment.

Detailed ways

The accompanying drawings are for illustrative purposes only and cannot be construed as limiting the patent;

In order to better illustrate this embodiment, some parts in the drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product;

For those skilled in the art, it is understandable that some well-known structures and descriptions thereof may be omitted in the drawings.

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Example 1

As shown in FIG. 1 , it is a schematic structural diagram of an all-parallel SCMA decoder architecture of this embodiment.

The fully parallel SCMA decoder architecture of this embodiment includes a residual initialization module 1, 2 processing units, a second functional node update module 5, and a log likelihood ratio calculation module 6, wherein the processing unit includes a first functional node update Module 2, variable node updating module 3, register 4, first function node updating module 2, and second function node updating module 5 have the same structure.

In the processing unit of this embodiment, the input terminal of the first functional node updating module 2 is used as the first input terminal of the processing unit, the input terminal of the register 4 is used as the second input terminal of the processing unit, and the output terminal of the functional node updating module 2 It is connected with the input end of the variable node update module 3, the output end of the variable node update module 3 is connected with the first input end of the adjacent second processing unit as the first output end of the processing unit, and the output end of the register 4 is used as the processing unit The second output end of the second processing unit is connected to the second input end of the next adjacent processing unit.

In this embodiment, the input terminal of the residual initialization module 1 is used as the input terminal of the fully parallel SCMA decoder architecture, and the output terminal of the residual initialization module 1 is respectively connected to the first input terminal and the second input terminal of the first processing unit. connected, the first output end of the first processing unit is connected to the first input end of the second processing unit adjacently arranged, the second output end of the first processing unit is connected to the second processing unit adjacently arranged The second input terminal is connected; the first output terminal and the second output terminal of the second processing unit are respectively connected to the input terminal of the second functional node update module 5, and the output terminal of the second functional node update module 5 is connected to the logarithmic likelihood The input terminal of the ratio calculation module 6 is connected, and the output terminal of the logarithmic likelihood ratio calculation module 6 is used as the output terminal of the fully parallel SCMA decoder architecture to output the decoding result of the decoding process.

The register in this embodiment is mainly used to store the residual initialization result corresponding to the signal group to be updated in the processing unit.

In this embodiment, the initialization residual module 1, the first function node module 2, the second function node update module 5, the variable node update module 3, the register 4, and the logarithmic likelihood ratio calculation module 6 respectively according to their preset clock cycle to work.

In this embodiment, the number of processing units is determined according to the number of iterations required by the signal to be decoded, so it can be seen that the number of iterations of the signal to be decoded is set to 3 times in this embodiment.

In this embodiment, the second function node update module 2 and the variable node update module 3 in each processing unit are optimized and designed according to the needs of the update process, and the multiplication and addition operations and comparison operations of each module are rationally streamlined. Design, In order to meet the clock matching between modules.

In the specific implementation process, the fully parallel SCMA decoder architecture of this embodiment is used to conduct simulation experiments, and a total of 1024 sets of data are decoded. Specifically, the signal to be decoded is divided into several signal groups and input to the residual initialization module 1 sequentially, and the signal group that completes the residual initialization is input to the first processing unit for signal group update processing, wherein the signal group that completes the residual initialization The signal group is input into the first function node update module 2 to update the function node, and the signal group that has completed the residual initialization is input to the register 4 for storage, and then the signal group that has completed the function node update is input to the variable node update module 3 for variable node Update: After the first processing unit completes the signal group update process, the first processing unit will transmit the signal group that has completed the update process and the residual initialization result of the signal group to the adjacent second processing unit for processing, and repeat the above steps , after the second processing unit completes the signal group update process, the signal group and the residual initialization result of the signal group are input into the second function node update module 5 for function node update processing, and then input into the log likelihood ratio calculation module 6 The logarithmic likelihood ratio is calculated, and the final output is the decoding result.

It can be seen from the above implementation process that the fully parallel SCMA decoder architecture of this embodiment forms a fully pipelined iterative update process, and the first functional node update module 2 and the variable node update module 3 required for each iteration are set in parallel, through The register 4 stores the residual initialization result corresponding to the signal group to be updated in this processing unit and transmits it to the next iteration process, and designs the first function node update module 2, the variable node according to the number of iterations required The number of processing units composed of the updating module 3 and the register 4 is implemented, so as to realize the unfolding of the serial individual iterative updating process.

Assuming that the number of users at the SCMA transmitting end is J=6, the number of multiplexed resource blocks is K=4, the modulation method is Quadrature Phase Shift Keying (QPSK), and each SCMA code word contains 2 bits of information, that is, the code The number of words is M=4, the transmission channel is a Gaussian white noise (Additive White Gaussian Noise, AWGN) channel, and the channel gain is 1, and the SCMA decoder master clock frequency S=50MHz, then the full The theoretical SCMA decoder throughput of the parallel SCMA decoder architecture is:

Among them, t is the number of cycles required for each iteration.

In the simulation process, a total of 1024 sets of data are decoded, and the entire decoding process takes about 11,000 cycles, so the decoding delay time is:

Among them, n is the number of cycles required for the decoding process.

Therefore, the SCMA decoder throughput ' of this embodiment is obtained as:

Wherein, totaldata represents the number of data groups to be decoded.

From the above calculation results, it can be seen that the SCMA decoder throughput obtained by the fully parallel SCMA decoder architecture of this embodiment is basically consistent with the theoretical calculation results, which proves that the fully parallel SCMA decoder architecture of this embodiment can effectively improve SCMA decoding. Encoder throughput.

Example 2

The present embodiment proposes a method for using an all-parallel SCMA decoder architecture, as shown in FIG. 2 , which is a flowchart of a method for using the all-parallel SCMA decoder architecture of this embodiment, including the following steps:

The signal to be decoded is divided into several signal groups and input to the residual initialization module 1 in turn, and the signal group that completes the residual initialization is input to the first processing unit for signal group update processing, wherein the signal group that completes the residual initialization is input In the first functional node update module 2, the function node is updated, and the signal group that completes the residual initialization is stored in the register 4, and then the signal group that completes the function node update is input into the variable node update module 3 to update the variable node; first. After the first processing unit completes the update processing of the signal group, the processing unit transmits the updated signal group and the residual initialization result of the signal group to the next adjacent processing unit for processing until the signal group is sent to the last processing unit After the process is completed, the signal group that has completed the update process and the residual initialization result of the signal group are input into the second function node update module 5 for function node update processing, and then the output signal group is input to the log likelihood ratio calculation module 6, the logarithmic likelihood ratio is calculated, and the final output is the decoding result.

In this embodiment, the signal to be decoded includes the received signal, channel condition, noise power, and codebook input signal, and the signal group is based on the residual initialization module 1, the first functional node update module 2, the variable node update module 3, and the register 4 , the second function node update module 5, and the logarithmic likelihood ratio calculation module 6 preset clock cycles for input.

The method for using the full-parallel SCMA decoder architecture of this embodiment is applied to a full-parallel SCMA decoder architecture, which includes a residual initialization module 1, 2 processing units, a second functional node update module 5, and The number-likelihood ratio calculation module 6, wherein the processing unit includes a first function node update module 2, a variable node update module 3, and a register 4, and the first function node update module 2 and the second function node update module 5 have the same structure.

In the processing unit, the input terminal of the first functional node updating module 2 is used as the first input terminal of the processing unit, and the input terminal of the register 4 is used as the second input terminal of the processing unit; the output terminal of the first functional node updating module 2 is connected with the variable The input terminal of the node update module 3 is connected, the output terminal of the variable node update module 3 is connected with the first input terminal of the adjacent second processing unit as the first output terminal of the processing unit, and the output terminal of the register 4 is used as the first output terminal of the processing unit The second output end is connected to the second input end of the next adjacent processing unit. The input terminal of the residual initialization module 1 is used as the input terminal of the full parallel SCMA decoder architecture, the output terminal of the residual initialization module 1 is connected with the first input terminal and the second input terminal of the first processing unit, and the first processing unit The first output end of the unit is connected to the first input end of the second processing unit adjacently arranged, and the second output end thereof is connected to the second input end of the second processing unit adjacently arranged, and the second processing unit The first output end and the second output end of each are connected to the input end of the second functional node updating module 5 respectively, and the output end of the second functional node updating module 5 is connected to the input end of the logarithmic likelihood ratio calculation module 6, and the logarithm The output terminal of the likelihood ratio calculation module 6 is used as the output terminal of the fully parallel SCMA decoder architecture to output the decoding result after the decoding process is completed.

In this embodiment, the second function node update module 2 and the variable node update module 3 in each processing unit are optimized and designed according to the needs of the update process, and the multiplication and addition operations and comparison operations of each module are rationally streamlined. Design, In order to meet the clock matching between modules.

In the specific implementation process, the fully parallel SCMA decoder architecture of this embodiment is used to conduct simulation experiments, and a total of 1024 sets of data are decoded. Specifically, the signal to be decoded is divided into several signal groups and input to the residual initialization module 1 sequentially, and the signal group that completes the residual initialization is input to the first processing unit for signal group update processing, wherein the signal group that completes the residual initialization The signal group is input into the first function node update module 2 to update the function node, and the signal group that has completed the residual initialization is input to the register 4 for storage, and then the signal group that has completed the function node update is input to the variable node update module 3 for variable node Update: After the first processing unit completes the signal group update process, the first processing unit will transmit the signal group that has completed the update process and the residual initialization result of the signal group to the adjacent second processing unit for processing, and repeat the above steps , after the second processing unit completes the signal group update process, the signal group and the residual initialization result of the signal group are input into the second function node update module 5 for function node update processing, and then input into the log likelihood ratio calculation module 6 The logarithmic likelihood ratio is calculated, and the final output is the decoding result.

The same or similar reference numerals correspond to the same or similar components;

The terms describing the positional relationship in the drawings are only for illustrative purposes and cannot be interpreted as limitations on this patent;

Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (6)

1. a kind of full parellel SCMA decoder architecture, it is characterised in that: be sequentially connected including residual error initialization module, at least two By the first functional node update module, variable node update module, register group at processing unit, the second functional node more New module, logarithm likelihood ratio calculating module；

Wherein, first input end of the input terminal of the first functional node update module as processing unit, register it is defeated Enter second input terminal of the end as processing unit, the output end and variable node of the first functional node update module update mould The input terminal of block connects, first output end and adjacent time of the output end of the variable node update module as processing unit The first input end of a processing unit connects, the output end of the register as processing unit second output terminal with it is adjacent Second input terminal of secondary a processing unit connects；The first of the output end of the residual error initialization module and first processing unit is defeated Enter end, the connection of the second input terminal, the first output end of the last one processing unit, second output terminal respectively with the second functional node The input terminal of update module connects, the output end of the second functional node update module and the input terminal of logarithm likelihood ratio calculating module Connection, output end output decoding result of the output end of the logarithm likelihood ratio calculating module as the framework.

2. full parellel SCMA decoder architecture according to claim 1, it is characterised in that: the initialization residual error module, First functional node module, the second functional node update module, variable node update module, register, log-likelihood calculations Module works according to its preset clock cycle respectively.

3. full parellel SCMA decoder architecture according to claim 1, it is characterised in that: the quantity of the processing unit is 2~5.

4. a kind of application method of full parellel SCMA decoder architecture, which comprises the following steps: by signal to be decoded It is divided into several signal groups and sequentially inputs the residual error initialization module, the signal group for completing residual error initialization inputs first place It is handled in reason unit, wherein the signal group for completing residual error initialization inputs in the first functional node update module and carries out function Node updates, and complete to be stored in the signal group input register that residual error initializes, then complete what functional node updated Variable node update, i.e. the signal group update processing of completion processing unit are carried out in signal group input variable node updates module； After first processing unit completes signal group update processing, processing unit transmits the residual error initialization result of signal group and signal group It is handled into adjacent time processing unit, until signal group is transmitted in the last one processing unit and completes signal group After update processing, the residual error initialization result of signal group and signal group, which inputs, carries out function section in the second functional node update module Then point update processing will carry out log-likelihood calculations in the signal group input logarithm likelihood ratio calculating module of output, finally Output obtains decoding result.

5. the application method of full parellel SCMA decoder architecture according to claim 4, it is characterised in that: the signal group According to residual error initialization module, the first functional node update module, variable node update module, register, the second functional node The preset clock cycle is inputted in update module, logarithm likelihood ratio calculating module.

6. the application method of full parellel SCMA decoder architecture according to claim 4, it is characterised in that: described to be decoded Signal includes receiving signal, channel condition, noise power, code book input signal.