CN110417509A - A kind of full parellel SCMA decoder architecture and its application method - Google Patents
A kind of full parellel SCMA decoder architecture and its application method Download PDFInfo
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Abstract
The present invention proposes a kind of full parellel SCMA decoder architecture and its application method, in full parellel SCMA decoder architecture, first input end of the input terminal of first functional node update module as processing unit, the input terminal of register as processing unit the second input terminal and residual error initialization result is stored, the output end of first functional node update module is connect with the input terminal of variable node update module, the output end of variable node update module is connect as the first output end of processing unit with time first input end of processing unit, the output end of register is connect as the second output terminal of processing unit with the second input terminal of adjacent time processing unit；The output end of residual error initialization module is connect with the first, second input terminal of first processing unit, first, second output end of the last one processing unit is connect with the input terminal of the second functional node update module respectively, and the output end of the second functional node update module and the input terminal of logarithm likelihood ratio calculating module connect.
Description
Technical field
The present invention relates to wireless communication technology field, more particularly, to a kind of full parellel SCMA decoder architecture and its
Application method.
Background technique
Non-orthogonal multiple access (Non-Orthogonal Multiple Access, NOMA) technology is considered as 5G mobile
The most key one of technology in communication.NOMA technology is different from traditional orthogonal transmission, uses nonopiate biography in transmitting terminal
It is defeated, a resource block is distributed into multiple users, multiple users is realized in the same resource block while carrying out data transmission,
Thus substantially increase frequency spectrum resource utilization rate.NOMA technology initiatively introduces multi-user interference in transmitting terminal, thus is receiving
End needs to carry out multi-user association demodulation to eliminate interference, eliminates multi-access inference for example, by using successive interference cancellation techniques.In order to
Multi-user interference is reduced to the greatest extent, mainly uses the NOMA access way of both mainstreams at present: being multiplexed based on power domain
Non-orthogonal multiple access technology (Power Domain Non-Orthogonal Multiple Access, PD-NOMA) and base
In the Sparse Code multiple access technique (Sparse Code Multiple Access, SCMA) of code domain multiplexing.
SCMA technology is a kind of technology of eating dishes without rice or wine that nonopiate access is realized by code domain multiplexing, and core concept is to pass through
The superposition of the nonopiate extension of code domain carries out various dimensions modulation, realizes under same resource block quantity, accommodates more business and uses
Family, and communication is greatly improved under the premise of guaranteeing communication quality using the multiuser detection of low complex degree in receiving end
The handling capacity of network.
Currently, SCMA algorithm uses Message Passing Algorithm (the Message Passing based on factor graph in receiving end
Algorithm, MPA) user's detection is carried out, although MPA algorithm reduces detection the characteristics of SCMA algorithm sparse coding is utilized
The complexity of algorithm, but the decoding process of its factor iteration still has higher algorithm complexity, the complexity limitation of MPA algorithm
The handling capacity of SCMA system, biggish time delay is also brought along during hardware realization.
Summary of the invention
The present invention is that the above-mentioned height of algorithm complexity in the prior art is overcome to cause the handling capacity of SCMA system small and time delay
Big defect provides a kind of full parellel SCMA decoder architecture and its application method.
In order to solve the above technical problems, technical scheme is as follows:
A kind of full parellel SCMA decoder architecture, including residual error initialization module, at least two are sequentially connected by the first function
Can node updates modules, variable node update module, register group at processing unit, the second functional node update module, right
Number likelihood ratio computing module；
Wherein, first input end of the input terminal of the first functional node update module as processing unit, register it is defeated
Enter second input terminal of the end as processing unit, output end and the variable node update module of the first functional node update module
The output end of input terminal connection, variable node update module is single single with adjacent time processing as the first output of processing unit
The first input end connection of member, second output terminal and adjacent time processing unit of the output end of register as processing unit
The second input terminal connection；First input end, the second input terminal of the output end of residual error initialization module and first processing unit
Connection, the first output end of the last one processing unit, the second output terminal input with the second functional node update module respectively
End connection, the output end of the second functional node update module and the input terminal of logarithm likelihood ratio calculating module connect, log-likelihood
Output end than computing module decodes result as the output end output of framework.
In the technical program, signal to be decoded is divided into several signal groups and sequentially inputs the residual error initialization mould
Block, the signal group for completing residual error initialization, which inputs in first processing unit, carries out signal group data update processing, wherein completing residual
The signal group of difference initialization inputs and carries out functional node update in the first functional node update module, and completes residual error initialization
It is stored in signal group input register, is then completed in the signal group input variable node updates module that functional node updates
Carry out variable node update, i.e. the signal group update processing of completion processing unit；First processing unit is completed at the update of signal group
After reason, the residual error initialization result for completing the signal group and the signal group that update processing is transmitted to adjacent secondary by processing unit
It is handled in processing unit, until signal group is transmitted in the last one processing unit and after completing processing, at completion update
The signal group of reason and the residual error initialization result of the signal group input in the second functional node update module and carry out functional node more
Then new processing will carry out log-likelihood calculations, final output in the signal group input logarithm likelihood ratio calculating module of output
Obtain decoding result.
The technical program is more by being converted to the iterative process updated in serial frame to functional node and variable node
A parallel arrangement of functional node update module and variable node update module make can have multiple groups within the same time in framework
Signal data carries out functional node update in framework of the invention and variable node updates, wherein the first functional node updates mould
Block is consistent with the structure of the second functional node update module；By the way that multiple registers are arranged, residual error initialization process result is deposited
Storage realizes being fully deployed for iterative process in the register of each processing unit, forms flowing structure.
Preferably, residual error module, the first functional node module, the second functional node update module, variable node are initialized
Update module, register, logarithm likelihood ratio calculating module work according to its preset clock cycle respectively.
Preferably, the quantity of processing unit is 2~5, wherein the quantity of processing unit iteration according to needed for signal to be decoded
Number determine.
The present invention also proposes a kind of application method of full parellel SCMA decoder architecture, decodes using above-mentioned full parellel SCMA
Device framework, comprising the following steps:
Signal to be decoded is divided into several signal groups and sequentially inputs the residual error initialization module, it is initial to complete residual error
The signal group of change is inputted in first processing unit and is handled, wherein the signal group for completing residual error initialization inputs the first function section
Functional node update is carried out in point update module, and completes to be stored in the signal group input register that residual error initializes, so
It completes to carry out variable node update in the signal group input variable node updates module that functional node updates afterwards, that is, it is single to complete processing
The signal group update processing of member；After first processing unit completes signal group update processing, processing unit will be completed to update processing
The residual error initialization result of signal group and signal group is transmitted in adjacent time processing unit and is handled, until signal group passes
After being sent in the last one processing unit and completing signal group update processing, the residual error initialization result of signal group and the signal group
Progress functional node update processing in the second functional node update module is inputted, the signal group of output is then inputted into log-likelihood
Than carrying out log-likelihood calculations in computing module, final output obtains decoding result.
Preferably, signal group updates mould according to residual error initialization module, the first functional node update module, variable node
Block, register, the second functional node update module, the preset clock cycle is inputted in logarithm likelihood ratio calculating module.
Preferably, signal to be decoded includes receiving signal, channel condition, noise power, code book input signal.
Compared with prior art, the beneficial effect of technical solution of the present invention is:
(1) by the way that serial iteration structure is expanded into parallel arrangement of multilayer functional node update module and variable node
The framework of update module can effectively improve the handling capacity of SCMA hardware algorithm system；
(2) signal to be decoded is inputted according to the clock cycle, realizes different groups of signal to be decoded in the function of different levels
It is decoded simultaneously in node updates module and variable node update module, is further reduced time delay；
(3) using the decoder architecture of Parallel Design can update module to layer each in framework and variable node update mould
Block can simplify the calculating process of each module, operand be reduced, to further increase the handling capacity of system.
Detailed description of the invention
Fig. 1 is the schematic diagram of the full parellel SCMA decoder architecture of the present embodiment.
Fig. 2 is the application method flow chart of the full parellel SCMA decoder architecture of the present embodiment.
Specific embodiment
The attached figures are only used for illustrative purposes and cannot be understood as limitating the patent；
In order to better illustrate this embodiment, the certain components of attached drawing have omission, zoom in or out, and do not represent actual product
Size；
To those skilled in the art, it is to be understood that certain known features and its explanation, which may be omitted, in attached drawing
's.
The following further describes the technical solution of the present invention with reference to the accompanying drawings and examples.
Embodiment 1
As shown in Figure 1, the structural schematic diagram of the full parellel SCMA decoder architecture for the present embodiment.
The full parellel SCMA decoder architecture of the present embodiment, including residual error initialization module 1,2 processing unit, the second function
Energy node updates module 5, logarithm likelihood ratio calculating module 6, wherein processing unit includes the first functional node update module 2, becomes
Measure node updates module 3, register 4, and the structure phase of the first functional node update module 2, the second functional node update module 5
Together.
In the processing unit of the present embodiment, using the input terminal of the first functional node update module 2 as the of processing unit
One input terminal, second input terminal of the input terminal of register 4 as processing unit, the output end of functional node update module 2 with
The input terminal of variable node update module 3 connects, first output of the output end of variable node update module 3 as processing unit
It holds and is connect with the first input end of adjacent time processing unit, second output of the output end of register 4 as processing unit
It holds and is connect with the second input terminal of adjacent time processing unit.
In the present embodiment, input terminal of the input terminal of residual error initialization module 1 as full parellel SCMA decoder architecture is residual
The output end of poor initialization module 1 is connect with the first input end of first processing unit, the second input terminal respectively, at first
First output end of reason unit is connect with the first input end for second processing unit being disposed adjacent, first processing unit
Second output terminal is connect with the second input terminal of second processing unit being disposed adjacent；First output of second processing unit
End, second output terminal are connect with the input terminal of the second functional node update module 5 respectively, the second functional node update module 5
Output end is connect with the input terminal of logarithm likelihood ratio calculating module 6, and the output end of logarithm likelihood ratio calculating module 6 is as full parellel
The output end of SCMA decoder architecture exports the decoding result for completing decoding processing.
Register in the present embodiment is mainly used for storing corresponding to the signal group of the processing to be updated in present treatment unit
Residual error initialization result.
In the present embodiment, initialization residual error module 1, the second functional node update module 5, becomes first functional node module 2
Amount node updates module 3, register 4, logarithm likelihood ratio calculating module 6 work according to its preset clock cycle respectively.
In the present embodiment, quantity the number of iterations according to needed for signal to be decoded of processing unit is determined, it can be seen that this
The number of iterations of signal to be decoded is set as 3 times in embodiment.
In the present embodiment, the second functional node update module 2 in each processing unit and variable node update module 3
It needs to optimize respectively according to renewal process, reasonable flowing water is carried out by the multiply-add operation to each module, comparison operation
Change design, to meet the clock matches between each module.
In the specific implementation process, emulation experiment is carried out using the full parellel SCMA decoder architecture of the present embodiment, shared
1024 groups of data are decoded.Specifically, signal to be decoded is divided into several signal groups and to sequentially input the residual error initial
Change module 1, the signal group for completing residual error initialization, which inputs in first processing unit, carries out signal group update processing, wherein completing residual
The signal group of difference initialization inputs and carries out functional node update in the first functional node update module 2, and completes residual error initialization
Signal group input register 4 in stored, then will complete functional node update signal group input variable node updates
Variable node update is carried out in module 3；After first processing unit completes signal group update processing, first processing unit will be completed more
The residual error initialization result of the signal group and the signal group that newly handle is transmitted in second adjacent processing unit and is handled,
It repeats the above steps, second processing unit initializes the residual error of signal group and the signal group after completing signal group update processing
As a result progress functional node update processing in the second functional node update module 5 is inputted, then inputs log-likelihood calculations again
Log-likelihood calculations are carried out in module 6, final output obtains decoding result.
By above-mentioned implementation process it is found that the full parellel SCMA TLRF translator frame of the present embodiment is configured to the iteration of full continuous-flow type more
First functional node update module 2 required for each iteration and variable node update module 3 are arranged parallel, lead to by new process
It crosses register 4 and residual error initialization result corresponding to the signal group of the processing to be updated in present treatment unit is stored and passed
It is sent to during next iteration, and the number of iteration is designed by the first functional node update module 2, variable node as needed
The quantity for the processing unit that update module 3, register 4 form, to realize the expansion of serial individually iteration renewal process.
Assuming that the resource block quantity K=4 of multiplexing, modulation system is orthogonal phase shift in the number of users J=6 of SCMA transmitting terminal
Keying (Quadrature Phase Shift Keying, QPSK), each SCMA code word include 2bit information, i.e. code word number
For M=4, transmission channel is white Gaussian noise (Additive White Gaussian Noise, AWGN) channel, and channel increases
Benefit is 1, and SCMA decoder master clock frequency S=50MHz, then full parellel SCMA decoder architecture used by the present embodiment
Theoretical SCMA decoder handling capacity throughput are as follows:
Wherein, t is periodicity required for each iteration.
And in simulation process, sharing 1024 groups of data is decoded, and the entire process that decodes needed for about 11000 week
Phase, then decoding delay time are as follows:
Wherein, n is amount of cycles needed for decoding process.
Therefore the SCMA decoder handling capacity throughput ' of the present embodiment is obtained are as follows:
Wherein, totaldata indicates the quantity of data group to be decoded.
By above-mentioned calculated result it is found that the obtained SCMA decoder of full parellel SCMA decoder architecture of the present embodiment gulps down
The amount of spitting is almost the same with the calculated results, it was demonstrated that the full parellel SCMA decoder architecture of the present embodiment can effectively improve SCMA
The handling capacity of decoder.
Embodiment 2
The present embodiment proposes a kind of application method of full parellel SCMA decoder architecture, as shown in Fig. 2, for the present embodiment
The application method flow chart of full parellel SCMA decoder architecture, comprising the following steps:
Signal to be decoded is divided into several signal groups and sequentially inputs the residual error initialization module 1, at the beginning of completing residual error
The signal group of beginningization, which inputs in first processing unit, carries out signal group update processing, wherein the signal group for completing residual error initialization is defeated
Enter progress functional node update in the first functional node update module 2, and completes the signal group input register 4 of residual error initialization
In stored, then will complete functional node update signal group input variable node updates module 3 in carry out variable node
It updates；After first processing unit completes signal group update processing, processing unit will be completed to update the signal group handled and the signal
The residual error initialization result of group is transmitted in adjacent time processing unit and is handled, until signal group is transmitted to the last one
In processing unit and after completing processing, the signal group for updating processing and the residual error initialization result input second of the signal group are completed
Functional node update processing is carried out in functional node update module 5, and the signal group of output is then inputted into log-likelihood calculations
Log-likelihood calculations are carried out in module 6, final output obtains decoding result.
In the present embodiment, signal to be decoded includes receiving signal, channel condition, noise power, code book input signal, and believe
Number group is according to residual error initialization module 1, the first functional node update module 2, variable node update module 3, register 4, second
The preset clock cycle is inputted in functional node update module 5, logarithm likelihood ratio calculating module 6.
The application method of the full parellel SCMA decoder architecture of the present embodiment is applied to a kind of full parellel SCMA TLRF translator frame
Structure, wherein including 1,2 processing unit of residual error initialization module, the second functional node update module 5, log-likelihood calculations
Module 6, wherein processing unit includes the first functional node update module 2, variable node update module 3, register 4, and first
Functional node update module 2, the structure of the second functional node update module 5 are identical.
In processing unit, first input end of the input terminal of the first functional node update module 2 as processing unit is posted
Second input terminal of the input terminal of storage 4 as processing unit；The output end and variable node of first functional node update module 2
The input terminal of update module 3 connects, the output end of variable node update module 3 as processing unit the first output end with it is adjacent
Time processing unit first input end connection, the output end of register 4 as processing unit second output terminal with it is adjacent
Time processing unit the connection of the second input terminal.The input terminal of residual error initialization module 1 is as full parellel SCMA TLRF translator frame
First input end, the second input terminal of the input terminal of structure, the output end of residual error initialization module 1 and first processing unit connect
It connecing, the first output end of first processing unit is connect with the first input end for second processing unit being disposed adjacent, the
Two output ends are connect with the second input terminal of second processing unit being disposed adjacent, the first output of second processing unit
End, second output terminal are connect with the input terminal of the second functional node update module 5 respectively, the second functional node update module 5
Output end is connect with the input terminal of logarithm likelihood ratio calculating module 6, and the output end of logarithm likelihood ratio calculating module 6 is as full parellel
The output end of SCMA decoder architecture exports the decoding result for completing decoding processing.
In the present embodiment, the second functional node update module 2 in each processing unit and variable node update module 3
It needs to optimize respectively according to renewal process, reasonable flowing water is carried out by the multiply-add operation to each module, comparison operation
Change design, to meet the clock matches between each module.
In the specific implementation process, emulation experiment is carried out using the full parellel SCMA decoder architecture of the present embodiment, shared
1024 groups of data are decoded.Specifically, signal to be decoded is divided into several signal groups and to sequentially input the residual error initial
Change module 1, the signal group for completing residual error initialization, which inputs in first processing unit, carries out signal group update processing, wherein completing residual
The signal group of difference initialization inputs and carries out functional node update in the first functional node update module 2, and completes residual error initialization
Signal group input register 4 in stored, then will complete functional node update signal group input variable node updates
Variable node update is carried out in module 3；After first processing unit completes signal group update processing, first processing unit will be completed more
The residual error initialization result of the signal group and the signal group that newly handle is transmitted in second adjacent processing unit and is handled,
It repeats the above steps, second processing unit initializes the residual error of signal group and the signal group after completing signal group update processing
As a result progress functional node update processing in the second functional node update module 5 is inputted, then inputs log-likelihood calculations again
Log-likelihood calculations are carried out in module 6, final output obtains decoding result.
The same or similar label correspond to the same or similar components；
The terms describing the positional relationship in the drawings are only for illustration, should not be understood as the limitation to this patent；
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
Made any modifications, equivalent replacements, and improvements etc., should be included in the claims in the present invention within the spirit and principle of invention
Protection scope within.
Claims (6)
1. a kind of full parellel SCMA decoder architecture, it is characterised in that: be sequentially connected including residual error initialization module, at least two
By the first functional node update module, variable node update module, register group at processing unit, the second functional node more
New module, logarithm likelihood ratio calculating module；
Wherein, first input end of the input terminal of the first functional node update module as processing unit, register it is defeated
Enter second input terminal of the end as processing unit, the output end and variable node of the first functional node update module update mould
The input terminal of block connects, first output end and adjacent time of the output end of the variable node update module as processing unit
The first input end of a processing unit connects, the output end of the register as processing unit second output terminal with it is adjacent
Second input terminal of secondary a processing unit connects；The first of the output end of the residual error initialization module and first processing unit is defeated
Enter end, the connection of the second input terminal, the first output end of the last one processing unit, second output terminal respectively with the second functional node
The input terminal of update module connects, the output end of the second functional node update module and the input terminal of logarithm likelihood ratio calculating module
Connection, output end output decoding result of the output end of the logarithm likelihood ratio calculating module as the framework.
2. full parellel SCMA decoder architecture according to claim 1, it is characterised in that: the initialization residual error module,
First functional node module, the second functional node update module, variable node update module, register, log-likelihood calculations
Module works according to its preset clock cycle respectively.
3. full parellel SCMA decoder architecture according to claim 1, it is characterised in that: the quantity of the processing unit is
2~5.
4. a kind of application method of full parellel SCMA decoder architecture, which comprises the following steps: by signal to be decoded
It is divided into several signal groups and sequentially inputs the residual error initialization module, the signal group for completing residual error initialization inputs first place
It is handled in reason unit, wherein the signal group for completing residual error initialization inputs in the first functional node update module and carries out function
Node updates, and complete to be stored in the signal group input register that residual error initializes, then complete what functional node updated
Variable node update, i.e. the signal group update processing of completion processing unit are carried out in signal group input variable node updates module；
After first processing unit completes signal group update processing, processing unit transmits the residual error initialization result of signal group and signal group
It is handled into adjacent time processing unit, until signal group is transmitted in the last one processing unit and completes signal group
After update processing, the residual error initialization result of signal group and signal group, which inputs, carries out function section in the second functional node update module
Then point update processing will carry out log-likelihood calculations in the signal group input logarithm likelihood ratio calculating module of output, finally
Output obtains decoding result.
5. the application method of full parellel SCMA decoder architecture according to claim 4, it is characterised in that: the signal group
According to residual error initialization module, the first functional node update module, variable node update module, register, the second functional node
The preset clock cycle is inputted in update module, logarithm likelihood ratio calculating module.
6. the application method of full parellel SCMA decoder architecture according to claim 4, it is characterised in that: described to be decoded
Signal includes receiving signal, channel condition, noise power, code book input signal.
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