CN106301683B - A kind of DMPA interpretation method and decoder based on SCMA system - Google Patents
A kind of DMPA interpretation method and decoder based on SCMA system Download PDFInfo
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
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- H—ELECTRICITY
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- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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Abstract
The invention discloses a kind of DMPA interpretation method and decoder based on SCMA system, method includes initialization, resource node updates, node layer updates, 4 steps of probability calculation and symbol judgement；Decoder includes the initialization unit for initialization, the resource node updating unit for resource node update, for the node layer updating unit of node layer update and for the probability calculation unit of probability calculation and symbol judgement.The invention has the benefit that the property using MPA decoding principle low complex degree in Sparse System proposes DMPA algorithm, greatly reduce the decoding complexity of SCMA system, and the series optimization in timing and resource multiplex is made for the hardware structure of DMPA algorithm, obtain extremely simple low-complexity decoding device framework, so that in the range of processing speed allows, hardware consumption is greatly reduced, and improves hardware availability ratio.
Description
Technical field
It is especially a kind of based on the DMPA interpretation method of SCMA system and decoding the present invention relates to wireless communication technology field
Device.
Background technique
In recent years, quick surge state is presented in the extensive use with wireless communication technique in each field, social communication requirement
Gesture, conventional communication techniques are increasingly unable to satisfy social development needs.It is mobile according to the prediction of major carrier and authoritative advisory organization
Broadband services flow will increase as many as 1000 times in coming 10 years.To cope with upcoming huge communication pressure, 5G is as complete
New mobile communication technology comes into being.Wherein, " Gbps user experience rate " by be 5G most critical technical indicator.To realize
This ultrahigh speed transmission rate, 5G will apply to large-scale antenna array, novel multiple access, super-intensive networking, new network framework,
The important technologies such as entire spectrum access.And novel multiple access technology will play the part of in the entire system as one of 5G key technology realized
Drill vital role.Novel multiple access technology will carry out efficient superposed transmission so that the access capability of system obtains to transmission signal
It is promoted to further, to guarantee the large-scale equipment connection requirement of 5G network.
Backtracking multiple access technology experienced the evolution and change of long duration, in Modern wireless communication since generation
In have irreplaceable critical role.Traditional multiple access technology includes frequency division multiple access (FDMA), time division multiple acess (TDMA), code point
Multiple access (CDMA), space division multiple access (SDMA) etc., and used in 4G technology it is then orthogonal frequency division multiple access (OFDMA).There is this more
A little multiple access technologies are all the multiple access technology in orthogonal level, the very big limitation by resource quantity.In contrast, nonopiate more
In the technology of location, accessing user can then be greater than number of resources at double, thus the bottleneck that effectively solving.
Sparse Code Division Multiple Access (SCMA) is exactly 5G communication mid-term novel multiple access technology ready for use, and is had important
Nonopiate characteristic.Theoretical analysis shows that SCMA has extremely outstanding overload ability to bear and resource multiplex ability, with biography
System multiple access technology is compared, and access amount can at least promote 50%, and as internal system contact number of interconnection purpose increase can be into one
Step is promoted.In the pertinent literature about SCMA, the decoding policy based on maximum a posteriori probability is proposed for decoding, uses this
The SCMA system of decoding policy can still maintain preferably error rate level while guaranteeing high-level access amount, but in fact
There is high complexity on now.
Summary of the invention
Technical problem to be solved by the present invention lies in, a kind of DMPA interpretation method based on SCMA system is provided, it can be with
The decoding complexity that SCMA system can be greatly reduced, greatly reduces hardware consumption, improves hardware availability ratio.
In order to solve the above technical problems, the present invention provides a kind of DMPA interpretation method based on SCMA system, including as follows
Step:
(1) it initializes；If (K, N) SCMA system, SCMA code dimension is K, and constellation dimension is N, then the maximum of the system is used
The family number of plies isWherein, (K, N) SCMA system is (4,2), maximum number of user 6；
Here ykRepresent the kth position bit for receiving signal, xk,1,xk,2,xk,3It respectively represents and is connected with k-th of resource node
3 client layers, 3 bits overlapped on this node, N0,kWhat is indicated is in the corresponding environment of k-th of resource node
The power density of Gaussian noise；
(2) resource node updates；
Wherein, RkThat represent is k-th of resource node, m1,m2,m3=1 ..., M represents three to be connected with this resource node
The respective different transmitting symbol of a client layer；It represents from the client layer biography that those of is connected with resource node
The value of the confidence of the resource node is passed,It then represents and is transmitted from the resource node that those of is connected with client layer
It is a kind of opposite direction of transfer to the value of the confidence of the client layer；
(3) node layer updates；
Wherein, m=1 ..., M, which is represented, sends symbol different in glossary of symbols；After step (3), return step (2),
And thus constitute an iteration；The setting of the number of iterations is related to actual channel circumstance, when the number of iterations meets the receipts of the value of the confidence
After holding back condition, (4) are entered step by step (3)；The specific condition of convergence are as follows: according to target error rate level, given threshold a is (logical
It is standing to be set to a≤10-5)；If (n-1)th resource node updates the value of the confidence and node layer update the value of the confidence is respectivelyWithN-th is respectivelyWithIf all the value of the confidence meetWithThen it is judged to restraining, iteration terminates；The number of iterations at this time is n, for different channel rings
The numerical value of border n is different, and when channel circumstance is severe, the numerical value of n is often larger；
(4) probability calculation and symbol judgement；
Wherein, LjRepresent j-th of client layer；The symbol that each client layer has most probable value is picked out, is as finally estimated
The originally transmitted symbol counted out.
A kind of DMPA decoder based on SCMA system, including for initialization initialization unit, be used for resource node
The resource node updating unit of update, for node layer update node layer updating unit and be used for probability calculation and symbol judgement
Probability calculation unit；Initialization unit is connected with resource node more new node, and resource node updating unit and node layer update
Unit is connected, and node layer updating unit is connected with probability calculation unit；Decoder input is y, H and N0, exports and is
Preferably, original decoder is to carry out the update of data iteration in the form of " step ", refines, is obtained more to " step "
Small unit of account " stage " can jump into next " step " in the case where current " step " does not have been calculated all, make each
The hardware module of " step " is in the same time all in operating condition；After obtaining " stage grade " timing, carried out using folding
Optimization on resource multiplex.
Preferably, folding operation is carried out in each " step ", the folding process in " step " can be described as four mainly
Step: it determines folding set, seek folding equation, durability analysis and register distribution；In determining folding set step, advise first
The folding order and folding set number that definite decoding device is folded, then the initial data flow graph DFG according to each " step "
Label is grouped to arithmetic elements all kinds of in figure, label is being gathered into interior Rational Arrangement, is prolonged in DFG folding rear path with meeting
When non-negative requirement；It is seeking folding in equation step, then according to the delay number in folding set and the original path DFG, according to
It folds multiplexing formula and calculates the delay unit number after folded on each path DFG；In durability analysis step, according to folding set
With fold equation determine data input time and final the extinctions moment so that it is determined that out its in systems there are the times
Length by analyze minimum register number required for system and by Life Table and life diagram in a manner of shown；It is posting
In storage assigning process, reach the minimum register determined in previous step to-backward register allocation strategy using preceding
Number, the strategy first distribute to first unappropriated register when data are distributed nearby, and it is next each
Be sequentially allocated from the front to the back in clock cycle to next register followed by until reach the last one register or
Data have been withered away, the case where for reaching the last one register, data distribute to from the front to the back again first it is unoccupied
Register, and the latter register is distributed to from the front to the back again in next clock cycle, repeatedly, until all point
With completion.
The invention has the benefit that the property using MPA decoding principle low complex degree in Sparse System proposes DMPA
Algorithm greatly reduces the decoding complexity of SCMA system, and the hardware structure for being directed to DMPA algorithm makes timing and resource is multiple
With series optimization, obtain extremely simple low-complexity decoding device framework so that processing speed allow in the range of, pole
Hardware consumption is reduced greatly, and improves hardware availability ratio.
Detailed description of the invention
Fig. 1 is the performance curve of the bLock error rate of DMPA interpretation method of the present invention.
Fig. 2 is the performance curve of each layer bit error rate of DMPA interpretation method of the present invention.
Fig. 3 is the schematic diagram of original " step " level framework of DMPA of the present invention.
Fig. 4 is the timing diagram of original " step " level framework of DMPA of the present invention.
Fig. 5 is the timing diagram of DMPA of the present invention " stage " level framework.
Fig. 6 is the data flow diagram of DMPA step 1 part to be optimized of the present invention.
Fig. 7 is the life diagram of DMPA step 1 part to be optimized of the present invention.
Fig. 8 is the register assigning process schematic diagram of DMPA step 1 part to be optimized of the present invention.
Fig. 9 is the final low complex degree framework of DMPA of the present invention " stage " grade timing.
Specific embodiment
As illustrated in fig. 1 and 2, a kind of DMPA interpretation method based on SCMA system, includes the following steps:
(1) it initializes；If (K, N) SCMA system, SCMA code dimension is K, and constellation dimension is N, then the maximum of the system is used
The family number of plies isWherein, (K, N) SCMA system is (4,2), maximum number of user 6；
Here ykRepresent the kth position bit for receiving signal, xk,1,xk,2,xk,3It respectively represents and is connected with k-th of resource node
3 client layers, 3 bits overlapped on this node, N0,kWhat is indicated is in the corresponding environment of k-th of resource node
The power density of Gaussian noise；
(2) resource node updates；
Wherein, RkThat represent is k-th of resource node, m1,m2,m3=1 ..., M represents three to be connected with this resource node
The respective different transmitting symbol of a client layer；It represents from the client layer biography that those of is connected with resource node
The value of the confidence of the resource node is passed,It then represents and is transmitted from the resource node that those of is connected with client layer
It is a kind of opposite direction of transfer to the value of the confidence of the client layer；
(3) node layer updates；
Wherein, m=1 ..., M, which is represented, sends symbol different in glossary of symbols；After step (3), return step (2),
And thus constitute an iteration；The setting of the number of iterations is related to actual channel circumstance, when the number of iterations meets the value of the confidence
After the condition of convergence, (4) are entered step by step (3)；The specific condition of convergence are as follows: according to target error rate level, given threshold a
(it is usually arranged as a≤10-5)；If (n-1)th resource node updates the value of the confidence and node layer update the value of the confidence is respectively
WithN-th is respectivelyWithIf all the value of the confidence meetWithThen it is judged to restraining, iteration terminates；The number of iterations at this time is n, for different channel rings
The numerical value of border n is different, and when channel circumstance is severe, the numerical value of n is often larger；
(4) probability calculation and symbol judgement；
Wherein, LjRepresent j-th of client layer；The symbol that each client layer has most probable value is picked out, is as finally estimated
The originally transmitted symbol counted out.
In initialization step, the internal node internet based on SCMA, by such as ambient noise, channel conditions and
It receives the external informations such as signal and calculates initial required sign condition probability, mutually passed for the value of the confidence in following iterative decoding
Carry out preliminary preparation；It is updated in step in resource node, the form that resource node more new formula is expressed as and accumulates, to complete
To approaching of seeking of marginal probability and approximate；It is updated in step in node layer, is substantially carried out normalization operation, it will be in previous step
Calculated the value of the confidence is limited in section [0,1], to facilitate the realization of algorithm within hardware；Probability calculation and symbol judgement walk
In rapid, by the convergence the value of the confidence by obtaining after certain the number of iterations, reliable Soft Inform ation is exported, and calculate according to Soft Inform ation
The sending probability of each symbol of each client layer out is picked out each client layer and is finally estimated with the symbol conduct of most probable value
Originally transmitted symbol.
As shown in figure 3, basic decoder is obtained based on above-mentioned decoding process, including the initialization for initialization
Unit, for resource node update resource node updating unit, for node layer update node layer updating unit and be used for
The probability calculation unit of probability calculation and symbol judgement；Initialization unit is connected with resource node more new node, and resource node is more
New unit is connected with node layer updating unit, and node layer updating unit is connected with probability calculation unit；Decoder input be y, H and
N0, exports and isOriginal decoder is to carry out the update of data iteration in the form of " step ", and specific time diagram is as indicated at 4.
According to, the biggest problems are that when running current " step ", the hardware module of other " steps " is in such a way that " step " is unit
Idle state, so that the hardware availability ratio of whole system is not high.Then " step " is refined, it is single obtains smaller calculating
Position " stage ", to facilitate the introducing of deep pipeline in systems, i.e. in the case where current " step " does not have been calculated all
Next " step " can be jumped into, makes the hardware module of each " step " in the same time all in operating condition, after corresponding optimization
" stage " grade timing diagram is as shown in Figure 5.The calculating of each " step " has all been refined as smaller operation time slot, makes deep pipeline
It is interspersed to be possibly realized.
After obtaining " stage grade " timing, corresponding hardware structure is still extremely complex, further uses folding
Carry out the optimization on resource multiplex.Since whole structure is considerably complicated huge, it is difficult to carry out multiplex optimization from whole level, because
This carries out folding operation in each " step ", to become a kind of folding strategy of piecemeal, not only achieved the purpose that multiplexing but also
Greatly reduce design complexities.Folding process in " step " can be described as four key steps: determining folding set, seeks rolling over
Folded equation, durability analysis and register distribution.In determining folding set step, regulation decoder is folded first
Fold order and folding set number, then according to each " step " initial data flow graph (DFG) to arithmetic elements all kinds of in figure into
Label is being gathered interior Rational Arrangement, is folding the non-negative requirement that is delayed in rear path to meet DFG by row grouping label；It is seeking
It folds in equation step, then according to the delay number in folding set and the original path DFG, calculates folding according to multiplexing formula is folded
Delay unit number on each path poststack DFG；In durability analysis step, data are determined according to folding set and folding equation
Input time and final extinctions moment so that it is determined that out its in systems there are time spans to analyze needed for system
The minimum register number wanted simultaneously is shown by way of Life Table and life diagram；In register assigning process, utilize
The backward register allocation strategy of forward direction-come reach in previous step determine minimum register number, the strategy data divide
Timing first distributes to first unappropriated register nearby, and in each next clock cycle from the front to the back according to
Sub-distribution give followed by next register until reaching the last one register or data have been withered away, for reaching
The case where the last one register, data distribute to first unappropriated register again from the front to the back, and when next
The clock period distributes to the latter register from the front to the back again, repeatedly, until being all assigned.Pass through above folding
Technology carries out " step " interior folding to each " step " corresponding module, then final " stage " grade low complex degree framework can be obtained.
The interior piecemeal of " step " of DMPA " stage " grade timing low complex degree framework folds multiplexing will be with step 1 initialization step
Original architecture for be illustrated.The data flow diagram of step 1 part to be optimized is as shown in Figure 6.
Firstly, as shown in figure 4, share 2 input terminals in original architecture, 7 adders and 3 multipliers, then really
Determining folding set number is 3, and type is respectively input terminal folding set, adder folding set and multiplier folding set, and provides to roll over
Folded order is 7.Classification designator is carried out to each arithmetic element in the way of Fig. 4, same type of label is placed on same folding
It concentrates, and these labels is carried out with reasonable position arrangement in folding set to meet the delay after folded on each path DFG
Number is non-negative.Finally obtained folding set description are as follows:
Then, in conjunction with the delay number on each path in folding set and original DFG, each folding is sought using calculation formula is folded
Folded equation.Fold calculation formula are as follows:
DF(U → V)=Nw (e)-PU+v-u (9)
Wherein DF(U → V) is the delay number folded on rear path U → V, and N is to fold order, PUFor the assembly line of node U
Order, v and u are respectively the folding ordinal number that node U and V is concentrated in respective folded.Thus the portion to be optimized of the step of formula obtains one
The folding equation divided are as follows:
After obtaining folding set and folding equation, so that it may further carry out durability analysis to folding stand structure, determine each
The input times of data and wither away the moment to obtain data in systems there are the times.By to synchronization in system
It is that the statistics of " activation number " finds out the maximum number of simultaneous data there are data amount check, thus obtains and fold framework realization
Required minimum register number.According to this principle, obtains corresponding Life Table and life diagram has been shown in table 1 and Fig. 7,
And determine that minimum register number needed for framework is 8.
The Life Table of table 1.DMPA step 1 part to be optimized.
Finally, using it is preceding to-backward register allocation technique to reach the minimum register determined in above-mentioned steps
Number.In assigning process, data select first unappropriated register from front to back, and in the next clock cycle according to
Sub-distribution is to the latter register until reaching end register or data have been withered away, if register reaches end register
But the service life is still end, then the adjacent first unoccupied register of non-dispensing from the front to the back, and in next clock week
Phase distributes to next register from the front to the back again, and so on, until all data are assigned.According to this principle,
The register distribution schematic diagram of step 1 part to be optimized is as shown in Figure 8.
Final " step " the interior folding framework of step 1 can be obtained after completing above-mentioned steps, it can be to step according to same principle
Rapid two, three, four, which carry out corresponding fold, is multiplexed.After the folding operation for completing each " step ", DMPA shown in Fig. 9 has just been obtained
The low complex degree framework of " stage " grade timing.Therefore, the present invention greatlies simplify the complexity of SCMA system decoder, and makes hard
Part service efficiency is improved.
Although the present invention is illustrated and has been described with regard to preferred embodiment, it is understood by those skilled in the art that
Without departing from scope defined by the claims of the present invention, variations and modifications can be carried out to the present invention.
Claims (3)
1. a kind of DMPA interpretation method based on SCMA system, which comprises the steps of:
(1) it initializes；If (K, N) SCMA system, SCMA code dimension is K, and constellation dimension is N, then the maximum client layer of the system
Number isWherein, (K, N) SCMA system is (4,2), maximum number of user 6；
Here ykRepresent the kth position bit for receiving signal, xk,1,xk,2,xk,3Respectively represent 3 to be connected with k-th of resource node
Client layer 3 bits overlapped on this node, N0,kThat indicate is Gauss in the corresponding environment of k-th of resource node
The power density of noise；
(2) resource node updates；
Wherein, RkThat represent is k-th of resource node, m1,m2,m3=1 ..., M represents three use being connected with this resource node
The respective different transmitting symbol of family layer；It represents and is passed to from the client layer that those of is connected with resource node
The value of the confidence of the resource node,It then represents from the resource node that those of is connected with client layer and passes to this
The value of the confidence of client layer is a kind of opposite direction of transfer；
(3) node layer updates；
Wherein, m=1 ..., M, which is represented, sends symbol different in glossary of symbols；After step (3), return step (2), and by
This constitutes an iteration；The setting of the number of iterations is related to actual channel circumstance, when the number of iterations meets the convergence of the value of the confidence
After condition, (4) are entered step by step (3)；The specific condition of convergence are as follows: according to target error rate level, given threshold a is (logical
It is standing to be set to a≤10-5)；If (n-1)th resource node updates the value of the confidence and node layer update the value of the confidence is respectively
WithN-th is respectivelyWithIf all the value of the confidence meet
WithThen it is judged to restraining, iteration terminates；The number of iterations at this time is n, for different channels
The numerical value of environment n is different, and when channel circumstance is severe, the numerical value of n is often larger；
(4) probability calculation and symbol judgement；
Wherein, LjRepresent j-th of client layer；The symbol that each client layer has most probable value is picked out, is as finally estimated
Originally transmitted symbol.
2. a kind of DMPA decoder based on SCMA system characterized by comprising initialization unit, use for initialization
In the resource node updating unit of resource node update, for the node layer updating unit of node layer update and for probability calculation
With the probability calculation unit of symbol judgement；Initialization unit is connected with resource node more new node, resource node updating unit with
Node layer updating unit is connected, and node layer updating unit is connected with probability calculation unit；Decoder input is y, H and N0, output
ForDecoder is to carry out the update of data iteration in the form of " step ", refines to " step ", obtains smaller unit of account " rank
Section " can jump into next " step " in the case where current " step " does not have been calculated all, the hardware module of each " step " is made to exist
The same time is all in operating condition；After obtaining " stage grade " timing, the optimization on resource multiplex is carried out using folding.
3. as claimed in claim 2 based on the DMPA decoder of SCMA system, which is characterized in that by folding operation each
It is carried out in " step ", the folding process in " step " can be described as four key steps: determining folding set, seeks folding equation, longevity
Life analysis and register distribution；In determining folding set step, the folding order that is folded of regulation decoder first
And folding set number, then the initial data flow graph DFG according to each " step " is grouped label to arithmetic elements all kinds of in figure,
Label is being gathered into interior Rational Arrangement, is folding the non-negative requirement that is delayed in rear path to meet DFG；It is seeking folding equation step
In, then according to the delay number in folding set and the original path DFG, the folding road HouDFGGe is calculated according to multiplexing formula is folded
Delay unit number on diameter；In durability analysis step, according to folding set and fold equation determine the input time of data with
And final extinctions moment so that it is determined that out its in systems there are time spans to be posted with analyzing minimum required for system
Storage number is simultaneously shown by way of Life Table and life diagram；In register assigning process, using it is preceding to-it is backward
Register allocation strategy come reach in previous step determine minimum register number, the strategy data distribute when first nearby divide
First unappropriated register of dispensing, and be sequentially allocated from the front to the back in each next clock cycle to following closely
Thereafter next register is until reach the last one register or data have been withered away, for reaching the last one deposit
The case where device, data distribute to first unappropriated register from the front to the back again, and next clock cycle again by
The latter register is distributed to after forward direction, repeatedly, until being all assigned.
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| CN106911431B (en) * | 2017-03-13 | 2020-11-03 | 哈尔滨工业大学 | Improved partial edge information transmission method applied to demodulation process of sparse code multiple access system |
| CN107508657A (en) * | 2017-08-08 | 2017-12-22 | 重庆邮电大学 | A kind of SCMA multi-user test methods based on weight factor message transmission |
| CN107707329B (en) * | 2017-08-28 | 2020-07-28 | 中南民族大学 | Sparse code multiple access system and multi-user detection method thereof |
| CN107911197B (en) * | 2017-11-07 | 2020-10-16 | 东南大学 | Folding-based 5G communication system receiving end design method |
| CN108737298B (en) * | 2018-04-04 | 2021-01-26 | 东南大学 | SCMA blind detection method based on image processing |
| CN109586838B (en) * | 2018-11-22 | 2020-11-03 | 东南大学 | Efficient factor matrix design method for large-scale SCMA system and hardware architecture thereof |
| CN110417509B (en) * | 2019-06-05 | 2021-08-20 | 中山大学 | Fully-parallel SCMA decoder and use method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104798317A (en) * | 2012-11-16 | 2015-07-22 | 华为技术有限公司 | Systems and methods for sparse code multiple access |
| CN104823384A (en) * | 2012-12-14 | 2015-08-05 | 华为技术有限公司 | System and method for open-loop MIMO communications in SCMA communications system |
| CN105356971A (en) * | 2015-10-27 | 2016-02-24 | 电子科技大学 | SCMA decoder based on probability calculation |
| CN105554865A (en) * | 2015-11-09 | 2016-05-04 | 哈尔滨工业大学 | MIMO-SCMA system downlink design method based on STBC |
-
2016
- 2016-08-04 CN CN201610633758.8A patent/CN106301683B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104798317A (en) * | 2012-11-16 | 2015-07-22 | 华为技术有限公司 | Systems and methods for sparse code multiple access |
| CN104823384A (en) * | 2012-12-14 | 2015-08-05 | 华为技术有限公司 | System and method for open-loop MIMO communications in SCMA communications system |
| CN105356971A (en) * | 2015-10-27 | 2016-02-24 | 电子科技大学 | SCMA decoder based on probability calculation |
| CN105554865A (en) * | 2015-11-09 | 2016-05-04 | 哈尔滨工业大学 | MIMO-SCMA system downlink design method based on STBC |
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