CN110416222A - Three-dimensional storage and preparation method thereof, electronic equipment - Google Patents
Three-dimensional storage and preparation method thereof, electronic equipment Download PDFInfo
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- CN110416222A CN110416222A CN201910646253.9A CN201910646253A CN110416222A CN 110416222 A CN110416222 A CN 110416222A CN 201910646253 A CN201910646253 A CN 201910646253A CN 110416222 A CN110416222 A CN 110416222A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The embodiment of the present application provides a kind of three-dimensional storage part, including substrate, stacked structure and two gap structures, the stacked structure is located on the substrate, and two gap structures run through the stacked structure, two gap structure intervals and is oppositely arranged.The three-dimensional storage part has through array contact area and transition region, and array contact area and the institute's transition region of running through is between two gap structures, and the transition region is located at described run through between array contact area and the gap structure.Compared with the prior art, three-dimensional storage part described in the embodiment of the present application eliminates electric leakage hidden danger, has ensured the normal use of the three-dimensional storage part.The embodiment of the present application also provides the preparation method and electronic equipment of a kind of three-dimensional storage part.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of three-dimensional storage and preparation method thereof, electronic equipment.
Background technique
Three-dimensional (3Dimension, 3D) memory is that a kind of storage that storage unit is three-dimensionally disposed in substrate is set
It is standby, have many advantages, such as that integration density is high, memory capacity is big and low in energy consumption, to obtain widely answering in electronic product
With.
In the production process of current three-dimensional storage part, contact hole (Contact Hole, CH) and through array hinder
It is often formed under same technique every structure (Through Array Barrier, TAB), and due to contact hole and runs through battle array
The structure of column barrier structure is different, can have biggish error when being formed through array barrier structure, three-dimensional is caused to be deposited
Memory device generates the problems such as electric leakage, influences the normal use of three-dimensional storage part.
Summary of the invention
The present invention provides a kind of three-dimensional storage part and preparation method thereof and electronic equipment, for avoiding three-dimensional storage part
Electrical leakage problems, guarantee three-dimensional storage part normal use.
Herein described three-dimensional storage part includes substrate, stacked structure and two gap structures, the stacked structure position
In on the substrate, two gap structures run through the stacked structure, two gap structure intervals and are oppositely arranged,
The three-dimensional storage part, which has, runs through array contact area and transition region, described to be located at two through array contact area and institute's transition region
Between a gap structure, and the transition region is located at described run through between array contact area and the gap structure.
Wherein, the stacked structure includes the interlayer insulating film and dielectric layer being alternately stacked on the substrate, described
Dielectric layer includes isolated part and transition portion, and the isolated part is located at described in array contact area, the transition
Part is located in the transition region, and one end of the transition portion is connect with the isolated part, and the other end and the gap are tied
Structure connection, and the material of the part in the transition portion close to the isolated part is identical as the material of the isolated part,
The difference of the material of the material and isolated part of part in the transition portion far from the isolated part.
Wherein, the three-dimensional storage part has core space, and the core space is located at the gap structure far from the mistake
Cross the side in area.
Wherein, the three-dimensional storage part further includes the channel structure and virtual channel structure through the stacked structure,
The channel structure is located in the core space, and the virtual channel structure is located in the transition region, the virtual channel junction
Structure is identical as the radial dimension of the channel structure.
Wherein, it is directed toward on the direction of the core space along described through array contact area, virtual channel described at least 9 rows
Structural assignments are in the transition region.
Wherein, the dielectric layer further includes core, and the core is located at the transition portion far from described
The side of isolated part, the core are located in the core space, and the core passes through the gap structure and institute
State transition portion connection, and the material phase of the material of the core and the isolated part separate in the transition portion
Together.
Wherein, the channel structure includes the memory layer of the circumferential surface of stem and the encirclement stem, and the stem includes
Insulating layer and conductive plug, the insulating layer are located at the stem close to one end of the substrate, and the conductive plug is located at described exhausted
Surface of the edge layer far from the substrate, the virtual channel structure are identical with the structure of the channel structure.
Wherein, the three-dimensional storage part further includes through array contact structure, and the array contact structure that runs through is located at
It is described to run through in array contact area, and run through the stacked structure.
The preparation method of three-dimensional storage part described in the embodiment of the present application includes:
There is provided semiconductor structure, wherein the semiconductor structure includes substrate and the stack layer on the substrate, institute
Stating stack layer includes the interlayer insulating film being alternately stacked on the substrate and layer of dielectric material；
Form two gap openings for running through the stack layer, wherein two gap opening intervals and be oppositely arranged
With define the semiconductor structure through array contact area and transition region, it is described to run through array contact area and the transition region
Between two gap openings, and the transition region be located at the gap opening and it is described through array contact area it
Between；
The layer of dielectric material is converted into dielectric layer by the gap opening, the stack layer is converted in heaps
Stack structure.
Wherein, during in described " forming two gap openings for running through the stack layer ", two gaps are opened
Mouth also defines isolated part and the first medium part of the layer of dielectric material, and the isolated part is located at described through array
In contact zone, the first medium part is located in the transition region, one end and the isolation part of the first medium part
Divide connection, the other end is exposed in the gap opening；
It is described " layer of dielectric material to be converted by dielectric layer by the gap opening, the stack layer is turned
Change stacked structure into " during, the first medium part is converted by transition portion by the gap opening.
Wherein, during in described " forming two gap openings for running through the stack layer ", two gaps are opened
Mouth also defines the core space of the semiconductor structure, and the core space is located at one of the gap opening far from the transition region
Side.
Wherein, during in described " forming two gap openings for running through the stack layer ", two gaps are opened
Mouth also defines the second medium part of the layer of dielectric material, and it is remote that the second medium part is located at the first medium part
Side from the isolated part, and the second medium part is located in the core space, the second medium part is close
One end of the first medium part is exposed in the gap opening；
It is described " layer of dielectric material to be converted by dielectric layer by the gap opening, the stack layer is turned
Change stacked structure into " during, further includes: the second medium part is converted by core by the gap opening
Point.
Wherein, before described " forming two gap openings for running through the stack layer ", the preparation method further include: shape
At the channel structure and virtual channel structure for running through the stack layer, the radial direction of the channel structure and the virtual channel structure
Size is identical.
Wherein, described " layer of dielectric material to be converted by dielectric layer by the gap opening, by the stacking
Layer is converted into stacked structure " after, the preparation method further include: formed and run through array contact knot through the stacked structure
Structure, it is described to be located at described run through in array contact area through array contact hole.
Wherein, described " layer of dielectric material to be converted by dielectric layer by the gap opening, by the stacking
Layer is converted into stacked structure " after, the preparation method further include: form gap structure in the gap opening.
Herein described electronic equipment includes processor and any of the above-described kind of three-dimensional storage part, the processor be used for
Data are written in the three-dimensional storage part and read data.
Three-dimensional storage part described in the embodiment of the present application removes in the prior art through array barrier structure, simplifies
The structure of three-dimensional storage part does not need erosion while etch channels hole in the production preparation process of three-dimensional storage part
It carves and runs through array barrier structure, be not in etch incomplete problem through array barrier structure, avoid and be subsequently generated
The problem of three-dimensional storage part bottom is leaked electricity, has ensured the normal use of three-dimensional storage part.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the overlooking structure diagram of three-dimensional storage part in the prior art；
Fig. 2 is the schematic diagram of the section structure of three-dimensional storage part shown in Fig. 1 along the direction A-A；
Fig. 3 is a kind of overlooking structure diagram of three-dimensional storage part provided by the embodiments of the present application；
Fig. 4 is the schematic diagram of the section structure of three-dimensional storage part shown in Fig. 3 along the direction B-B；
Fig. 5 is the enlarged structure schematic diagram in the region the C of three-dimensional storage part shown in Fig. 4；
Fig. 6 is a kind of flow diagram of the preparation method of three-dimensional storage part provided by the embodiments of the present application；
Fig. 7-1 to Fig. 7-7 is the schematic diagram of the section structure of each technique in the preparation method of three-dimensional storage part shown in Fig. 6；
Fig. 8 is the structural schematic diagram of a kind of electronic equipment provided by the embodiments of the present application.
Specific embodiment
Below with reference to the Figure of description specific embodiment that the present invention will be described in more detail.Although being shown in attached drawing
Exemplary embodiments of the present invention, but it is to be understood that, can also using be different from other modes described herein come reality
The present invention is applied, therefore, the present invention is not limited by these following embodiments.
Before describing a specific embodiment of the invention, the first simple three-dimensional storage part introducing lower industry and generalling use
Structure.Also referring to Fig. 1 and Fig. 2, three-dimensional storage part 100 has substrate 110, stacked structure 120 in vertical direction
With multiple gap structures 130.Stacked structure 120 is located on substrate 110, and multiple gap structures 130 run through stacked structure 120, will
Three-dimensional storage part 100 is divided into multiple subpools 101.The battle array formed in each subpool 101 with channel hole 140
Column, virtual channel hole (Dummy Hole) 150,160 He of (Through Array Barrier, TAB) structure is obstructed through array
Through array contact (Through Array Contact, TAC) structure 170.In the preparation process of three-dimensional storage part 100,
It channel hole 140 and is formed under same etch process through array barrier structure 160, is hindered due to channel hole 130 and through array
Different every the shape and size of structure 160, easily generation channel hole 130 etches completely and loses through array barrier structure 160
Incomplete problem is carved, causes the three-dimensional storage part bottom being subsequently generated to be leaked electricity, influences the normal use of three-dimensional storage part.
In consideration of it, the embodiment of the present application provides a kind of three-dimensional storage part, it is above-mentioned through array barrier knot by removing
Structure and two gap structures simplify the structure of three-dimensional storage part, do not need to etch through array while etch channels hole
Barrier structure is not in that the etching of channel hole etches incomplete problem completely and through array barrier structure, avoids subsequent
The problem of three-dimensional storage part bottom electric leakage of generation, the normal use of three-dimensional storage part is ensured.
Also referring to Fig. 3 and Fig. 4, Fig. 3 is a kind of vertical view knot of three-dimensional storage part 200 provided by the embodiments of the present application
Structure schematic diagram, Fig. 4 are the schematic diagram of the section structure of three-dimensional storage part shown in Fig. 3 200 along the direction B-B.
Three-dimensional storage part shown in the embodiment of the present application 200 includes substrate 210, stacked structure 220 and two gap structures
230.Stacked structure 220 is located on substrate 210, and two gap structures 230 are between stacked structure 220, two gap structures 230
Every and be oppositely arranged.Three-dimensional storage part 200, which has, runs through array contact area 201 and transition region 202, runs through array contact area
201 and transition region 202 be located between two gap structures 230, transition region 202 is located to be tied through array contact area 201 and gap
Between structure 230.Wherein, two gap structures 230 extend along the y axis, and are intervally arranged along the x axis.
It is noted that being added to X, Y and Z axis in figs. 3 and 4 further to illustrate in three-dimensional storage part 200
Spatial relationship between each component.Substrate 210 includes two transverse directions being laterally extended in X-direction (transverse direction) and Y-direction
Surface (for example, top surface and bottom surface).As it is used herein, being located in three-dimensional storage part 200 in Z-direction in substrate
On most lower plane in when, judge a component (for example, layer or device) relative to substrate 210 in Z-direction (vertical direction)
Another component (for example, layer or device) "upper" of three-dimensional storage part 200, " top " still " lower section ".In the entire disclosure
Middle application is used to describe the identical mark of spatial relationship.In addition, Y-direction is directed toward in the paper of Fig. 2.
In the present embodiment, the material of substrate 210 is monocrystalline silicon (Si).Certainly, in other embodiments, the material of substrate can
Think elemental semiconductor such as germanium (Ge), compound semiconductor such as germanium (SiGe), silicon carbide (SiC), GaAs (GaAs), gallium phosphide
(GaP), indium phosphide (InP), indium arsenide (InAs) and/or indium antimonide (InSb), alloy semiconductor such as gallium arsenic (GaAsP),
Aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), Gallium indium arsenide (GaInAs), InGaP (GaInP) and/or gallium phosphide
The combination of indium arsenic (GaInAsP) or above each material.In addition, substrate 202 can be " semiconductor-on-insulator " wafer, such as absolutely
Silicon (SOI) or germanium on insulator (GOI) etc. on edge body can form three-dimensional storage part by techniques such as ion implantings in the substrate
The deep or shallow various potential wells of required p-type/n-type.
Stacked structure 220 is formed on the top surface of substrate 210.Stacked structure 220 includes being alternately stacked on substrate 210
Interlayer insulating film 221 and dielectric layer 222.Specifically, the vertically upper (figure of interlayer insulating film 221 and dielectric layer 222
Show Z-direction) it is alternately laminated.In the present embodiment, the material of interlayer insulating film 221 is silica (SixOy, such as SiO2), silicon nitride
(SixNy, such as SiN), nitridation oxygen silicon (SiON) or the above a variety of materials combination.Dielectric layer 222 and interlayer insulating film 221
Material is different, and dielectric layer 222 includes isolated part 2221 and transition portion 2222.Isolated part 2221 is located to be connect through array
It touches in area 201, the examples of materials of isolated part 2221 is silicon nitride.Transition portion 2222 is located in transition region 202, transition part
Points 2222 one end is connect with isolated part 2221, and the other end is connect with gap structure 230, and in transition portion 2222 it is close every
Part from part 2221 is identical as the material of isolated part 2221, part and isolated part 2221 far from isolated part 2221
Material it is different.Wherein, the material in transition portion 2222 close to the part of isolated part 2221 is silicon nitride, far from isolation part
2221 part is divided to be formed by conductive material replacement silicon nitride, i.e., transition portion 2222 is to replace silicon nitride by conductive material portion
It is formed.Wherein, conductive material be tungsten (W), cobalt (Co), copper (Cu), aluminium (Al), doped polycrystalline Si (polysilicon), doped single crystal Si,
Silicide or more than various conductive materials combination.
Gap structure 230 vertical (diagram Z-direction) extends through the interlayer insulating film being alternately stacked on substrate 210
221 and dielectric layer 222, and be connected to substrate 210.Gap structure 230 also extends along the y axis, and stacked structure 220 is drawn
It is divided into multiple pieces, as shown in Figure 3.Specifically, gap structure 230 includes the first conductor layer 231 and the second conductor layer 232.First
Conductor layer 231 is located at the bottom that gap structure 230 is located at gap structure 230 towards one end of substrate 210, i.e. the first conductor layer 231
Portion.Wherein, it is polysilicon that the material of the first conductor layer 231 is exemplary.It is remote that second conductor layer 232 is laminated in the first conductive layer 231
Surface from substrate 210, i.e. the second conductor layer 232 are located at the top of the first conductor layer 231 namely the second conductor layer 232 is located at
The top of gap structure 230, the examples of materials of the second conductor layer 232 are tungsten (W).Certainly, in other embodiments, second lead
The material of body layer 232 may be cobalt (Co), copper (Cu), aluminium (Al), doped polycrystalline Si (polysilicon), doped single crystal Si, silication
Object or more than various conductive materials combination.In some embodiments, gap structure 230, and grid gap (Gate Line can be claimed
Slit, GLS), contact public source (Array Common Source, ACS) of three-dimensional storage part 200 can be served as.
In the present embodiment, there are four gap structures 230, and the upper interval setting along the x axis of four gap structures 230 is located at
Two intermediate gap structures 230 define a miscellaneous function area 203, are located at through array contact area 201 and transition region 202 auxiliary
It helps in functional areas 203.Specifically, being located at the intermediate region in miscellaneous function area 203 through array contact area 201.Three-dimensional storage
Part 200 further includes being located at through array contact structure 240 through array contact structure 240 through stacked structure 220 and running through battle array
In column contact zone 201.It extends through and is alternately stacked on substrate 210 through array contact structure 240 vertical (diagram Z-direction)
Interlayer insulating film 221 and isolated part 2221, and be connected to substrate 210.It can be with shortening through array contact structure 240
Interconnection wiring transmission comes from and/or arrives the electric signal of three-dimensional storage part 200 (such as power bus part).Wherein, run through battle array
The material of column contact structures 240 include and be not limited to tungsten (W), cobalt (Co), copper (Cu), aluminium (Al), doped polycrystalline Si (polysilicon),
Doped single crystal Si, silicide or more than various conductive materials combination
Transition region 202 is located at miscellaneous function area 203 close to the region of gap structure 230.In the present embodiment, transition region 204
There are two, along perpendicular to (in diagram X-direction), two transition regions 204 are located at and pass through on the extending direction of gap structure 230
Wear the two sides in array contact area 201.Three-dimensional storage part 200 further includes the virtual channel structure 250 through stacked structure 220,
Virtual channel structure 250 is located in transition region 202.Specifically, virtual channel structure 250 vertical (diagram Z-direction) extends and passes through
The interlayer insulating film 221 and transition portion 2222 being alternately stacked on substrate 210 are worn, and is connect with substrate 210, to be deposited to three-dimensional
Memory device 200 provides mechanical support.Further, (scheme along on the direction that array contact area 201 is directed toward transition region 202
Show X-direction), the virtual channel structure 230 of 9 rows is intervally arranged in transition region 204.Certainly, in other embodiments, edge is run through
Array contact area is directed toward on the direction of transition region, and 13 rows or the virtual channel junction of other numbers of rows can also be placed in transition region
Structure, the application are not especially limited this.
Please refer to fig. 5, Fig. 5 is the enlarged structure schematic diagram in the region C in three-dimensional storage part shown in Fig. 4 200.
Virtual channel structure 250 includes stem 251, channel layer 253 and memory layer 252, stem 251,253 and of channel layer
Memory layer 252 is successively arranged along the center of virtual channel structure 250 to the direction of its outer peripheral surface.Stem 251 includes along vertical
Direction stacks the insulating layer 2511 and conductive plug 2512 of setting, and the material of insulating layer 251 is silica (SixOy, such as SiO2), nitrogen
SiClx (SixNy, such as SiN), nitridation oxygen silicon (SiON) or the above a variety of materials combination.Conductive plug 252 is made of polysilicon.This
Outside, in other embodiments, the injection of p class Doped ions can also be carried out to conductive plug 252 made of polysilicon, led with reducing
The threshold voltage of electricity plug 252 is also convenient for the threshold voltage of control top selection gate convenient for the Ohmic contact of itself and metal routing
(Vt), consistency is more preferable.Channel layer 253 is arranged around the circumferential surface of stem 251, and the material of channel layer 253 includes and is not limited to more
The semiconductor materials such as crystal silicon, monocrystalline silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C or SiGe:H.Memory layer 252 is located at channel layer
Between 253 and stacked structure 220, by the perimeter conductive in the channel layer 253 of virtual channel structure 250 and stacked structure 220
Layer insulation.Memory layer 252 includes barrier insulating layer 2521, electric charge capture layer 2522 and tunneling insulation layer 2523, stops insulation
Layer 2521, electric charge capture layer 2522 and tunneling insulation layer 2523 are successively arranged from outside to inside.Barrier insulating layer 2521 and tunnelling are exhausted
The examples of materials of edge layer 2523 is silica, and the examples of materials of electric charge capture layer 2522 is silicon nitride, forms silica-nitrogen
SiClx-silica (O-N-O) structure.Certainly, virtual channel structure 250 further includes epitaxial layer 254, and epitaxial layer 254 is located at virtual
Channel structure 250 is close to the side of substrate 210, i.e. the bottom that is located at virtual channel structure 250 of epitaxial layer 254, stem 251, ditch
Channel layer 252 and memory layer 252 are located at surface of the epitaxial layer 254 far from substrate, and epitaxial layer 254 is connected to channel layer 252.It needs
It is noted that in other embodiments, channel structure can not also include epitaxial layer, be directly connected to substrate using channel layer
.
Further, three-dimensional storage part 200 has core space 204, and core space 204 is located at gap structure 230 far from mistake
Cross the side in area 202.Specifically, core space 204 is located at outside miscellaneous function area 203.In the present embodiment, there are two core spaces 204,
The gap structure 230 of gap structure 230 and a centre on the outside of one defines a core space 204, i.e., along perpendicular to gap
On the extending direction of structure 230 (in diagram X-direction), two core spaces 204 are located at the two sides in miscellaneous function area 203,
I.e. each core space 204 is connect by a gap structure 230 with miscellaneous function area 203.
The dielectric layer 222 of stacked structure 220 further includes core 2223, and core 2223 is located at transition portion
2222 sides far from isolated part 2221, core 2223 are located in core space 204, and core 2223 is tied by gap
Structure 230 is connect with transition portion 2222, the material phase of core 2223 and isolated part 2221 separate in transition portion 2222
Together.Wherein, by being formed using conductive material replacement silicon nitride, conductive material is tungsten (W), cobalt (Co), copper for core 2223
(Cu), aluminium (Al), doped polycrystalline Si (polysilicon), doped single crystal Si, silicide or more than various conductive materials combination.
Three-dimensional storage part 200 further includes the channel structure (also known as NAND string) 260 through stacked structure 220, channel junction
Structure 260 is located in core space 204, and the radial dimension of channel structure 260 is identical as the radial dimension of virtual channel structure 250.
Specifically, channel structure 260 vertical (diagram Z-direction) extends through the interlayer insulating film 221 being alternately stacked on substrate 210
With core 2223, and it is connect with substrate 210.Wherein, core 2223 potentially acts as the storage list in channel structure 260
The control grid of member.
Channel structure 260 is identical as the structure of virtual channel structure 250.Channel structure 260 includes stem, channel layer and deposits
Reservoir layer, stem, channel layer and memory layer are successively arranged along the center of channel structure 260 to the direction of its outer peripheral surface.Stem
Insulating layer and conductive plug including vertically stacking setting, the material of insulating layer are silica (SixOy, such as SiO2), nitridation
Silicon (SixNy, such as SiN), nitridation oxygen silicon (SiON) or the above a variety of materials combination.Conductive plug is made of polysilicon.In addition, In
In other embodiments, the injection of p class Doped ions can also be carried out, to conductive plug made of polysilicon to reduce the threshold of conductive plug
Threshold voltage is also convenient for the threshold voltage (Vt) of control top selection gate, consistency convenient for the Ohmic contact of itself and metal routing
More preferably.Channel layer around stem circumferential surface be arranged, the material of channel layer include and be not limited to polysilicon, monocrystalline silicon, monocrystalline germanium,
The semiconductor materials such as SiGe, Si:C, SiGe:C or SiGe:H.Memory layer, will between channel layer and stacked structure 220
The channel layer of channel structure 260 and the perimeter conductive layer in stacked structure 220 insulate.Memory layer includes barrier insulating layer, electricity
Lotus capture layer and tunneling insulation layer, barrier insulating layer, electric charge capture layer and tunneling insulation layer are successively arranged from outside to inside.Stop exhausted
Edge layer and the examples of materials of tunneling insulation layer are silica, and the examples of materials of electric charge capture layer is silicon nitride, form oxidation
Silicon-silicon-nitride and silicon oxide (O-N-O) structure.Certainly, channel structure 260 further includes epitaxial layer, and epitaxial layer is located at channel structure
260 close to the side of substrate 210, i.e. the epitaxial layer bottom that is located at channel structure 260, and stem, channel layer and memory layer are located at
Surface of the epitaxial layer far from substrate, and epitaxial layer is connected to channel layer.It should be noted that in other embodiments, channel junction
Structure can not also include epitaxial layer, be directly connected to substrate using channel layer.
Three-dimensional storage part compared with the prior art, three-dimensional storage part 200 provided by the embodiments of the present application remove
The structure for simplifying three-dimensional storage part 200 through array barrier structure and two gap structures, in three-dimensional storage part 200
In preparation process, do not need to etch to be formed through array barrier structure while etch channels hole, avoid because of channel hole and
Occur etching incomplete problem through array barrier structure because of size difference through array barrier structure, relieve because running through
The incomplete and hidden danger there are bottom electric leakage of array barrier structure etching, has ensured the three-dimensional storage part that final production comes out
Normal use.
Referring to Fig. 6, the embodiment of the present application also provides a kind of preparation method of three-dimensional storage part, comprising:
Step S1 provides semiconductor structure 200a referring to Fig. 7-1, and semiconductor structure 200a includes substrate 210 and is located at lining
Stack layer 220a on bottom 210, stack layer 220a include the interlayer insulating film 221 and medium material being alternately stacked on substrate 210
Bed of material 222a.Wherein, step S1 can be realized by following step S11 to step S13.
Step S11 provides substrate 210.Wherein, the material of substrate 210 is monocrystalline silicon (Si).Certainly, in other embodiments
In, the material of substrate can be elemental semiconductor such as germanium (Ge), compound semiconductor such as germanium (SiGe), silicon carbide (SiC), arsenic
Gallium (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/or indium antimonide (InSb), alloy semiconductor such as phosphorus
Change gallium arsenic (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), Gallium indium arsenide (GaInAs), InGaP
(GaInP) and/or the combination of InGaP arsenic (GaInAsP) or above each material.In addition, substrate 202 can be " on insulator
Semiconductor " wafer, such as silicon-on-insulator (SOI) or germanium on insulator (GOI) etc., can pass through the works such as ion implanting in the substrate
The deep or shallow various potential wells of p-type/n-type needed for skill forms three-dimensional storage part.
Step S12 forms stack layer 220a on substrate 210, obtains semiconductor structure 200b referring to Fig. 7-2.Specifically
, interlayer insulating film 221 and layer of dielectric material 222a can use chemical vapor deposition (Chemical Vapor
Deposition, CVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor
Deposition, PECVD), physical vapour deposition (PVD) (Physical Vapor Deposition, PVD), atomic layer deposition
(Atomic Layer Deposition, ALD), plasma enhanced atomic layer deposition (Plasma Enhanced Atomic
Layer Deposition, PEALD) or other suitable membrane deposition methods, it is successively alternately heavy on the top surface of substrate 210
Product is formed.Wherein, the material of interlayer insulating film 221 is silica (SixOy, such as SiO2), silicon nitride (SixNy, such as SiN), nitridation
The combination of oxygen silicon (SiON) or the above a variety of materials, the material of layer of dielectric material 222a be silicon nitride, unformed silicon, polysilicon or
The materials such as aluminium oxide.Using O/N, (for silica as interlayer insulating film 221, silicon nitride is as Jie in stack layer 220a in the present embodiment
Material bed of material 222a) illustrate subsequent technique process for lamination.
Step S13 forms the channel structure 260 and virtual channel structure 250 for running through stack layer 220a.Wherein, channel junction
Structure 260 and virtual channel structure 250 extend vertically through stack layer 220a.
In the present embodiment, step S13 can be realized by following step S131 to step S132.
Step S131 forms the channel hole 224 and virtual channel hole 225 for running through stack layer 220a, obtains referring to Fig. 7-3
Semiconductor structure 200c.Wherein, channel hole 224 is identical with the radial dimension in virtual channel hole 225.Specifically, using etching work
Skill etch stack layer 220a is formed simultaneously through stack layer 220a and exposes the channel hole 224 and virtual channel hole of substrate 210
225。
Compared to the preparation process flow of the three-dimensional storage part of current industry, channel hole 224 and virtual in the present embodiment
The radial dimension in channel hole 225 is identical, during forming channel hole 224 and virtual channel hole 225 at the same time, is avoided that because of void
Quasi- channel hole is different from the radial dimension in channel hole and causes virtual channel hole that can not etch complete problem, is conducive to improve life
Produce precision.
Step S132 is respectively formed 260 He of channel structure in channel hole 224 and virtual channel hole 225 referring to Fig. 7-1
Virtual channel structure 250, obtains semiconductor structure 200a.Wherein, step 132 can pass through following step S1321 to step
S1327 is realized.
Step S1321 forms epitaxial layer towards one end of substrate 210 in channel hole 224 and virtual channel hole 225.Specifically
, the epitaxial layer being connected to substrate 210 is formed in the bottom in channel hole 224 and virtual channel hole 225.Wherein, epitaxial layer shows
Example property material is silicon, but not limited to this, it can deposit and to be formed by using CVD, ALD or other suitable deposition methods.
Step S1322 forms memory layer in channel hole 224 and virtual channel hole 225.Specifically, in channel hole 224
Barrier insulating layer, electric charge capture layer and tunnel insulating layer are sequentially formed on the hole wall in virtual channel hole 225, to form memory
Layer.Wherein, the examples of materials of barrier insulating layer and tunneling insulation layer is silica, and the examples of materials of electric charge capture layer is nitrogen
SiClx, this three layers can deposit and be formed by using CVD, ALD or other suitable deposition methods, so that memory layer is formed
Oxide-nitride-oxide (O-N-O) structure.
Step S1323 forms channel layer on the surface of memory layer.Wherein, channel layer is connected to epitaxial layer.Specifically,
Channel layer is formed away from the surface of electric charge capture layer in tunneling insulation layer.Wherein, the material of channel layer includes and is not limited to polycrystalline
The semiconductor materials such as silicon, monocrystalline silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C or SiGe:H, can by using CVD, ALD or its
He deposits to be formed suitable deposition method.
Step S1324, etching is located at channel layer and memory layer above epitaxial layer, to expose epitaxial layer.
Step S1325 forms insulation material layer in channel hole 224 and virtual channel hole 225.Specifically, using ALD work
Skill fill insulant in channel hole 224 and virtual channel hole 225, to be formed in channel hole 224 and virtual channel hole 225
Insulation material layer.Wherein, insulating materials is illustratively silica.
Step S1326 etches insulation material layer, forms the insulating layer of stem and the groove at the top of stem.Specifically,
Insulation material layer is etched to expose channel layer, so that there is no insulating materials residual on the cell wall of groove, to guarantee to be subsequently formed to lead
The side of electricity plug can be bonded completely with channel layer.
Step S1327, forms conductive plug in groove.Specifically, conductive material is deposited by way of ALD or CVD
In groove 202c, to form the conductive plug of stem.Wherein, conductive material is polysilicon, and the periphery and channel layer of conductive plug 260
241 fittings completely, to guarantee that three-dimensional storage part has preferable electric property.In addition, can also to the polysilicon plug of formation into
The injection of row p class Doped ions, to reduce the threshold voltage of conductive plug, convenient for the Ohmic contact of itself and metal routing, is also convenient for controlling
The threshold voltage (Vt) of system top selection gate, consistency is more preferable.
Step S2 forms two gap openings 223 for running through stack layer 220a, obtains semiconductor structure referring to Fig. 7-4
200d.Wherein, two gap openings 223 interval and be oppositely arranged with define semiconductor structure 200d through array contact area
201 and transition region 202, it is located between two gap openings 223 through array contact area 201 and transition region 202, transition region 202
Positioned at through between array contact area 201 and gap opening 223.
In this step, gap opening 223 is through stack layer 220a and exposes substrate 210, and two gap openings 223 define auxiliary
Functional areas 203 are helped, are located in miscellaneous function area 203 through array contact area 201 and transition region 202.Through array contact area 201
Positioned at the intermediate region in miscellaneous function area 203, transition region 202 is located at miscellaneous function area 203 close to the region of gap opening 223.
Specifically, (being illustrated in X-direction) along perpendicular on the extending direction of gap opening 223, two mistakes there are two transition regions 202
It crosses area 202 and is located at the two sides through array contact area 201.Two gap openings 223 define layer of dielectric material 222a's
Isolated part 222b and first medium part 222c, isolated part 222b are located in array contact area 201, first medium portion
222b is divided to be located in transition region 202, one end of first medium part 222c is connect with isolated part 222b, the end face structure of the other end
At the partial sidewall of gap opening 223, in order to replace in the 222b of first medium part subsequently through gap opening 223 close to seam
The part of gap opening 223.
Two gap openings 223 also define the core space 204 of semiconductor structure 200b, and core space 204 is opened positioned at gap
223 sides far from transition region 202 of mouth.Specifically, core space 204 is located at outside miscellaneous function area 203.In the present embodiment, core
There are two areas 204, along perpendicular to (in diagram X-direction), two core spaces 204 are distinguished on the extending direction of gap opening 223
Positioned at the two sides in miscellaneous function area 203.Two gap openings 223 also define the second medium part of layer of dielectric material 222a
222c, second medium part 222c are located at side of the first medium part 222c far from isolated part 222b, second medium part
222a3 is located in core space 204, and second medium part 222c constitutes gap close to the end face of one end of first medium part 222c
The partial sidewall of opening 223, in order to replace second medium part 222c subsequently through gap opening 223.
Step S3 please refers to Fig. 7-5, and layer of dielectric material 222a is converted into dielectric layer 222 by gap opening 223,
Stack layer 220a is converted into stacked structure 220, semiconductor structure 200e is obtained.Specifically, passing through seam using conductive material
Part and second medium part 222c of the 223 replacement first medium part 222b of gap opening close to gap opening 223, first is situated between
Matter part 222b and second medium part 222c are converted into transition portion 2222 and core 2223 respectively, by dielectric material
Layer 222a is converted into dielectric layer 225.It should be noted that due to first medium part 222c and second medium part 222a3
It is relatively close apart from gap opening 223 positioned at the two sides of gap opening 223, and isolated part 222b apart from gap opening 223 farther out,
Therefore only first medium part 222b is replaced close to the part of gap opening 223 and second medium part 222c by conductive material
It changes, and isolated part 2221 is not replaced, runs through array contact area 201 to define.
In this step, it can be used and 221 (such as SiO of interlayer insulating film2) have compared to layer of dielectric material 222a (such as SiN)
There is the wet-etching technology of high selectivity to realize and replaces layer of dielectric material 222a using conductive material portion.Such as it rather than limits
System, wet etching chemical reagent may include hot phosphoric acid (H3PO4).Since wet etching chemical reagent is high selectivity to SiN
, by oxide (such as SiO2) made of any layer or structure (such as interlayer insulating film 221) will not be etched or remove, i.e.,
Any layer or structure made of oxide will not all be influenced by wet-etching technology.
After the part layer of dielectric material 222a near gap opening 223 is completely removed, so that it may by CVD,
PECVD, ALD, PEALD or combinations thereof deposited conductor material, by between 223 filled media material layer 222a of gap opening
Space, to form dielectric layer 222, as shown in Fig. 7-5.Wherein, conductor material may include W, Co, Cu, Al, polysilicon,
Silicide or combinations thereof.
In the present embodiment, the preparation method further includes step S4 to step S6.
Step S4 please refers to Fig. 7-6, forms gap structure 230 in gap opening 223, obtains semiconductor structure 200f.
Specifically, sequentially forming the first conductor layer 231 and the second conductor layer 322 in gap opening 223.Wherein, the first conductor layer 231
Examples of materials be polysilicon, the examples of materials of the second conductor layer 222 is tungsten (W).Certainly, in other embodiments,
The material of two conductor layers 222 may be cobalt (Co), copper (Cu), aluminium (Al), doped polycrystalline Si (polysilicon), doped single crystal Si,
Silicide or more than various conductive materials combination.
Step S5 please refers to Fig. 7-7, runs through array through stacked structure 226 being formed in array contact area 201
Contact hole 227 obtains semiconductor structure 200g.Specifically, being formed simultaneously using etch process etch stack layer 220a through heap
Lamination 220a and expose substrate 210 run through array contact hole 227.
Step S6 obtains three referring to Fig. 4, running through array contact structure 360 being formed in array contact hole 227
Tie up memory device 200.Wherein, the material through array contact structure 240 include and be not limited to tungsten (W), cobalt (Co), copper (Cu),
Aluminium (Al), doped polycrystalline Si (polysilicon), doped single crystal Si, silicide or more than various conductive materials combination.
It has been described, has been not discussed herein above as the effect of the preparation method of the three-dimensional storage part.
Referring to Fig. 8, Fig. 8 is the structural schematic diagram of a kind of electronic equipment 300 provided by the embodiments of the present application.
Electronic equipment 300 shown in the embodiment of the present application includes processor 310 and any of the above-described kind of three-dimensional storage part 200,
Processor 310 is used to that data to be written into three-dimensional storage part 200 and reads data.
It has hereinbefore been described, has been not discussed herein as the effect of the electronic equipment.
The above is exemplary embodiments of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the principle of the present invention, several improvements and modifications, these improvements and modifications can also be made to it
Also it is considered as protection scope of the present invention.
Claims (16)
1. a kind of three-dimensional storage part, which is characterized in that the three-dimensional storage part includes substrate, stacked structure and two
Gap structure, the stacked structure are located on the substrate, and two gap structures run through the stacked structure, described in two
It gap structure interval and is oppositely arranged, the three-dimensional storage part, which has, runs through array contact area and transition region, described to run through battle array
Column contact zone and institute's transition region are located between two gap structures, and the transition region runs through array contact area positioned at described
Between the gap structure.
2. three-dimensional storage part according to claim 1, which is characterized in that the stacked structure includes being alternately stacked in institute
The interlayer insulating film and dielectric layer on substrate are stated, the dielectric layer includes isolated part and transition portion, the isolation part
In described in the array contact area, the transition portion is located in the transition region quartile, one end of the transition portion and
The isolated part connection, the other end are connect with the gap structure, and close with the isolated part in the transition portion
Part material it is identical as the material of the isolated part, the material of the part separate with the isolated part is isolated with described
The difference of partial material.
3. three-dimensional storage part according to claim 2, which is characterized in that the three-dimensional storage part has core space,
The core space is located at side of the gap structure far from the transition region.
4. three-dimensional storage part according to claim 3, which is characterized in that the three-dimensional storage part further includes through institute
The channel structure and virtual channel structure of stacked structure are stated, the channel structure is located in the core space, the virtual channel
Structure is located in the transition region, and the virtual channel structure is identical as the radial dimension of the channel structure.
5. three-dimensional storage part according to claim 4, which is characterized in that along described through described in array contact area direction
On the direction of core space, virtual channel structure described at least 9 rows is arranged in the transition region.
6. three-dimensional storage part according to claim 3, which is characterized in that the dielectric layer further includes core,
The core is located at side of the transition portion far from the isolated part, and the core is located at the core space
Interior, the core is connect by the gap structure with the transition portion, and the material of the core with it is described
Material in transition portion far from the isolated part is identical.
7. three-dimensional storage part according to claim 5, which is characterized in that the channel structure includes stem and encirclement institute
The memory layer of the circumferential surface of stem is stated, the stem includes insulating layer and conductive plug, and it is close that the insulating layer is located at the stem
One end of the substrate, the conductive plug are located at surface of the insulating layer far from the substrate, the virtual channel structure and
The structure of the channel structure is identical.
8. three-dimensional storage part according to claim 1-7, which is characterized in that the three-dimensional storage part also wraps
It includes through array contact structure, the array contact structure that runs through runs through in array contact area positioned at described, and runs through the heap
Stack structure.
9. a kind of preparation method of three-dimensional storage part characterized by comprising
There is provided semiconductor structure, wherein the semiconductor structure includes substrate and the stack layer on the substrate, the heap
Lamination includes the interlayer insulating film being alternately stacked on the substrate and layer of dielectric material；
Form two gap openings for running through the stack layer, wherein two gap opening intervals and be oppositely arranged with boundary
Make the semiconductor structure through array contact area and transition region, it is described to be located at through array contact area and the transition region
Between two gap openings, and the transition region is located at the gap opening and described between the array contact area；
The layer of dielectric material is converted into dielectric layer by the gap opening, the stack layer is converted into stack knot
Structure.
10. the preparation method of three-dimensional storage part according to claim 9, which is characterized in that described " to be formed through described
During in two gap openings of stack layer ", two gap openings also define the isolation of the layer of dielectric material
Part and first medium part, positioned at described in array contact area, the first medium part is located at the isolated part
In the transition region, one end of the first medium part is connect with the isolated part, and the end face of the other end constitutes the seam
The partial sidewall of gap opening；
It is described " layer of dielectric material to be converted by dielectric layer by the gap opening, the stack layer is converted into
During stacked structure ", the first medium part is converted by transition portion by the gap opening.
11. the preparation method of three-dimensional storage part according to claim 10, which is characterized in that described " to be formed and run through institute
State two gap openings of stack layer " in during, two gap openings also define the core of the semiconductor structure
Heart district, the core space are located at side of the gap opening far from the transition region.
12. the preparation method of three-dimensional storage part according to claim 11, which is characterized in that described " to be formed and run through institute
State two gap openings of stack layer " in during, two gap openings also define the of the layer of dielectric material
Second medium part, the second medium part are located at the first medium partially away from the side of the isolated part, and described
Second medium part is located in the core space, one end end face structure of the second medium part close to the first medium part
At the partial sidewall of the gap opening；
It is described " layer of dielectric material to be converted by dielectric layer by the gap opening, the stack layer is converted into
During stacked structure ", further includes: the second medium part is converted into core by the gap opening.
13. the preparation method of three-dimensional storage part according to claim 9, which is characterized in that described " to be formed through described
Before two gap openings of stack layer ", the preparation method further include: form the channel structure and void for running through the stack layer
Quasi- channel structure, the channel structure are identical with the radial dimension of the virtual channel structure.
14. the preparation method of three-dimensional storage part according to claim 9, which is characterized in that described " to pass through the gap
The layer of dielectric material is converted into dielectric layer by opening, and the stack layer is converted into stacked structure " after, the preparation
Method further include: formed and run through array contact structure through the stacked structure, the array contact hole of running through is positioned at described
In array contact area.
15. the preparation method of three-dimensional storage part according to claim 9, which is characterized in that described " to pass through the gap
The layer of dielectric material is converted into dielectric layer by opening, and the stack layer is converted into stacked structure " after, the preparation
Method further include: form gap structure in the gap opening.
16. a kind of electronic equipment, which is characterized in that including processor and such as the described in any item three-dimensional storages of claim 1-8
Device, the processor are used to that data to be written into the three-dimensional storage part and read data.
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