CN110401425B - Automatic gain adjuster and automatic gain adjusting circuit - Google Patents
Automatic gain adjuster and automatic gain adjusting circuit Download PDFInfo
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- CN110401425B CN110401425B CN201910650024.4A CN201910650024A CN110401425B CN 110401425 B CN110401425 B CN 110401425B CN 201910650024 A CN201910650024 A CN 201910650024A CN 110401425 B CN110401425 B CN 110401425B
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- G—PHYSICS
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- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C23/00—Non-electrical signal transmission systems, e.g. optical systems
- G08C23/04—Non-electrical signal transmission systems, e.g. optical systems using light waves, e.g. infrared
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Abstract
The invention provides an automatic gain adjuster, which comprises a noise integrator, an interval time detector, a holding time timer, an RS trigger, a control logic circuit and a gain control integrator, wherein the noise integrator is used for detecting the interval time of the noise integrator; the output end of the noise integrator is respectively connected to the input end of the interval time detector, the first input end of the holding time timer and the control logic circuit; the interval time detector is respectively connected to the RS trigger and the holding time timer; the output end of the holding time timer is respectively connected to the RS trigger and the control logic circuit; the RS trigger is respectively connected to the holding time timer and the control logic circuit; the control logic circuit is connected to the gain control integrator, and the control logic circuit is connected to the gain control integrator. Compared with the related art, the automatic gain adjuster can effectively distinguish noise and signals in the infrared signal with short interval time and long total coding time, and the automatic gain circuit has high decoding accuracy on the infrared signal.
Description
[ Field of technology ]
The invention relates to the field of infrared remote control, in particular to an automatic gain adjuster and an automatic gain adjusting circuit applied to an infrared receiver.
[ Background Art ]
With the continuous development of remote controllers, infrared receivers are widely used. The infrared receiver is provided with an automatic gain adjustment circuit, and the structural design of the automatic gain adjustment circuit directly influences the function implementation of the infrared receiver. Therefore, in order to improve the performance of the infrared receiver, an optimal design of the automatic gain adjustment circuit is required.
In the related art, the automatic gain adjustment circuit includes a diode, a current/voltage conversion circuit, a preamplifier, a gain variable amplifier, a band-pass filter, a comparator, a demodulation integrator, a shaping output circuit, and an automatic gain adjuster. The output end of the diode is connected with the input end of the current/voltage conversion circuit, the output end of the current/voltage conversion circuit is connected with the input end of the pre-amplifier, the output end of the pre-amplifier is connected with the input end of the gain variable amplifier, the output end of the gain variable amplifier is connected with the input end of the gain suppressor, the output end of the gain suppressor is connected with the input end of the band-pass filter, the output end of the band-pass filter is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the automatic gain adjuster and the demodulation integrator, the output end of the automatic gain adjuster is connected with the gain variable amplifier, and the output end of the demodulation integrator is connected with the input end of the shaping output circuit.
However, the automatic gain adjuster in the related art recognizes the signal as noise when receiving the ir-encoded signal with a small interval time and a long total encoding length, and then continuously reduces the gain of the gain variable amplifier, so that the ir receiver cannot receive the complete ir-encoded signal.
Therefore, it is necessary to provide an automatic gain adjuster and an automatic gain adjusting circuit for solving the above-mentioned problems.
[ Invention ]
The invention aims to provide an automatic gain adjuster and an automatic gain adjusting circuit, wherein the automatic gain adjuster effectively distinguishes noise and signals in infrared signals with short interval time and long total coding time, so that the automatic gain adjusting circuit has high accuracy in decoding the infrared signals with short interval time and long total coding time.
The automatic gain adjuster can receive and decode the infrared signal with short interval time and long total encoding time, so that noise and signals can be effectively distinguished, and the automatic gain circuit can decode the infrared signal with short interval time and long total encoding time.
In order to achieve the above object, the present invention provides an automatic gain adjuster, which includes a noise integrator, an interval time detector, a hold time timer, an RS flip-flop, a control logic circuit, and a gain control integrator;
the output end of the noise integrator is respectively connected to the input end of the interval time detector, the first input end of the holding time timer and the first input end of the control logic circuit;
The output end of the interval time detector is respectively connected to the first input end of the RS trigger and the second input end of the holding time timer;
The output end of the holding time timer is respectively connected to the second input end of the RS trigger and the second input end of the control logic circuit;
The output end of the RS trigger is respectively connected to the third input end of the holding time timer and the third input end of the control logic circuit;
the first output end of the control logic circuit is connected to the first input end of the gain control integrator, and the second output end of the control logic circuit is connected to the second input end of the gain control integrator.
Preferably, the noise integrator is configured to receive an input signal of the automatic gain adjuster, determine whether the input signal belongs to a preset frequency range, and control an output end of the noise integrator to output a high level or a low level according to a determination result;
The interval time detector is used for detecting the low-level duration time and the high-level duration time of the output end of the noise integrator in real time, calculating and obtaining a judgment threshold value, comparing the magnitude relation between the high-level duration time and the judgment threshold value, and controlling the output end of the interval time detector to output high level or low level according to the comparison result;
The RS trigger is used for detecting the level and the level change condition of the output end of the interval time detector and the level change condition of the output end of the holding time timer in real time, and controlling the output end of the RS trigger to output high level or low level according to the detection result;
The hold time timer is configured to detect the level of the output end of the noise integrator, the level of the output end of the interval time detector, and the level of the output end of the RS trigger in real time, and detect the level change condition of the output end of the noise integrator and the level change condition of the output end of the interval time detector, and control the output end of the hold time timer to output one of a low level, a high level, and a positive narrow pulse according to the detection result;
The control logic circuit is used for detecting the levels of the output end of the noise integrator, the output end of the holding time timer and the output end of the RS trigger in real time, controlling the first output end of the control logic circuit to output a low level or a high level according to the detection result, and controlling the second output end of the control logic circuit to output a high level or a low level;
The gain control integrator is used for detecting the level of the first output end and the second output end of the control logic circuit in real time, and controlling the output end of the gain control integrator to output a gain control signal according to the detection result.
Preferably, the predetermined frequency range is 36 khz to 41 khz.
Preferably, the judgment threshold is a sum of 1/10 of the low level duration and a preset time.
Preferably, the preset time is 100 microseconds.
The invention also provides an automatic gain adjustment circuit, which comprises a diode, a current/voltage conversion circuit, a preamplifier, a gain variable amplifier, a band-pass filter, a comparator, a demodulation integrator, a shaping output circuit and the automatic gain adjuster; the input end of the diode is connected to the ground, the output end of the diode is connected to the input end of the current/voltage conversion circuit, the output end of the current/voltage conversion circuit is connected to the input end of the preamplifier, the output end of the preamplifier is connected to the first input end of the gain variable amplifier, the output end of the gain variable amplifier is connected to the input end of the band-pass filter, the output end of the band-pass filter is connected to the input end of the comparator, the first output end of the comparator is connected to the demodulation integrator, and the output end of the demodulation integrator is connected to the input end of the shaping output circuit; a second output of the comparator is connected to an input of the noise integrator, and an output of the gain control integrator is connected to a second input of the gain variable amplifier.
Preferably, the comparator is configured to send an input signal to an input terminal of the noise integrator;
The gain variable amplifier is used for receiving the gain control signal output by the output end of the gain control integrator, controlling the voltage of the gain variable amplifier to rise or fall according to the gain control signal, and controlling the gain of the gain variable amplifier to rise or fall.
Preferably, the diode is an infrared photodiode.
Compared with the related art, the automatic gain adjuster comprises a noise integrator, an interval time detector, a holding time timer, an RS trigger, a control logic circuit and a gain control integrator; by means of the arrangement of the noise integrator, when an infrared coding signal with small interval time and long total coding length is received, the noise integrator judges whether the signal is a useful signal or ambient light interference noise, effectively distinguishes the signal from noise, and based on the judgment, a gain control signal is output through the gain control integrator, so that the noise is suppressed and the useful signal can be amplified and output. When the above-described automatic gain adjuster is applied to the automatic gain adjustment circuit of the present invention, the automatic gain adjustment circuit appropriately maintains the gain level based on the gain control signal, improving the decoding accuracy for the infrared signal having a short interval time and a long total encoding time.
[ Description of the drawings ]
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic circuit diagram of an automatic gain adjuster according to the present invention;
FIG. 2 is a waveform diagram illustrating the operation of the automatic gain adjuster according to the present invention;
FIG. 3 is a flowchart illustrating the operation of the automatic gain adjuster of the present invention;
Fig. 4 is a schematic circuit diagram of an automatic gain adjustment circuit according to the present invention.
[ Detailed description ] of the invention
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides an automatic gain adjuster 100, which includes a noise integrator 1, an interval time detector 2, a hold time timer 3, an RS flip-flop 4, a control logic circuit 5, and a gain control integrator 6.
The input end V in of the noise integrator 1 is connected with an external module, and the input end V in is used as an input port of the automatic gain adjuster 100 and is used for receiving an input signal sent by the external module;
the output terminal V int of the noise integrator 1 is connected to the input terminal of the interval time detector 2, the first input terminal of the hold time timer 3 and the first input terminal of the control logic circuit 5, respectively;
The output terminal V gap of the interval time detector 2 is connected to the first input terminal of the RS flip-flop 4 and the second input terminal of the hold time timer 3, respectively;
The output terminal V hold of the hold time timer 3 is connected to the second input terminal of the RS flip-flop 4 and the second input terminal of the control logic circuit 5, respectively;
the output terminal V rs of the RS flip-flop 4 is connected to the third input terminal of the hold time timer 3 and the third input terminal of the control logic circuit 5, respectively;
A first output V sp of the control logic circuit 5 is connected to a first input of the gain control integrator 6, and a second output V sn of the control logic circuit 5 is connected to a second input of the gain control integrator 6;
The output terminal V agc of the gain control integrator 6 is connected to an external module, and the output terminal V agc is used as an output port of the automatic gain adjuster 100, so as to output a gain control signal to the external module.
Referring to fig. 1-3, the functions of the various modules of the automatic gain adjuster 100 are described below:
The noise integrator 1 is configured to receive an input signal sent by an external module, determine whether the input signal belongs to a preset frequency range, and control an output end of the noise integrator to output a high level or a low level according to a determination result.
Specifically, the noise integrator 1 performs an integration operation on the input signal received by the input terminal V in, determines whether the input signal belongs to a preset frequency range, if so, controls the output terminal V int to output a low level, and if not, controls the output terminal V int to output a high level; the typical value of the preset frequency range is 36 khz to 41 khz, but other frequency ranges are also possible.
The interval time detector 2 is configured to detect the low level duration and the high level duration of the output end V int of the noise integrator 1 in real time, calculate and obtain a judgment threshold, compare the magnitude relation between the high level duration and the judgment threshold, and control the output end V gap of the interval time detector 2 to output a high level or a low level according to the comparison result.
Specifically, when the output terminal V int outputs a low level, the interval time detector 2 detects in real time the duration of the output terminal V int outputting the low level, denoted as a low level duration T b, and the low level duration T b is a burst time; when the output terminal V int outputs a high level, the interval time detector 2 detects in real time the duration of the output terminal V int outputting the high level, which is denoted as a high level duration T gap, and the high level duration T gap is the interval time between two adjacent pulse signals; the interval time detector 2 obtains the determination threshold T 0 through a preset functional relation calculation, specifically, the determination threshold T i is a sum of one tenth of the low-level duration T b and a preset time T 0, that is, the determination threshold: t i＝Tb×10％+T0. Wherein i refers to comparison of the ith time, and i is an integer greater than or equal to 1; the preset time T 0 is preset, and may be specifically set according to practical situations, for example, in this embodiment, the preset time T 0 is 100 microseconds.
For ease of understanding, the operation of the inter-time detector 2 will be illustrated as follows:
when the output terminal V int outputs a low level first, the interval time detector 2 detects and records a first low level duration T b1, and calculates a determination threshold T 1＝Tb1×10％+T0 for obtaining a first comparison according to the first low level duration T b1; When the output terminal V int stops outputting the low level and changes to output the high level, the interval time detector 2 detects and records the first high level duration T gap1, and compares the first high level duration T gap1 with the first comparison judgment threshold T 11 in real time, If the first high level duration T gap1 is greater than the first comparison determination threshold T 11, the output terminal V gap of the interval detector 2 outputs a low level; Then, when the output terminal V int stops outputting the high level and changes to output the low level, the interval time detector 2 detects and records the low level duration T b2 of the second time, at this time, calculates the judgment threshold T 2＝Tb2×10％+T0 for obtaining the second comparison according to the low level duration T b2 of the second time, The inter-time detector 2 then compares the second comparison decision threshold T 12 with the last detected first high-level duration T gap1, and when the first high-level duration T gap1 is less than the second comparison decision threshold T 12, the output V gap of the inter-time detector 2 outputs a high level. similarly, the inter-time detector 2 controls the output terminal V gap to output a high level or a low level according to the result of the comparison.
The RS flip-flop 4 is configured to detect the level and the level change condition of the output end V gap of the interval time detector 2 and the level change condition of the output end V hold of the hold time timer 3 in real time, and control the output end V rs of the RS flip-flop 4 to output a high level or a low level according to the detection result.
Specifically, when the output terminal V gap is detected as a rising edge and the output terminal V hold keeps outputting a low level, the output terminal V rs outputs a high level; when the output terminal V hold is detected as a rising edge while the output terminal V gap maintains the output low level, the output terminal V rs outputs the low level.
The hold time timer 3 is configured to detect the level of the output terminal V int of the noise integrator 1, the level of the output terminal V gap of the interval time detector 2, and the level of the output terminal V rs of the RS flip-flop 4 in real time, and detect the level change condition of the output terminal V int of the noise integrator 1 and the level change condition of the output terminal V gap of the interval time detector 2, and control the output terminal V hold of the hold time timer 3 to output one of a low level, a high level, and a positive and a narrow pulse according to the detection result.
Specifically, when it is detected that the output terminal V gap outputs a high level or the output terminal V int outputs a low level, the output terminal V hold outputs a low level.
When the output end V rs is detected to output a high level and the input end V gap is a falling edge, the output end V hold keeps outputting a low level in a first preset time, and then outputs a positive narrow pulse; the period of the positive narrow pulse is not limited, for example, as an alternative embodiment, the period of the positive narrow pulse is preferably 10 microseconds.
When the output terminal V rs outputs a low level and the output terminal V int is a rising edge, the output terminal V hold outputs a low level which is maintained for a second preset time, and then outputs a high level.
It should be noted that the first preset time and the second preset time are not limited, and may be set according to practical situations, for example, in this embodiment, the first preset time is 10 ms, and the second preset time is 20 ms.
The control logic circuit 5 is configured to detect the levels of the output terminal V int of the noise integrator 1, the output terminal V hold of the hold time timer 3, and the output terminal V rs of the RS flip-flop 4 in real time, control the first output terminal V sp of the control logic circuit 5 to output a low level or a high level according to the detection result, and control the second output terminal V sn of the control logic circuit 5 to output a high level or a low level;
Specifically, when it is detected that the output terminal V rs outputs a high level and the output terminal V int outputs a low level, the first output terminal V sp outputs a low level, otherwise, the first output terminal V sp outputs a high level.
When the output terminal V rs outputs a low level and the output terminal V hold outputs a high level, the second output terminal V sn outputs a high level, otherwise, the second output terminal V sn outputs a low level.
The gain control integrator 6 is configured to detect the level of the first output terminal V sp and the second output terminal V sn of the control logic circuit 5 in real time, and control the output terminal V agc of the gain control integrator 6 to output a gain control signal according to the detection result.
Specifically, when it is detected that the first output terminal V sp outputs a high level and the second output terminal V sn outputs a low level, the voltage of the output terminal V agc is kept constant and a gain maintaining signal is transmitted to an external module.
When the first output terminal V sp outputs a low level and the second output terminal V sn outputs a low level, the voltage of the output terminal V agc rises and a gain down signal is transmitted to an external module.
When the first output terminal V sp outputs a high level and the second output terminal V sn outputs a high level, the voltage of the output terminal V agc drops and a gain up signal is transmitted to an external module.
Further, as shown in the figure, the whole working procedure of the automatic gain adjuster 100 is:
In stage 001, the initial state of the automatic gain adjustment circuit 100 is stage 001, and the automatic gain adjuster 100 determines whether the output terminal V int is at a low level in real time.
When the output terminal V int is detected to be at the low level, the process goes to the stage 009, the second output terminal V sn is controlled to output the low level, the gain maintaining signal is sent, and then the process goes back to the stage 001 to repeatedly judge whether the output terminal V int is at the low level.
When the output V int goes high, it jumps to phase 002.
In the stage 002, it is determined whether the high level duration T gap of the time is smaller than the determination threshold T i for the time determination, if yes, the stage 003 is skipped, the output terminal V rs outputs the high level, and the time is counted from 0 seconds, and the time length is counted and recorded as the trigger duration T rs. Then, while keeping recording the trigger duration T rs, jumping to a stage 004 to determine whether the output terminal V int is at a low level, if yes, jumping to a stage 006 to enable the first output terminal V sp to output a low level, so that the voltage of the output terminal V agc rises, and sending a gain down signal; if not, the process goes to a stage 005 to make the first output terminal V sp output a high level, and sends a gain hold signal. Then, returning to the stage 002 again, determining whether the high level duration T gap of the time is smaller than the determination threshold T i for the time determination, if yes, jumping to the stage 003, repeatedly enabling the output terminal V rs to output the high level, and restarting timing from 0 seconds, and recording the timing length of the time as the trigger duration T rs. The logic loops formed by subsequent stages 004, 005, 006 and 002 are then repeated.
In stage 002, when it is determined whether or not the high-level duration T gap of the time is greater than the determination threshold T i for the time determination, the process proceeds to stage 007.
In stage 007, it is determined whether the output terminal V rs is at a low level, if yes, it jumps to stage 011, and determines whether the duration T gap of the high level is greater than the second preset time; if not, the process goes to stage 008 to determine whether the trigger duration T rs is greater than the first preset time.
In stage 008, if the result of the determination is yes, the process jumps to stage 010, so that the output terminal V rs outputs a low level, at this time, the first output terminal V sp outputs a high level, a gain hold signal is sent, and then the process jumps to stage 011 again; if the result is negative, go to stage 004 and enter the logic loop formed by the following stages 005, 006 and 002.
In the stage 011, if the judgment result is yes, the process jumps to a stage 013, so that the second output terminal V sn outputs a high level, the voltage of the output terminal V agc is reduced, a gain rising signal is sent, and then the process jumps to a stage 001 again; if the result is negative, the process goes to stage 012, the second output terminal V sn is enabled to output a low level, and a gain hold signal is sent, and then goes to stage 001 again.
Referring to fig. 1 and fig. 4, the present invention further provides an automatic gain adjustment circuit 200, which includes a diode 201, a current/voltage conversion circuit 202, a pre-amplifier 203, a gain variable amplifier 204, a band-pass filter 205, a comparator 206, a demodulation integrator 207, a shaping output circuit 208, and the automatic gain adjuster 100 according to the present invention.
In this embodiment, the input end of the diode 201 is connected to the ground, the output end of the diode 201 is connected to the input end of the current/voltage conversion circuit 202, the output end of the current/voltage conversion circuit 202 is connected to the input end of the preamplifier 203, the output end of the preamplifier 203 is connected to the first input end of the gain variable amplifier 204, the output end of the gain variable amplifier 204 is connected to the input end of the band-pass filter 205, the output end of the band-pass filter 205 is connected to the input end of the comparator 206, the first output end of the comparator 206 is connected to the demodulation integrator 207, and the output end of the demodulation integrator 207 is connected to the input end of the shaping output circuit 208; a second output of the comparator 206 is connected to an input of the noise integrator 1, and an output of the gain control integrator 204 is connected to a second input of the gain variable amplifier 204.
It should be noted that the diode 201 is an infrared photodiode, and is configured to receive a red signal sent by an infrared signal emitting device.
Further, the comparator 206 is configured to send an input signal to the input terminal V int of the noise integrator 1; the gain variable amplifier 204 is configured to receive a gain control signal output from the output terminal V agc of the gain control integrator 1, where the gain control signal includes any one of a gain hold signal, a gain up signal, and a gain down signal, and control the voltage of the gain variable amplifier 204 to rise or fall according to the gain control signal, and control the gain of the gain variable amplifier 204 to rise or fall.
The automatic gain adjuster 100 of the present invention is applied to the automatic gain adjusting circuit 200 of the present invention, and it should be noted that each device in the automatic gain adjusting circuit 200, such as the diode 201, the current/voltage converting circuit 202, the preamplifier 203, the gain variable amplifier 204, the band-pass filter 205, the comparator 206, the demodulation integrator 207, and the shaping output circuit 208, are all devices or circuit chips in the prior art; meanwhile, the components in the automatic gain adjuster 100, such as the noise integrator 1, the interval time detector 2, the hold time timer 3, the RS flip-flop 4, the control logic circuit 5, the gain control integrator 6, and the like, are components or circuit chips in the prior art, and the circuit structure of the present invention is formed by different circuit connections of the components so as to realize a new function, so that the automatic gain adjuster 100 can read the digital signal output by the comparator 206, judge whether the signal is a useful signal or an ambient light interference noise through the noise integrator 1, and send a gain control signal to the gain variable amplifier 204 through the gain control integrator 6 based on the judgment, thereby effectively suppressing the noise and amplifying the useful signal. Thereby enabling the automatic gain adjustment circuit 200 to properly maintain the gain level based on the gain control signal, improving its decoding accuracy for infrared signals having short interval times and long total encoding times.
Compared with the related art, the automatic gain adjuster comprises a noise integrator, an interval time detector, a holding time timer, an RS trigger, a control logic circuit and a gain control integrator; by means of the arrangement of the noise integrator, when an infrared coding signal with small interval time and long total coding length is received, the noise integrator judges whether the signal is a useful signal or ambient light interference noise, effectively distinguishes the signal from noise, and based on the judgment, a gain control signal is output through the gain control integrator, so that the noise is suppressed and the useful signal can be amplified and output. When the above-described automatic gain adjuster is applied to the automatic gain adjustment circuit of the present invention, the automatic gain adjustment circuit appropriately maintains the gain level based on the gain control signal, improving the decoding accuracy for the infrared signal having a short interval time and a long total encoding time.
While the invention has been described with respect to the above embodiments, it should be noted that modifications can be made by those skilled in the art without departing from the inventive concept, and these are all within the scope of the invention.
Claims (7)
1. An automatic gain adjuster, comprising a noise integrator, an interval time detector, a hold time timer, an RS trigger, control logic, and a gain control integrator;
the output end of the noise integrator is respectively connected to the input end of the interval time detector, the first input end of the holding time timer and the first input end of the control logic circuit;
The output end of the interval time detector is respectively connected to the first input end of the RS trigger and the second input end of the holding time timer;
The output end of the holding time timer is respectively connected to the second input end of the RS trigger and the second input end of the control logic circuit;
The output end of the RS trigger is respectively connected to the third input end of the holding time timer and the third input end of the control logic circuit;
A first output end of the control logic circuit is connected to a first input end of the gain control integrator, and a second output end of the control logic circuit is connected to a second input end of the gain control integrator;
the noise integrator is used for receiving the input signal of the automatic gain adjuster, judging whether the input signal belongs to a preset frequency range, and controlling the output end of the noise integrator to output high level or low level according to a judging result;
The interval time detector is used for detecting the low-level duration time and the high-level duration time of the output end of the noise integrator in real time, calculating and obtaining a judgment threshold value, comparing the magnitude relation between the high-level duration time and the judgment threshold value, and controlling the output end of the interval time detector to output high level or low level according to the comparison result;
The RS trigger is used for detecting the level and the level change condition of the output end of the interval time detector and the level change condition of the output end of the holding time timer in real time, and controlling the output end of the RS trigger to output high level or low level according to the detection result;
The hold time timer is configured to detect the level of the output end of the noise integrator, the level of the output end of the interval time detector, and the level of the output end of the RS trigger in real time, and detect the level change condition of the output end of the noise integrator and the level change condition of the output end of the interval time detector, and control the output end of the hold time timer to output one of a low level, a high level, and a positive narrow pulse according to the detection result;
The control logic circuit is used for detecting the levels of the output end of the noise integrator, the output end of the holding time timer and the output end of the RS trigger in real time, controlling the first output end of the control logic circuit to output a low level or a high level according to the detection result, and controlling the second output end of the control logic circuit to output a high level or a low level;
The gain control integrator is used for detecting the level of the first output end and the second output end of the control logic circuit in real time, and controlling the output end of the gain control integrator to output a gain control signal according to the detection result.
2. The automatic gain adjuster of claim 1, wherein the predetermined frequency range is 36 khz to 41 khz.
3. The automatic gain adjuster according to claim 1, wherein the determination threshold is a sum of 1/10 of the low level duration and a preset time.
4. The automatic gain adjuster of claim 3 wherein the predetermined time is 100 microseconds.
5. An automatic gain adjustment circuit comprising a diode, a current/voltage conversion circuit, a pre-amplifier, a gain variable amplifier, a band pass filter, a comparator, a demodulation integrator, a shaping output circuit, and an automatic gain adjuster according to any one of claims 1-4; the input end of the diode is connected to the ground, the output end of the diode is connected to the input end of the current/voltage conversion circuit, the output end of the current/voltage conversion circuit is connected to the input end of the preamplifier, the output end of the preamplifier is connected to the first input end of the gain variable amplifier, the output end of the gain variable amplifier is connected to the input end of the band-pass filter, the output end of the band-pass filter is connected to the input end of the comparator, the first output end of the comparator is connected to the demodulation integrator, and the output end of the demodulation integrator is connected to the input end of the shaping output circuit; a second output of the comparator is connected to an input of the noise integrator, and an output of the gain control integrator is connected to a second input of the gain variable amplifier.
6. The automatic gain adjustment circuit of claim 5, wherein,
The comparator is used for sending an input signal to the input end of the noise integrator;
The gain variable amplifier is used for receiving the gain control signal output by the output end of the gain control integrator, controlling the voltage of the gain variable amplifier to rise or fall according to the gain control signal, and controlling the gain of the gain variable amplifier to rise or fall.
7. The automatic gain adjustment circuit of claim 5, wherein the diode is an infrared photodiode.
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