CN110398617B - Testing device and folding probe card testing system - Google Patents
Testing device and folding probe card testing system Download PDFInfo
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- CN110398617B CN110398617B CN201810377251.XA CN201810377251A CN110398617B CN 110398617 B CN110398617 B CN 110398617B CN 201810377251 A CN201810377251 A CN 201810377251A CN 110398617 B CN110398617 B CN 110398617B
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- 238000012360 testing method Methods 0.000 title claims abstract description 262
- 239000000523 sample Substances 0.000 title claims description 59
- 238000010586 diagram Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 8
- 238000012812 general test Methods 0.000 description 3
- 238000012669 compression test Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention discloses a test device which is provided with a first output/input, a second output/input, a first comparator, a second comparator, a data combination module, a first data output circuit and a second data output circuit. The first comparator and the second comparator receive the first test data and the second test data respectively. The data combining module, electrically connected to the first comparator and the second comparator, receives the compared first test data of the first comparator and the compared second test data of the second comparator, and further receives the instruction code. The first data output circuit and the second data output circuit are respectively connected to the first output/input and the second output/input, and are further electrically connected to the data combination module.
Description
Technical Field
The present invention relates to a test apparatus and a folded probe card test system using the same, and more particularly, to a test apparatus having flexibility for use with a plurality of different probe cards having one and a plurality of input/outputs.
Background
When testing Integrated Circuits (ICs) on a wafer, multiple devices are tested in parallel as much as possible, to be cost effective and to reduce the test time per wafer. Test system controllers have evolved to increase the number of channels, and thus the number of devices that can be tested in parallel. However, a test system controller with added test channels is an important cost factor for a test system, as is a probe card with complex wiring to accommodate multiple parallel test channels. It is therefore desirable to provide an overall probe card structure that allows increased test parallelism without requiring increased test system controller channels and without increasing probe card routing complexity.
Referring to fig. 1, fig. 1 is a block diagram of a conventional test apparatus in a conventional test system. The conventional testing apparatus 1 includes a plurality of comparators 111 and 112 and a plurality of data output circuits 121 and 122, wherein each of the comparators 111 and 112 is electrically connected to a corresponding one of the data output circuits 121 and 122 in a one-to-one manner.
Each comparator 111, 112 receives a corresponding one of the test data DG _1, DG _ 2. Each comparator 111, 112 compares the received test data DG _1, DG _2 and outputs the compared test data to a corresponding one of the data output circuits 121, 122. Then, the data output circuits 121 and 122 output the compared test data at their output terminals DQ1 and DQ2, respectively. The conventional test apparatus 1 employs a plurality of input/output configurations (i.e., 2 input/output configurations), but this may increase the wiring complexity of the probe card.
Referring to fig. 2, fig. 2 is a block diagram of another conventional testing apparatus in a conventional testing system. The conventional testing apparatus 2 includes a plurality of comparators 211 and 212, a data combiner 22 and a data output circuit 23, wherein the comparators 211 and 212 are electrically connected to the data combiner 22, and the data combiner 22 is electrically connected to the data output circuit 23.
Each comparator 211, 212 receives a corresponding one of the test data DG _1, DG _ 2. Each comparator 211, 212 compares the received test data DG _1, DG _2 and outputs the compared test data to the data combiner 22. The data combiner 22 further receives the instruction codes CY [1:0] and outputs the compared test data of the comparator 211, the compared test data of the comparator 212, or a combination of the compared test data of the comparators 211, 212 to the data output circuit 23 according to the instruction codes CY [1:0 ].
For example, when the command code CY [1:0] is "00", the data output circuit 23 outputs the combination of the compared test data of the comparators 211, 212 at its output DQ 1. When the command code CY [1:0] is "10", the data output circuit 23 outputs the compared test data of the comparator 211 at its output terminal DQ 1. When the command code CY [1:0] is "01", the data output circuit 23 outputs the compared test data of the comparator 212 at its output terminal DQ 1. The use of a single input/output configuration (i.e., 1 input/output configuration) with the existing test apparatus 2 may result in a need for a test controller and may not be suitable for probe cards having multiple inputs/outputs.
Disclosure of Invention
One of the objectives of the present invention is to provide a test apparatus that can be adapted for use in both test systems with one and more input/outputs (i.e., probe cards with flexibility for one and more input/outputs).
It is another object of the present invention to provide a folded probe card test system capable of using a test apparatus for a general test mode.
At least in order to achieve the above object, the present invention provides a test apparatus comprising; a first input/output (IO) and a second input/output; a first comparator to receive first test data; a second comparator to receive second test data; the data combination module is electrically connected to the first comparator and the second comparator, receives the compared first test data of the first comparator and the compared second test data of the second comparator, and further receives the instruction code; the first data output circuit is electrically connected to the first input/output and data combination module; the second data output circuit is electrically connected to the second output/input and data combination module, wherein according to the instruction code, the data combination module respectively outputs the compared first test data and the compared second test data to the first output/input and the second output/input through the first data output circuit and the second data output circuit; alternatively, the data combining module outputs the compared second test data and the compared first test data to the first output/input and the second output/input through the first data output circuit and the second data output circuit, respectively, according to the instruction code.
In one embodiment of the present invention, the data combining module outputs a combination of the compared first test data and the compared second test data to the first input/output and the second input/output through the first data output circuit and the second data output circuit according to the command code.
In one embodiment of the present invention, the data combining module includes a first data combiner and a second data combiner, the first comparator and the second comparator are electrically connected to all of the first data combiner and the second data combiner, and the first data combiner and the second data combiner are respectively connected to the first data output circuit and the second data output circuit, wherein the instruction code is applied to the first data combiner and the second data combiner.
In an embodiment of the present invention, the testing apparatus further includes: a third output/input and a fourth output/input; the third data output circuit and the fourth data output circuit are respectively and electrically connected to the third output/input and the fourth output/input and further electrically connected with the data combination module; wherein the data combining module outputs the compared first test data of the first comparator to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared second test data of the second comparator to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, according to the instruction code; or, according to the instruction code, the data combining module outputs the compared first test data of the first comparator to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, and the data combining module outputs the compared second test data of the second comparator to the first output/input and the third output/input through the first data output circuit and the third data output circuit; or, the data combination module outputs a combination of the compared first test data and the compared second test data to the first to fourth output/inputs through the first to fourth data output circuits according to the instruction code.
In one embodiment of the present invention, the test apparatus further comprises a third output/input and a fourth output/input; third to eighth comparators for receiving third to eighth test data, respectively; and third to fourth data output circuits electrically connected to the third output/input and the fourth output/input, respectively, and further electrically connected to the data combining module; wherein the data combining module outputs four of the compared first to eighth test data of the first to eighth comparators to the first to fourth output/inputs through the first to fourth data output circuits according to the instruction code.
In one embodiment of the present invention, the data combining module includes first to fourth data combiners, the first to eighth comparators are electrically connected to all of the first to fourth data combiners, and the first to fourth data combiners are respectively connected to the first to fourth data output circuits, wherein the command code is applied to the first to fourth data combiners.
At least to achieve the above object, the present invention provides a test apparatus comprising: first to fourth output/inputs; a first comparator receiving ith test data from a chip die; a second comparator receiving the i +1 th test data from the chip die; a data combination module electrically connected to the first comparator and the second comparator, receiving the ith test data compared by the first comparator and the (i +1) th test data compared by the second comparator, and further receiving the instruction code; first to fourth data output circuits electrically connected to the data combining module and respectively electrically connected to the first to fourth output/inputs; wherein the data combining module outputs the compared ith test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared (i +1) th test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, according to the instruction code; or, according to the instruction code, the data combination module outputs the compared ith +1 test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combination module outputs the compared ith test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit; where i is an integer belonging to an even number and i +1 is no greater than the number of outputs of the chip die.
At least to achieve the above object, the present invention provides a folded probe card test system, comprising: a testing device; and a folded probe card electrically connected to the test device; wherein, testing arrangement includes: first to fourth output/inputs; a first comparator receiving ith test data from a chip die; a second comparator receiving the i +1 th test data from the chip die; the data combination module is electrically connected to the first comparator and the second comparator, receives the ith test data compared by the first comparator and the (i +1) th test data compared by the second comparator, and further receives the instruction codes; and first to fourth data output circuits electrically connected to the data combining module and respectively electrically connected to the first to fourth output/inputs; according to the instruction code, the data combination module outputs the compared ith test data to a first output/input and a third output/input through a first data output circuit and a third data output circuit, and the data combination module outputs the compared (i +1) th test data to a second output/input and a fourth output/input through a second data output circuit and a fourth data output circuit; or, according to the instruction code, the data combination module outputs the compared ith +1 test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combination module outputs the compared ith test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit; where i is an integer belonging to an even number and i +1 is no greater than the number of outputs of the chip die.
In an embodiment of the present invention, the data combining module outputs a combination of the compared ith test data and the compared (i +1) th test data to the first to fourth output/inputs through the first to fourth data output circuits according to the command code.
In one embodiment of the present invention, the first and third input/output are electrically connected to each other through the folded probe card, and the second and fourth input/output are electrically connected to each other through the folded probe card.
In summary, the test apparatus can be applied to a test system having one input/output and a test system having a plurality of input/outputs, and by expanding the test apparatus, the test apparatus can be used to fold a probe card.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art to which the present invention pertains, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block diagram of a conventional testing apparatus in a conventional testing system.
FIG. 2 is a block diagram of another conventional testing apparatus in a conventional testing system.
FIG. 3 is a block diagram of a test apparatus in a test system according to an embodiment of the present invention.
FIG. 4 is a block diagram of a test apparatus in a test system according to another embodiment of the present invention.
FIG. 5 is a block diagram of a folded probe card test system according to one embodiment of the invention.
Fig. 6 is a block diagram of a testing apparatus in a folded probe card testing system according to an embodiment of the present invention.
FIG. 7 is a block diagram of a test apparatus in a test system according to another embodiment of the present invention.
Detailed Description
In order to make the examiner more easily understand the objects, features, and effects of the present invention, a plurality of embodiments are provided together with the accompanying drawings for detailed description of the present invention.
One embodiment of the present invention provides a test apparatus comprising a plurality of data combiners, wherein each data combiner is electrically connected to all comparators of the test apparatus, and the compared test data output from the data combiners may differ based on the instruction code applied on the data combiners. Therefore, the test apparatus is applicable not only to a probe card having one input/output in the compression test mode but also to a probe card having a plurality of input/outputs in the compression test mode. Furthermore, in one embodiment of the present invention, the test apparatus may be expanded to accommodate a folded probe card in a general test mode to provide a folded probe card test system.
Referring to fig. 3, fig. 3 is a block diagram of a test apparatus in a test system according to an embodiment of the present invention. The test apparatus 3 includes a plurality of comparators 311, 312, a data combining module 32, and a plurality of data output circuits 331, 332. The test apparatus 3 has, for example, two input/outputs DQ1, DQ2, but the present invention is not limited thereto. The comparators 311, 312 are electrically connected to the data combining module 32, the data combining module 32 is electrically connected to the data output circuits 331, 332, and the data output circuits 331, 332 are electrically connected to the input/output DQ1, DQ2, respectively. Input/outputs DQ1, DQ2 may be used to be connected to probe cards having 2 inputs/outputs or 1 input/output.
The data combination module 32 comprises a plurality of data combiners 321, 322. The data combiner 321 is electrically connected to the comparators 311, 312, and the data combiner 322 is electrically connected to the comparators 311, 312. The data combiners 321, 322 receive the compared test data of the comparators 311, 312 and further receive the instruction codes CY [1:0 ]. When the instruction code CY [1:0] applied to the data combination module 32 is "00", the data combiners 321, 322 output the combination of the compared test data of the comparators 311, 312 to the data output circuits 331, 332. When the instruction code CY [1:0] applied to the data combining module 32 is "10", the data combiners 321, 322 output the compared test data of the comparators 311, 312 to the data output circuits 321, 322, respectively. When the command code CY [1:0] applied to the data combining module 32 is "01", the data combiners 321, 322 output the compared test data of the comparators 312, 311 to the data output circuits 321, 322, respectively.
When a probe card having one input/output is used, the input/output of the probe card may be electrically connected to one of the input/outputs DQ1, DQ2 of the test apparatus 3, and the compared test data of the comparator 311 or 312 detected by the probe card having one input/output may be identified by identifying the command code CY [1:0 ]. For example, if the I/O of the probe card is electrically connected to the I/O DQ2 of the test apparatus 3 and the command codes CY [1:0] are "10", the compared test data of the comparator 312 is detected. In addition, by changing the instruction code CY [1:0] to "01", the compared test data of the comparator 311 is detected.
When a probe card having two input/outputs is used, the two input/outputs of the probe card may be electrically connected to the input/outputs DQ1, DQ2 of the test apparatus 3, respectively (or, may be electrically connected to the input/outputs DQ2, DQ1 of the test apparatus 3, respectively), and, by identifying the command codes CY [1:0], the compared test data of the comparator 311 or 312 probed by the probe card having two input/outputs may be identified (or, the compared test data of the comparator 312 or 311 may be identified). For example, if two input/outputs of the probe card are electrically connected to input/outputs DQ1, DQ2 of the test apparatus 3, respectively, and the command codes CY [1:0] are "10", the compared test data of the comparators 311, 312 are detected by the two input/outputs of the probe card, respectively. In addition, by changing the command code CY [1:0] to "01", the compared test data of the comparators 312, 11 are detected by two input/outputs of the probe card, respectively.
It is clear that the test apparatus 3 provides flexibility for two different probe cards with one input/output and with two input/outputs. In addition, for a probe card with one input/output, one of the input/outputs DQ1, DQ2 of the test apparatus may be selected to be electrically connected to the input/output of the probe card according to the circumstances (e.g., space limitations, noise, etc.).
Referring to fig. 4, fig. 4 is a block diagram of a test apparatus in a test system according to another embodiment of the present invention. The testing device 4 comprises a plurality of comparators 411 and 412, a data combining module 42 and a plurality of data output circuits 431 to 434, wherein the comparators 411 and 412 are electrically connected to the data combining module 42, and the data combining module 42 is electrically connected to the data output circuits 431 to 434. The test apparatus 4 further includes four input/outputs DQ1, DQ2, DQ3, DQ4 electrically connected to the data output circuits 431-434, respectively. The input/outputs DQ1, DQ2, DQ3, DQ4 may be used to be connected to probe cards having four input/outputs, two input/outputs, or one input/output.
The comparators 411, 412 receive the test data DG _1, DG _2, respectively, and the comparators 411, 412 output the compared test data to the data combining module 42, respectively. The data combining module 42 includes four data combiners 421-424, wherein the comparators 411, 412 are electrically connected to all the data combiners 421-424, and the data combiners 421-424 are electrically connected to the data output circuits 431-434. The data combiners 421-424 further receive the command codes CY [1:0 ]. When the command code CY [1:0] is "00", the data combiners 421-424 output the combination of the compared test data of the comparators 411, 412. When the instruction code CY [1:0] is "10", the data combiners 421, 423 output the compared test data of the comparator 411, and the data combiners 422, 424 output the compared test data of the comparator 412. When the instruction code CY [1:0] is "01", the data combiners 421, 423 output the compared test data of the comparator 412, and the data combiners 422, 424 output the compared test data of the comparator 411.
Referring to fig. 5, fig. 5 is a block diagram of a folded probe card test system according to an embodiment of the present invention. Folded probe card test system 5 includes semiconductor device 51 and folded probe card 52. The folded probe card 52 has 16 inputs/outputs arranged in a rainbow connection (rainbow connection). That is, the jth input/output of the folded probe card 52 is electrically connected to the (j +8) th input/output of the folded probe card 52, where j is an integer from 1 to 8.
The semiconductor device 51 may have a chip die 511 and a testing device 512, wherein two of the 8 output terminals of the chip die 511 are electrically connected to two input terminals of the testing device 512. For example, test device 512 receives test data DG _ i, DG _ (i +1), where i is an integer selected from 1, 3, 5, 7 (i.e., i is an integer and i +1 is not greater than the number of outputs of chip die 511). Semiconductor device 51 may be a memory device and chip die 511 may be a memory die, but the invention is not limited thereto. The four input/outputs DQi, DQ (i +1), DQ (i +8), DQ (i +9) of the test apparatus 512 are electrically connected to the jth, jth + 1, (j +8) th, and (j +9) th input/outputs of the folded probe card 52, respectively.
Referring to fig. 6, fig. 6 is a block diagram of a test apparatus in a folded probe card test system according to an embodiment of the present invention. The testing device 6 includes a plurality of comparators 611 and 612, 4 data combiners 621-624 in the data combining module 62, and a plurality of data output circuits 631-634, wherein the comparators 611 and 612 are electrically connected to the data combining module 62, and the data combining module 62 is electrically connected to the data output circuits 631-634. The testing device 6 further includes four input/output DQi, DQ (i +1), DQ (i +8), DQ (i +9), the input/output DQi, DQ (i +1), DQ (i +8), DQ (i +9) are electrically connected to the jth, jth + 1, jth + 8, jth +9 input/output of the folded probe card, respectively, and the data output circuits 631 to 634 are electrically connected to the input/output DQi, DQ (i +1), DQ (i +8), DQ (i +9), wherein i is an integer selected from 1, 3, 5, 7.
Referring to fig. 7, fig. 7 is a block diagram of a test apparatus in a test system according to another embodiment of the present invention. The test apparatus 7 includes a plurality of comparators 711-718, a data combining module 72, and a plurality of data output circuits 731-734. The test apparatus 3 has four input/outputs DQ1 to DQ4, for example, but the present invention is not limited thereto. The comparators 711-718 are electrically connected to the data combining module 72, the data combining module 72 is electrically connected to the data output circuits 731-734, and the data output circuits 731-734 are electrically connected to the input/output DQ 1-DQ 4, respectively. The input/outputs DQ 1-DQ 4 may be used to connect to a probe card with 4 inputs/outputs, 2 inputs/outputs, or 1 input/output.
The data combining module 72 includes a plurality of data combiners 721-724, wherein the data combiners 721-724 are electrically connected to the comparators 711-718 to receive the compared test data of the comparators 711-718, and the data combiners 721-724 are electrically connected to the data output circuits 731-734. The data combiners 721-724 further receive the command codes CY [2:0] and respectively output the compared test data of four comparators 711-718 to the data output circuits 731-734.
For example, when the instruction code CY [2:0] is "000", the data combiners 721-724 respectively output the compared test data of the comparators 711, 712, 713, 714. When the command code CY [2:0] is "001", the data combiners 721-724 respectively output the compared test data of the comparators 712, 711, 714, 713. When the command code CY [2:0] is "010", the data combiners 721-724 respectively output the compared test data of the comparators 713, 714, 711, 712. When the instruction code CY [2:0] is "011", the data combiners 721-724 respectively output the compared test data of the comparators 714, 713, 712, 711. For example, when the instruction code CY [2:0] is "100", the data combiners 721-724 respectively output the compared test data of the comparators 715, 716, 717, 718. When the instruction code CY [2:0] is "101", the data combiners 721 to 724 respectively output the compared test data of the comparators 716, 715, 718, 717. When the instruction code CY [2:0] is "110", the data combiners 721 to 724 respectively output the compared test data of the comparators 717, 718, 715, 716. When the instruction code CY [2:0] is "111", the data combiners 721-724 respectively output the compared test data of the comparators 718, 717, 716, 715.
It is noted that if the probe card has only two input/outputs, the input/outputs of the probe card can be electrically connected to the input/outputs DQ1 and DQ4 of the test apparatus 7, and when the command codes CY [2:0] applied to the data combiners 721-724 are "000", "001", "100", and "101" for a time interval, the compared test data of all comparators 711-718 can be detected. In addition, when testing the semiconductor memory, the command code CY [2:0] may be a portion of a column code (column code) of the semiconductor memory, wherein the portion of the column code may not be used for the semiconductor memory. Therefore, no additional code generator may be required to generate instruction code CY [2:0 ].
In summary, at least one of the test apparatus provided above can be adapted for use in a plurality of test systems having one and more input/outputs (i.e., a plurality of different probe cards having flexibility for use with one and more input/outputs) in a compressive test mode, and at least one of the test apparatus provided above can be used in a folded probe card test system in a general test mode.
Although the present invention has been described by way of specific embodiments, many modifications and variations may be made thereto by those skilled in the art without departing from the scope and spirit of the present invention set forth in the claims.
List of reference numerals
1: existing testing apparatus
2: existing testing apparatus
3: testing device
4: testing device
5: folding probe card test system
6: testing device
7: testing device
22: data combiner
23: data output circuit
32: data combination module
42: data combination module
51: semiconductor device with a plurality of semiconductor chips
52: folding probe card
62: data combination module
72: data combination module
111: comparator with a comparator circuit
112: comparator with a comparator circuit
121: data output circuit
122: data output circuit
211: comparator with a comparator circuit
212: comparator with a comparator circuit
311: comparator with a comparator circuit
312: comparator with a comparator circuit
321: data combiner
322: data combiner
331: data output circuit
332: data output circuit
411: comparator with a comparator circuit
412: comparator with a comparator circuit
421: data combiner
422: data combiner
423: data combiner
424: data combiner
431: data output circuit
432: data output circuit
433: data output circuit
434: data output circuit
511: chip crystal grain
512: testing device
611: comparator with a comparator circuit
612: comparator with a comparator circuit
621: data combiner
622: data combiner
623: data combiner
624: data combiner
631: data output circuit
632: data output circuit
633: data output circuit
634: data output circuit
711: comparator with a comparator circuit
718: comparator with a comparator circuit
721: data combiner
724: data combiner
731: data output circuit
734: data output circuit
DG _ 1: test data
DG _ 2: test data
DG _ i: test data
DG _ (i + 1): test data
DQ _ 1: input/output
DQ _ 2: input/output
DQi: input/output
DQ (i + 1): input/output
DQ (i + 8): input/output
DQ (i + 9): input/output
CY [1:0 ]: instruction code
CY [2:0 ]: instruction code
Claims (10)
1. A test apparatus, comprising:
a first output/input and a second output/input;
a first comparator for receiving a first test data;
a second comparator for receiving a second test data;
a data combination module, electrically connected to the first comparator and the second comparator, for receiving a compared first test data of the first comparator and a compared second test data of the second comparator, and further receiving a command code;
a first data output circuit electrically connected to the first output/input and the data combining module; and
a second data output circuit electrically connected to the second output/input and the data combining module;
wherein the compared test data output by the first data output circuit and the second data output circuit of the data combining module is different based on the instruction code, and
wherein the data combining module outputs the compared first test data and the compared second test data to the first output/input and the second output/input through the first data output circuit and the second data output circuit, respectively, according to the instruction code; or, according to the instruction code, the data combining module outputs the compared first test data and the compared second test data to the second output/input and the first output/input through the second data output circuit and the first data output circuit, respectively.
2. The test apparatus of claim 1, wherein the data combination module outputs a combination of the compared first test data and the compared second test data to the first input/output and the second input/output through the first data output circuit and the second data output circuit according to the command code.
3. The test apparatus of claim 1, wherein the data combining module comprises a first data combiner and a second data combiner, the first comparator and the second comparator being electrically connected to all of the first data combiner and the second data combiner, and the first data combiner and the second data combiner being respectively connected to the first data output circuit and the second data output circuit, wherein the instruction code is applied to the first data combiner and the second data combiner.
4. The test device of claim 1, further comprising:
a third input/output and a fourth input/output; and
a third data output circuit and a fourth data output circuit, electrically connected to the third output/input and the fourth output/input, respectively, and further electrically connected to the data combination module;
wherein the data combining module outputs the compared first test data of the first comparator to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared second test data of the second comparator to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, according to the instruction code; or, according to the instruction code, the data combining module outputs the compared first test data of the first comparator to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, and the data combining module outputs the compared second test data of the second comparator to the first output/input and the third output/input through the first data output circuit and the third data output circuit; or, the data combination module outputs a combination of the compared first test data and the compared second test data to the first to fourth output/inputs through the first to fourth data output circuits according to the instruction code.
5. The test device of claim 1, further comprising:
a third input/output and a fourth input/output;
a third to eighth comparators for receiving the third to eighth test data, respectively; and
a third and fourth data output circuits electrically connected to the third output/input and the fourth output/input, respectively, and further electrically connected to the data combining module;
wherein the data combining module outputs four of the compared first to eighth test data of the first to eighth comparators to the first to fourth output/inputs through the first to fourth data output circuits according to the instruction code.
6. The test apparatus of claim 5, wherein the data combining module comprises first to fourth data combiners, the first to eighth comparators being electrically connected to all of the first to fourth data combiners, and the first to fourth data combiners being connected to the first to fourth data output circuits, respectively, wherein the command code is applied to the first to fourth data combiners.
7. A test apparatus, comprising:
a first to fourth output/input;
a first comparator for receiving an ith test data from a chip die;
a second comparator for receiving an i +1 test data from the chip die;
a data combination module, electrically connected to the first comparator and the second comparator, for receiving a compared ith test data of the first comparator and a compared (i +1) th test data of the second comparator, and further receiving a command code; and
a first to fourth data output circuits electrically connected to the data combining module and respectively electrically connected to the first to fourth output/inputs;
wherein the compared test data output by the data combining module through the first to fourth data output circuits are different based on the instruction code, and
wherein the data combining module outputs the compared ith test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared (i +1) th test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, according to the instruction code; or, according to the instruction code, the data combining module outputs the compared i +1 th test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared i +1 th test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit; where i is an integer belonging to an even number and i +1 is no greater than the number of outputs of the chip die.
8. A folded probe card test system comprising:
a testing device; and
a folded probe card electrically connected to the test device;
wherein, this testing arrangement includes:
first to fourth output/inputs;
a first comparator for receiving an ith test data from a chip die;
a second comparator for receiving an i +1 test data from the chip die;
a data combination module, electrically connected to the first comparator and the second comparator, receiving a compared ith test data of the first comparator and a compared ith +1 test data of the second comparator, and further receiving an instruction code; and
first to fourth data output circuits electrically connected to the data combining module and respectively electrically connected to the first to fourth output/inputs;
wherein the compared test data output by the data combining module through the first to fourth data output circuits are different based on the instruction code, and
wherein the data combining module outputs the compared ith test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared (i +1) th test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit, according to the instruction code; or, according to the instruction code, the data combining module outputs the compared i +1 th test data to the first output/input and the third output/input through the first data output circuit and the third data output circuit, and the data combining module outputs the compared i +1 th test data to the second output/input and the fourth output/input through the second data output circuit and the fourth data output circuit; where i is an integer belonging to an even number and i +1 is no greater than the number of outputs of the chip die.
9. The folded probe card test system of claim 8, wherein the data combining module outputs a combination of the compared ith test data and the compared (i +1) th test data to the first to fourth output/inputs through the first to fourth data output circuits according to the command code.
10. The folded probe card test system of claim 8, wherein the first and third I/O are electrically connected to each other through the folded probe card, and the second and fourth I/O are electrically connected to each other through the folded probe card.
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