CN110391863B - Data transmission control method and system - Google Patents

Abstract

The invention discloses a data transmission control method and a system, wherein the data transmission control system comprises a PPC, an FPGA and a DSP which is respectively in communication connection with the PPC and the FPGA, and the data transmission control method is characterized in that under the hardware architecture of the PPC, the DSP and the FPGA, the DSP adopts a multithreading frame handshake and timeout control mechanism to realize the data transmission control of a TDMA link layer, control the switching among TDMA data transmission flows among various communication modes, and ensure the stable and controllable working flow among the various communication modes, thereby ensuring the reliability and the communication diversity of data transmission, and simultaneously meeting the reliability and the communication diversity of the TDMA data transmission among the various communication modes.

Description

Data transmission control method and system

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a data transmission control method and system.

Background

The special communication network is built by related departments or units according to business requirements, and is a telecommunication network generally used in the interior, such as an emergency communication network, a special communication network for electric power and subways, and the like. Time Division Multiple Access (TDMA) is a communication technology for realizing shared transmission media or networks, is also a Multiple Access technology widely applied in private communication networks, and provides an implementation mode for Multiple users to commonly use the same transmission medium.

In the prior art, TDMA data transmission is implemented in a private communication network, which may be based on various hardware architectures and implementations, and meanwhile, in order to meet the data transmission reliability requirement, the data transmission control methods of various private communication networks are limited to specific communication application scenarios. However, the communication application scenarios of various private communication networks are not unique, which puts application demands on the communication diversity of the private communication networks, and there is no data transmission control method that can simultaneously satisfy data transmission reliability and communication diversity.

Disclosure of Invention

In view of this, the present invention provides a data transmission control method and system, so as to achieve TDMA data transmission between dedicated communication networks and satisfy both data transmission reliability and communication diversity.

In order to achieve the above object, the following solutions are proposed:

the invention discloses a data transmission control method, which is suitable for a data transmission control system comprising a Macintonia tower processor PPC, a field programmable gate array FPGA and a digital signal processor DSP which is respectively in communication connection with the PPC and the FPGA, and comprises the following steps:

initializing a peripheral interface and peripheral equipment of the DSP, wherein the peripheral interface is a communication interface between the DSP and the PPC and the FPGA, and the peripheral equipment comprises a time slot timer, an overtime timer and an interrupt controller;

the DSP receives the control parameters and the first group network data frame parameters issued by the PPC; the PPC determines the control parameters and the first network data frame parameters according to application scenes and task requirements;

the DSP configures the receiving and sending time slot of the time slot timer and the overtime waiting time of the overtime timer according to the control parameters;

the DSP determines a first data frame type according to the first networking data frame parameters, and configures the FPGA according to the first data frame type;

the DSP triggers the time slot timer according to the synchronous pulse generated by the interrupt controller, and enters a networking mode; the networking mode comprises a networking sending thread and a networking receiving thread, and the DSP determines whether to enter the networking sending thread or the networking receiving thread according to the current time slot number of the time slot timer;

the DSP controls the FPGA to transmit data frames in a networking mode;

the DSP determines whether to switch into a networking mode or a data transmission mode according to a zone bit of a data frame transmitted in the networking mode, wherein the data transmission mode comprises a data sending thread and a data receiving thread;

if the data transmission mode is switched into, the DSP controls the FPGA to transmit data frames in the data transmission mode;

when the data frame transmitted by the DSP in the data transmission mode is an end frame, switching into a networking mode;

when the data frame transmitted by the DSP in the data transmission mode is not the end frame, starting the overtime timer according to the data frame; the data frame transmitted by the DSP in the digital transmission mode is determined according to the data frame transmitted by the previous thread;

if the data frame transmission is not completed within the timeout waiting time matched with the currently transmitted data frame and configured in the timeout timer, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data transmission mode;

when the data transmission mode is switched into the networking mode, the DSP enters the networking mode which is entered when the time slot timer is triggered, and under other conditions, the DSP is switched from a sending thread to a receiving thread or from the receiving thread to the sending thread during each switching.

Optionally, the networking sending thread includes:

the DSP switches the radio frequency of the FPGA into a sending, receiving and closing of networking frequency points;

the DSP sends a first mode switching instruction to the FPGA to enable the FPGA to be switched to a networking sending mode;

the DSP sends a wave gate starting instruction to the FPGA, and the wave gate is opened to enable the FPGA to send a data frame;

the DSP determines whether to switch into a networking receiving thread or a data receiving thread according to the zone bit of the data frame transmitted under the networking sending thread;

the networking receiving thread comprises the following steps:

the DSP switches the radio frequency of the FPGA into a switch receiving and switching of networking frequency points;

the DSP sends a second mode switching instruction to the FPGA to enable the FPGA to be switched to a networking receiving mode;

the DSP sends a wave gate ending instruction to the FPGA to close the wave gate;

the DSP determines whether to switch into a networking sending thread or a data sending thread according to the zone bit of the data frame transmitted under the networking receiving thread;

the data sending thread comprises:

the DSP switches the radio frequency of the FPGA into a sending, receiving and closing of a data transmission frequency point;

the DSP sends a third mode switching instruction to the FPGA to enable the FPGA to be switched to a data sending mode;

the DSP sends a wave gate starting instruction to the FPGA and opens a wave gate;

the DSP determines a transmitted data frame according to the data frame transmitted by the previous thread;

when the data frame sent by the DSP is an end frame, switching into a networking mode;

when the transmitted data frame is not the end frame, the DSP starts the overtime timer according to the transmitted data frame;

if the data frame transmission is not completed within the timeout waiting time which is configured in the timeout timer and matched with the currently sent data frame, determining that the state is abnormal, switching into a networking mode, otherwise, switching into a data receiving thread;

the data receiving thread comprises:

the DSP switches the radio frequency of the FPGA into a switch receiving and switching of a data transmission frequency point;

the DSP sends a fourth mode switching instruction to the FPGA to enable the FPGA to be switched to a data receiving mode;

the DSP sends a wave gate ending instruction to the FPGA to close the wave gate;

the DSP determines the received data frame according to the data frame transmitted by the previous thread;

the DSP starts the overtime timer according to the received data frame;

if the data frame is not received within the timeout waiting time which is configured in the timeout timer and matched with the currently received data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data sending thread when the received data frame is not an end frame by the DSP.

Optionally, the data receiving thread further includes:

if the local cache is full in the process of receiving the content data frame by the data receiving thread, switching into a data sending thread;

accordingly, the reply full frame is not successfully received when the data transmission thread transmits data.

Optionally, the method further includes: if the DSP receives a second set of network data frame parameters issued by the PPC, the DSP determines a second data frame type according to the second set of network data frame parameters, and configures the FPGA according to the second data frame type, and subsequently, the DSP controls the FPGA to adopt a data frame matched with the second data frame type when the FPGA transmits data frames.

Optionally, the method further includes: and the DSP uploads the received data frame to the PPC in a networking receiving thread.

A second aspect of the present invention discloses a data transmission control system, including: the device comprises a Macinton tower processor PPC, a field programmable gate array FPGA and a digital signal processor DSP which is respectively in communication connection with the PPC and the FPGA;

the PPC is used for determining control parameters and first group network data frame parameters according to application scenes and task requirements and issuing the control parameters and the first group network data frame parameters;

the peripheral interface of the DSP is a communication interface between the DSP and the PPC and the FPGA, and the peripheral equipment of the DSP comprises a time slot timer, an overtime timer and an interrupt controller;

the initialized DSP is used for receiving the control parameters and the first group of network data frame parameters sent by the PPC; configuring a receiving and sending time slot of the time slot timer and the overtime waiting time of the overtime timer according to the control parameters; the DSP determines a first data frame type according to the first networking data frame parameters, and configures the FPGA according to the first data frame type; the DS triggers the time slot timer according to the synchronous pulse generated by the interrupt controller, and enters a networking mode; the networking mode comprises a networking sending thread and a networking receiving thread, and the DSP determines whether to enter the networking sending thread or the networking receiving thread according to the current time slot number of the time slot timer; the DSP controls the FPGA to transmit data frames in a networking mode; the DSP determines whether to switch into a networking mode or a data transmission mode according to a zone bit of a data frame transmitted in the networking mode, wherein the data transmission mode comprises a data sending thread and a data receiving thread; if the data transmission mode is switched into, the DSP controls the FPGA to transmit data frames in the data transmission mode; when the data frame transmitted by the DSP in the data transmission mode is an end frame, switching into a networking mode; when the data frame transmitted by the DSP in the data transmission mode is not the end frame, starting the overtime timer according to the data frame; the data frame transmitted by the DSP in the digital transmission mode is determined according to the data frame transmitted by the previous thread; if the data frame transmission is not completed within the timeout waiting time matched with the currently transmitted data frame and configured in the timeout timer, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data transmission mode;

when the data transmission mode is switched into the networking mode, the DSP enters the networking mode which is entered when the time slot timer is triggered, and under other conditions, the DSP is switched from a sending thread to a receiving thread or from the receiving thread to the sending thread during each switching;

and the FPGA is used for transmitting various data frames under the control of the DSP.

Optionally, in the networking sending thread, the DSP is configured to:

switching the radio frequency of the FPGA into a sending-receiving switch of a networking frequency point; sending a first mode switching instruction to the FPGA to enable the FPGA to be switched to a networking sending mode; sending a wave gate starting instruction to the FPGA, and opening a wave gate to enable the FPGA to send a data frame; determining whether to switch into a networking receiving thread or a data receiving thread according to a zone bit of a data frame transmitted under the networking sending thread;

in the networking receiving thread, the DSP is configured to:

switching the radio frequency of the FPGA to a transmitting switch receiving of networking frequency points; sending a second mode fantasy instruction to the FPGA to enable the FPGA to be switched to a networking receiving mode; sending a wave gate ending instruction to the FPGA to close the wave gate, and determining whether to switch into a networking sending thread or a data sending thread according to a flag bit of a data frame transmitted under the networking receiving thread;

in the data sending thread, the DSP is configured to:

switching the radio frequency of the FPGA into a sending-receiving switch of a data transmission frequency point; sending a third mode switching instruction to the FPGA to switch the FPGA to a data sending mode; sending a wave gate starting instruction to the FPGA, and opening a wave gate; determining a transmitted data frame according to the data frame transmitted by the previous thread; when the transmitted data frame is an end frame, switching into a networking mode, and when the transmitted data frame is not the end frame, starting the timeout timer according to the transmitted data frame; if the data frame transmission is not completed within the timeout waiting time which is configured in the timeout timer and matched with the currently sent data frame, determining that the state is abnormal, switching into a networking mode, otherwise, switching into a data receiving thread;

in a data receiving thread, the DSP, configured to:

switching on and off a transmitter for switching the radio frequency of the FPGA into a data transmission frequency point; sending a fourth mode switching instruction to the FPGA to switch the FPGA to a data receiving mode; sending a wave gate ending instruction to the FPGA to close the wave gate; determining a received data frame according to a data frame transmitted by a previous thread; starting the overtime timer according to the received data frame; if the data frame is not received within the timeout waiting time which is configured in the timeout timer and matched with the currently received data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data sending thread when the received data frame is not an end frame.

Optionally, in the data receiving thread, the DSP is further configured to switch to a data sending thread if a local cache is full in a process of receiving a content data frame by the data receiving thread,

accordingly, the DSP fails to receive the reply full frame when the data sending thread sends data.

Optionally, the DSP is further configured to:

if the DSP receives a second set of network data frame parameters issued by the PPC, the DSP determines a second data frame type according to the second set of network data frame parameters, and configures the FPGA according to the second data frame type, and subsequently, the DSP controls the FPGA to adopt a data frame matched with the second data frame type when the FPGA transmits data frames.

Optionally, in the networking receiving thread, the DSP is further configured to upload the received data frame to the PPC.

According to the technical scheme, the data transmission control method comprises the steps that under the hardware architecture of the PPC processor, the DSP processor and the FPGA processor, firstly, the DSP configures the receiving and sending time slot of the time slot timer and the timeout waiting time of the timeout timer according to control parameters issued by the PPC, and determines a first data frame type according to first networking data frame parameters issued by the PPC, and configures the FPGA according to the first data frame type. The control parameters and the first networking data frame parameters can be flexibly configured according to application scenes and task requirements, so that the requirement on communication diversity can be met. Secondly, the DSP triggers a time slot timer according to the synchronous pulse generated by the interrupt controller to enter a networking mode, the DSP controls the FPGA to transmit data frames in the networking mode, and determines whether to switch into the networking mode or the data transmission mode according to the zone bit of the data frames transmitted in the networking mode, if the data transmission mode is switched into, the DSP controls the FPGA to transmit the data frames in the data transmission mode, and the data frames transmitted in the data transmission mode by the DSP are determined according to the data frames transmitted by the previous thread, so that frame handshaking is realized, and the reliability of TDMA data transmission among various communication modes can be improved. Secondly, if the data frame transmitted by the DSP in the data transmission mode is an end frame, switching to the networking mode, if the data frame transmitted by the DSP is not the end frame, starting an overtime timer according to the data frame, if the data frame transmission is not completed within the overtime waiting time matched with the currently transmitted data frame and configured in the overtime timer, determining that the state is abnormal, switching to the networking mode, otherwise, switching to the data transmission mode. Based on the time-out mechanism, the reliability of the TDMA data transmission between the various communication modes can be further improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic flow chart of a data transmission control method according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a networking send thread according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a networking receive thread according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a data transmission control system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.

As can be seen from the background art, in the prior art, TDMA data transmission in a private communication network can be implemented based on various hardware architectures and implementation manners, but to ensure communication reliability, the TDMA data transmission in each specific communication application scenario cannot be universally implemented, so that various application requirements of the private communication network cannot be met.

Therefore, the invention discloses a data transmission control method and a data transmission control system, which can meet the communication reliability, realize the universality in the aspect of TDMA data transmission in each specific communication application scene and fulfill the aim of meeting the application requirements of the diversity and the reliability of a special communication network.

As shown in fig. 1, a schematic flow chart of a data transmission control method disclosed in an embodiment of the present invention is shown, where the data transmission control method is applicable to a data transmission control system including a PowerPC (PowerPC, PPC), a Field Programmable Gate Array (FPGA), and a Digital Signal Processor (DSP) respectively connected to the PPC and the FPGA in a communication manner.

It should be noted that the whole communication process is divided into a networking mode and a data transmission mode, where the networking mode is responsible for maintaining network connectivity and node network access, and specific service data transmission is performed in the data transmission mode.

The data transmission control method specifically comprises the following steps:

step S101: and initializing the peripheral interface and the peripheral equipment of the DSP.

In step S101, the peripheral interface is a communication interface between the DSP and the PPC and the FPGA. The peripheral device includes a time slot timer, a timeout timer, and an interrupt controller.

In practical applications, the communication interface may include a Serial rapid Input Output interface (SRIO), a Peripheral Component Interconnect Express (PCIE), and a General Purpose Input Output interface (GPIO).

And the SRIO and the GPIO are interfaces between the DSP and the FPGA. PCIE is the interface between DSP and PPC.

The number of the GPIOs can be multiple, and the setting of the specific number of the GPIOs is set by a technician according to actual conditions.

Step S102: and the DSP receives the control parameters and the first group network data frame parameters sent by the PPC.

In step S102, the PPC determines the control parameter and the first network data frame parameter according to an application scenario and a task requirement. In the embodiment of the invention, the control parameters and the first group of network data frame parameters are determined by the PPC according to the application scene and the task requirement, and based on the control parameters and the first group of network data frame parameters, the control parameters and the first group of network data frame parameters can be flexibly configured according to the application scene and the task requirement, so that the requirement of communication diversity can be met.

Step S103: and the DSP configures the receiving and sending time slot of the time slot timer and the overtime waiting time of the overtime timer according to the control parameters.

In step S103, optionally, the control parameters include a TDMA time slot parameter, a data successful receipt Acknowledgement frame (ACK) timeout time, a data Clear To Send (CTS) timeout time, and the like. And the DSP configures the receiving and sending time slots of the time slot timer according to the TDMA time slot parameters, and configures the timeout waiting time of the timeout timer according to the CTS timeout time and the ACK timeout time in the control parameters.

It should be noted that, by configuring the timeout waiting time of the timeout timer according to the CTS timeout time, the ACK timeout time, and the like in the control parameter, when a certain data frame is transmitted subsequently, the timeout timer may determine whether a state abnormality exists according to the timeout waiting time matched with the data frame. Specifically, if the data frame transmission is not completed within the corresponding timeout period, the status exception may be confirmed. For example, when the data frame ACK is transmitted, if the transmission of the data frame ACK is not completed within the timeout waiting time of the ACK, it is determined that the state is abnormal. The reliability of TDMA data transmission between various communication modes can be improved by judging whether the transmission state of a data frame is normal or not in a manner of setting timeout waiting time for each data frame.

It should be noted that the slot timer is used to calculate and maintain the TDMA slots.

The overtime timer is used for detecting the overtime step and resetting.

Step S104: and the DSP determines a first data frame type according to the first networking data frame parameters, and configures the FPGA according to the first data frame type.

In a specific implementation manner of step S104, the DSP determines the type of the networking data frame according to a flag bit in the networking data frame parameter sent by the PPC, and configures the FPGA through SRIO.

It should be noted that the FPGA is used to implement a data transmission control implementation technique of encoding, decoding and modulation/demodulation.

SRIO is the interface between DSP and FPGA.

Step S105: and the DSP triggers the time slot timer according to the synchronous pulse generated by the interrupt controller to enter a networking mode.

In step S105, the networking mode includes a networking sending thread and a networking receiving thread.

In the process of executing step S105, it is waited for the external synchronous clock of the interrupt controller to trigger the slot timer. And the DSP determines whether to enter a networking sending thread or a networking receiving thread according to the current time slot number of the time slot timer. In practical applications, the DSP and the interrupt controller may be communicatively connected through a GPIO interface, for example, the GPIO1 may be used to implement the communication between the DSP and the interrupt controller.

Optionally, when the time slot timer is triggered, the DSP enters a corresponding networking mode according to the time slot number in the TDMA time slot parameter. If the time slot number indicates a sending time slot, the DSP enters a networking sending thread, and if the time slot number indicates a receiving time slot, the DSP enters a networking receiving thread.

It should be noted that the external synchronous clock may have several pulses, and the DSP only needs to respond to the first pulse, and the following pulses do not need to respond.

The external synchronous clock starts the time slot timer after the external pulse triggers the time slot timer for the first time, and closes the external interrupt responding to the interrupt controller.

It should be noted that, in the embodiment of the present invention, in a general case, by performing an initialization operation on the DSP, the DSP may enter a networking mode.

It should be noted that, when the DSP first enters the networking mode, it is determined whether the current time slot is the sending time slot or the receiving time slot according to the current time slot number.

If the first time slot is a sending time slot, the DSP sends a networking data frame stored locally, and can update the content of the data frame from the PPC at the first receiving time slot after the sending is finished.

And in the sending time slot, the DSP switches the radio frequency through the GPIO to turn on the sending interface and turn off the receiving interface (networking frequency point). And the DSP sends a mode switching instruction to the FPGA through the SRIO and sends a wave gate starting instruction to the FPGA through the GPIO, so that the FPGA sends data outwards.

Here, different GPIOs may be configured according to the reference requirement. For example, the DSP can switch the radio frequency through GPIO2 and GPIO3 to turn on the transmit interface and turn off the receive interface (networking frequency point). In the process that the DSP sends the mode switching instruction to the FPGA through the SRIO, a wave gate start instruction may be sent to the FPGA through the GPIO4, so that the FPGA sends data to the outside. It should be noted that, the reference numerals of GPIO1, GPIO2, GPIO3 and GPIO4 herein represent different communication interfaces to distinguish the different communication interfaces, but do not limit the names of the communication interfaces.

If the first time slot is a receiving time slot, the DSP enters a networking receiving thread, and executes the operation of sending a locally stored networking data frame when waiting for the arrival of a sending time slot specified by the time slot number of the DSP, and updating the content of the data frame from the PPC at the first receiving time slot after the sending is finished.

Step S106: and the DSP controls the FPGA to transmit data frames in a networking mode.

In step S106, the networking mode includes a networking sending thread and a networking receiving thread. Specifically, as shown in fig. 2, the networking sending thread includes:

step S201: and the DSP switches the radio frequency of the FPGA into a sending, receiving and closing of the networking frequency point.

In S201, the sending and receiving switch specifically means to turn on the sending interface and turn off the receiving interface.

Step S202: and the DSP sends a first mode switching instruction to the FPGA to switch the FPGA to a networking sending mode.

Step S203: and the DSP sends a wave gate starting instruction to the FPGA, and opens the wave gate to enable the FPGA to send a data frame.

In step S203, when the DSP is in the networking sending thread, the DSP sends a wave gate start instruction to the FPGA, so that the FPGA sends a locally stored data frame to other devices, and obtains a current latest data frame from the PPC in a first receiving time slot after the data frame is sent, and updates the current latest data frame to the FPGA through SRIO. Wherein the other devices herein are system external devices.

Step S204: and the DSP determines whether to switch into a networking receiving thread or a data receiving thread according to the zone bit of the data frame transmitted under the networking sending thread.

In step S204, the DSP determines the type of the data frame to be transmitted according to the flag bit of the data frame transmitted under the networking transmission thread, and subsequently determines whether to enter a networking reception thread or a data reception thread according to the determined type of the data frame. For example, when the flag bit of the transmitted data frame is 0, the transmitted data frame is determined to be a networking broadcast frame, and the first receiving time slot after the sending time slot is ended is determined to be switched into a networking receiving thread. When the flag bit of the transmission data frame is 1, determining that the transmission data frame is a Request To Send (RTS for short), and determining To switch into a data receiving thread after the sending time slot is finished. It should be noted that, if the initialized first time slot is a sending time slot, the sent time slot is a networking broadcast frame, and a data frame sent by a subsequent sending time slot may be a networking broadcast frame or a data transmission request frame, which is specifically determined according to whether a node has a data transmission requirement.

When the time slot timer controls the DSP to switch to the receiving time slot, the DSP switches into the networking receiving thread, as shown in fig. 3, the networking receiving thread includes:

step S301: and the DSP switches the radio frequency of the FPGA into a switch receiving and switching of networking frequency points.

In step S301, the transmitter reception instruction turns off the transmission interface and turns on the reception interface. The DSP corresponding to the foregoing embodiment may switch the rf-on transmitting interface and turn off the receiving interface through GPIO2 and GPIO3, and in this step, the DSP may switch the rf-off transmitting interface and turn on the receiving interface through GPIO2 and GPIO 3.

Step S302: and the DSP sends a second mode switching instruction to the FPGA to switch the FPGA to a networking receiving mode.

In step S302, the DSP switches the FPGA mode through SRIO.

Step S303: and the DSP sends a wave gate ending instruction to the FPGA to close the wave gate.

The DSP corresponding to the foregoing embodiment may send a gate start instruction to the FPGA through GPIO4, in which step the DSP may send a gate end instruction to the FPGA through GPIO 4.

Step S304: the DSP determines whether to switch into the networking sending thread or the data sending thread according to the zone bit of the data frame transmitted under the networking receiving thread.

Optionally, when the DSP is in a networking receiving thread, the received data frame sent by the FPGA is analyzed, and the analyzed data frame is uploaded to the PPC. Specifically, after the radio frequency RF of the FPGA receives a data frame sent by another device, the data frame is decoded and converted into a baseband signal by the FPGA, the received data frame sent by the FPGA is analyzed, the analyzed data frame is sent to the DSP through the SRIO, and the DSP judges an operation to be executed according to a flag bit of the received data frame and uploads the data frame to the PPC. In this way, recording and display of data frames can be achieved on the PPC.

It should be noted that, if the DSP receives a second set of network data frame parameters issued by the PPC, the DSP determines a second data frame type according to the second set of network data frame parameters, and configures the FPGA according to the second data frame type, and then the DSP controls the FPGA to transmit data frames by using data frames matched with the second data frame type, so as to implement flexible switching of data frame types. In addition, the second networking data frame parameter here indicates a networking data frame parameter whose data frame type is different from the data frame type corresponding to the first networking data frame parameter. And when the second networking data frame parameter is not received, the data frame type corresponding to the first networking data frame parameter is continuously adopted to execute the networking mode or the data transmission mode.

Step S107: and the DSP determines whether to switch into the networking mode or the data transmission mode according to the zone bit of the data frame transmitted in the networking mode, and if the data transmission mode is switched into, the step S108 is executed.

Step S108: and the DSP controls the FPGA to transmit data frames in a digital transmission mode.

In step S108, the data transfer mode includes a data sending thread and a data receiving thread.

It should be noted that, in the data transfer mode, the data sending thread and the data receiving thread are switched no longer in accordance with the control of the slot timer.

And sending various transmission data frames in the data sending thread, wherein different transmission data frames correspond to different states.

The data frames transmitted in the data transmission thread include a CTS, a content data frame, an ACK, a reply full frame ACK BUFF for data unsuccessful reception, and a data transmission END frame END.

The content data frame may be understood as the transmitted valid data or the transmitted target data, for example, the content data frame may be control information, data information, and the like.

Specifically, the data sending thread includes:

a1, the DSP switches the radio frequency of the FPGA into the sending, receiving and closing of the data transmission frequency point.

And A2, the DSP sends a third mode switching instruction to the FPGA to switch the FPGA to the data sending mode.

A3, the DSP sends a wave gate starting instruction to the FPGA to open the wave gate.

A4, the DSP determines the data frame to be sent according to the data frame transmitted by the previous thread.

A5, when the data frame sent by DSP is the end frame, switching to network mode.

A6, when the data frame is not the end frame, the DSP starts the overtime timer according to the data frame.

A7, if the data frame transmission is not completed within the overtime waiting time matched with the currently sent data frame configured in the overtime timer, determining the state is abnormal, switching to the networking mode, otherwise, switching to the data receiving thread.

The data receiving thread comprises:

and B1, the DSP switches the radio frequency of the FPGA into a switch receiving and transmitting data transmission frequency points.

And B2, the DSP sends a fourth mode switching instruction to the FPGA to switch the FPGA to the data receiving mode.

And B3, the DSP sends a wave gate ending instruction to the FPGA to close the wave gate.

B4, the DSP determines the received data frame based on the data frame transmitted by the previous thread.

B5, the DSP starts a timeout timer based on the received data frame.

B6, if the data frame is not received within the overtime waiting time matched with the current received data frame configured in the overtime timer, determining that the state is abnormal, and switching to the networking mode, otherwise, switching to the data sending thread when the received data frame is not the end frame by the DSP.

Optionally, in the data receiving thread, if the local cache is full, the data receiving thread is switched to the data sending thread, and correspondingly, the DSP unsuccessfully receives the reply full frame when the data sending thread sends data.

Step S109: and judging whether the data frame transmitted by the DSP in the digital transmission mode is an end frame, if so, switching to a networking mode, and if not, executing the step S110.

In step S109, the data frame transmitted by the DSP in the digital transmission mode is determined according to the data frame transmitted by the previous thread.

In a specific implementation, the types of data frames transmitted in the data sending thread include CTS, content data frame, ACK, ACKBUFF, and END. When the data frame received by the DSP in the networking receiving thread is RTS, a CTS is sent in the data sending thread; when the data frame received by the DSP at the data receiving thread is CTS, the DSP sends a content data frame at the data sending thread; when the data frame received by the DSP in the networking receiving thread is a content data frame, sending ACK (acknowledgement character) in the data sending thread; the DSP sends ACK BUFF if the local storage data buffer is full in the process of receiving the content data frame by the data receiving thread; and when the DSP finishes sending the content data frame and the data receiving thread receives the ACK, the END is sent.

The data frame received in the data receiving thread is the same as the data frame used in the data sending thread.

Step S110, starting the timeout timer according to the data frame.

Step S111, if the data frame transmission is not completed within the timeout waiting time matched with the currently transmitted data frame and configured in the timeout timer, determining that the state is abnormal, and switching to a networking mode, otherwise, switching to a data transmission mode.

In step S111, it should be noted that, when setting the control parameter issued by the PPC, different timeout periods may be set for different data frames. Such as the timeout time corresponding to CTS, the timeout time corresponding to ACK, the timeout time of the content data frame, etc. in the control parameters, and then the timeout timer sets the corresponding timeout waiting time for different data frames.

Whether the data frame transmission is finished within the timeout waiting time matched with the currently transmitted data frame is determined, if the data frame transmission is not finished, the state is determined to be abnormal, and the purpose of improving the reliability of the data transmission by utilizing the timeout mechanism is achieved.

It should be noted that, when the data transfer mode is switched to the networking mode, the DSP enters the networking mode entered when the timeslot timer is triggered, and otherwise, switches from the sending thread to the receiving thread or switches from the receiving thread to the sending thread every time the DSP switches. In addition, the type of each transmission data frame is the same as the data frame type determined according to the networking data frame parameters.

In the process of specifically implementing step S107 to step S111, after the data transmission mode is switched to, for different transmission data frames, the corresponding timeout waiting time in the timeout timer is started. The following examples illustrate:

if the data frame received by the DSP in the networking receiving thread is RTS, the DSP sends CTS when switching to a data sending thread after the receiving time slot is finished, the DSP detects whether the CTS is overtime or not according to the overtime waiting time of the CTS, and if the CTS is overtime, the DSP is switched to a networking mode by the data sending thread; if not, the DSP is switched into a data receiving thread by the data sending thread after the CTS is sent, receives the content data frame, subsequently starts and starts the timeout waiting time matched with the content data frame in the timeout timer, and carries out timeout judgment.

In the process of receiving the content data frame, if the local data is fully stored, the DSP sends an ACK BUFF to the FPGA in the data sending thread, the DSP detects whether ACKBUFF is overtime or not according to the overtime waiting time of the ACK BUFF, and if the ACKBUFF is overtime, the DSP is switched into a networking mode by the data sending thread; if not, the DSP is switched into a data receiving thread by the data sending thread after the ACKBUFF sending is finished.

After the data sending thread sends the content data frame, the DSP receives ACK (acknowledgement character) in the data receiving thread, the DSP detects whether the time is out or not according to the overtime waiting time of the ACK, and if the time is out, the DSP is switched into a networking mode by the data receiving thread; if not, the DSP is switched into the data sending thread by the data receiving thread after the data frame sending is finished.

The embodiment of the invention discloses a data transmission control method, under the hardware architecture of a PPC processor, a DSP processor and an FPGA processor, the DSP adopts a multithreading frame handshake and an overtime control mechanism to realize the data transmission control of a TDMA link layer and control the switching between TDMA data transmission flows among various communication modes, and the stable and controllable work flow among the communication modes is ensured, so that the reliability and the communication diversity of data transmission are ensured, and the reliability and the communication diversity of TDMA data transmission among the various communication modes are simultaneously met.

The embodiment of the invention discloses a data transmission control method, under the PPC, DSP and FPGA hardware architecture, firstly, the DSP configures the receiving and sending time slot of a time slot timer and the overtime waiting time of an overtime timer according to control parameters issued by the PPC, determines a first data frame type according to first networking data frame parameters issued by the PPC, and configures the FPGA according to the first data frame type. The control parameters and the first networking data frame parameters can be flexibly configured according to application scenes and task requirements, so that the requirement on communication diversity can be met. Secondly, the DSP triggers a time slot timer according to the synchronous pulse generated by the interrupt controller to enter a networking mode, the DSP controls the FPGA to transmit a data frame in the networking mode, and determines whether to switch into the networking mode or the data transmission mode according to a zone bit of the data frame transmitted in the networking mode, if the data frame is switched into the data transmission mode, the DSP controls the FPGA to transmit the data frame in the data transmission mode, and the data frame transmitted in the data transmission mode by the DSP is determined according to the data frame transmitted by the previous thread and is equivalent to frame handshake, so that the reliability of TDMA data transmission among various communication modes can be improved. Secondly, if the data frame transmitted by the DSP in the data transmission mode is an end frame, switching to the networking mode, if the data frame transmitted by the DSP is not the end frame, starting an overtime timer according to the data frame, if the data frame transmission is not completed within the overtime waiting time matched with the currently transmitted data frame and configured in the overtime timer, determining that the state is abnormal, switching to the networking mode, otherwise, switching to the data transmission mode. Based on the time-out mechanism, the purpose of improving the reliability of TDMA data transmission among various communication modes can be achieved.

Based on the data transmission control method disclosed in the embodiment of the present invention, the embodiment of the present invention also correspondingly discloses a data transmission control system, as shown in fig. 4, which shows a schematic structural diagram of the data transmission control system, and the data transmission control system 400 mainly includes:

PPC401, DSP402 and FPGA 403.

The peripheral interface of the DSP402 is a communication interface between the DSP402 and the PPC401 and the FPGA 403.

It should be noted that the peripheral devices and the peripheral interfaces of the DSP402 need to be initialized. And the peripheral interface is a communication interface between the DSP and the PPC and the FPGA. The peripheral device includes a time slot timer, a timeout timer, and an interrupt controller.

It should be noted that the communication interface includes SRIO, PCIE, and GPIO.

And the SRIO and the GPIO are interfaces between the DSP and the FPGA.

PCIE is the interface between DSP and PPC.

The number of the GPIOs can be multiple, and the setting of the specific number of the GPIOs is set by a technician according to actual conditions.

The PPC401 is configured to determine a control parameter and a first group network data frame parameter according to an application scenario and a task requirement, and issue the control parameter and the first group network data frame parameter.

The initialized DSP402 is configured to receive a control parameter and a first set of network data frame parameters sent by the PPC 401; configuring a receiving and sending time slot of the time slot timer and the overtime waiting time of the overtime timer according to the control parameters; the DSP402 determines a first data frame type according to the first networking data frame parameters, and configures the FPGA403 according to the first data frame type; the DSP402 triggers the time slot timer according to the synchronous pulse generated by the interrupt controller, and enters a networking mode; the networking mode comprises a networking sending thread and a networking receiving thread, and the DSP402 determines whether to enter the networking sending thread or the networking receiving thread according to the current time slot number of the time slot timer; the DSP402 controls the FPGA403 to transmit data frames in a networking mode; the DSP402 determines whether to switch into a networking mode or a data transmission mode according to a zone bit of a data frame transmitted in the networking mode, wherein the data transmission mode comprises a data sending thread and a data receiving thread; if the data transmission mode is switched into, the DSP402 controls the FPGA403 to transmit data frames in the data transmission mode; when the data frame transmitted by the DSP402 in the data transmission mode is an end frame, switching into a networking mode; when the data frame transmitted by the DSP in the data transmission mode is not the end frame, starting the overtime timer according to the data frame; the data frame transmitted by the DSP402 in the digital transmission mode is determined according to the data frame transmitted by the previous thread; if the data frame transmission is not completed within the timeout waiting time matched with the currently transmitted data frame and configured in the timeout timer, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data transmission mode.

When the data transmission mode is switched into the networking mode, the DSP402 enters the networking mode entered when the timeslot timer is triggered, and otherwise, switches from the sending thread to the receiving thread or from the receiving thread to the sending thread every time the switching is performed.

Optionally, the DSP402 is further configured to, if the DSP receives a second set of network data frame parameters issued by the PPC, determine a second data frame type according to the second set of network data frame parameters, configure the FPGA according to the second data frame type, and subsequently, when the DSP controls the FPGA to transmit a data frame, use a data frame matched with the second data frame type.

The FPGA403 is configured to transmit various data frames under the control of the DSP 402.

In the networking sending thread, the DSP402 is configured to switch the radio frequency of the FPGA403 into a sending-receiving switch of a networking frequency point; sending a first mode switching instruction to the FPGA403 to switch the FPGA403 to a networking sending mode; sending a wave gate starting instruction to the FPGA403, and opening a wave gate to enable the FPGA403 to send a data frame; and determining whether to switch into a networking receiving thread or a data receiving thread according to the zone bit of the data frame transmitted under the networking sending thread.

In the networking receiving thread, the DSP402 is configured to switch the radio frequency of the FPGA to a switch receiving of a networking frequency point; sending a second mode switching instruction to the FPGA to switch the FPGA to a networking receiving mode; and sending a wave gate ending instruction to the FPGA to close the wave gate, and determining whether to switch into the networking sending thread or the data sending thread according to the zone bit of the data frame transmitted under the networking receiving thread.

Optionally, in the networking receiving thread, the DSP is further configured to upload the received data frame to the PPC.

During a data transmission thread, the DSP402 is configured to switch the radio frequency of the FPGA to a transmit-receive switch of a data transmission frequency point; sending a third mode switching instruction to the FPGA to switch the FPGA to a data sending mode; sending a wave gate starting instruction to the FPGA, and opening a wave gate; determining a transmitted data frame according to the data frame transmitted by the previous thread; when the transmitted data frame is an end frame, switching into a networking mode, and when the transmitted data frame is not the end frame, starting the timeout timer according to the transmitted data frame; if the data frame transmission is not completed within the timeout waiting time configured in the timeout timer and matched with the currently sent data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data receiving thread.

During a data receiving thread, the DSP402 is configured to switch the radio frequency of the FPGA403 to a transmit/receive switch of a data transmission frequency point; sending a fourth mode switching instruction to the FPGA403 to switch the FPGA403 to a data receiving mode; sending a wave gate ending instruction to the FPGA403 to close the wave gate; determining the received data frame according to the data frame transmitted by the previous thread; starting the timeout timer according to the received data; if the data frame is not received within the timeout waiting time which is configured in the timeout timer and matched with the currently received data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data sending thread when the received data frame is not an end frame.

Optionally, in the data receiving thread, the DSP402 is further configured to switch to the data sending thread if the local cache is full in the process of receiving the content data frame by the data receiving thread.

Accordingly, the DSP fails to receive the reply full frame when the data sending thread sends data.

The embodiment of the invention discloses a data transmission control system, which is characterized in that under the hardware architecture of a PPC processor, a DSP processor and an FPGA processor, firstly, a receiving and sending time slot of a time slot timer and the overtime waiting time of an overtime timer are configured through the DSP according to control parameters issued by the PPC, a first data frame type is determined according to first networking data frame parameters issued by the PPC, and the FPGA is configured according to the first data frame type. The control parameters and the first networking data frame parameters can be flexibly configured according to application scenes and task requirements, so that the requirement on communication diversity can be met. Secondly, the DSP triggers a time slot timer according to the synchronous pulse generated by the interrupt controller to enter a networking mode, the DSP controls the FPGA to transmit data frames in the networking mode, and determines whether to switch into the networking mode or the data transmission mode according to the zone bit of the data frames transmitted in the networking mode, if the data transmission mode is switched into, the DSP controls the FPGA to transmit the data frames in the data transmission mode, and the data frames transmitted in the data transmission mode by the DSP are determined according to the data frames transmitted by the previous thread, so that frame handshaking is realized, and the reliability of TDMA data transmission among various communication modes can be improved. Secondly, if the data frame transmitted by the DSP in the data transmission mode is an end frame, switching to the networking mode, if the data frame transmitted by the DSP is not the end frame, starting an overtime timer according to the data frame, if the data frame transmission is not completed within the overtime waiting time matched with the currently transmitted data frame and configured in the overtime timer, determining that the state is abnormal, switching to the networking mode, otherwise, switching to the data transmission mode. Based on the time-out mechanism, the reliability of the TDMA data transmission between the various communication modes can be further improved.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The above are merely examples of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (10)

1. A data transmission control method is characterized in that the method is suitable for a data transmission control system comprising a Macintonia tower processor PPC, a field programmable gate array FPGA and a digital signal processor DSP which is respectively in communication connection with the PPC and the FPGA, and the method comprises the following steps:

initializing a peripheral interface and peripheral equipment of the DSP, wherein the peripheral interface is a communication interface between the DSP and the PPC and between the DSP and the FPGA respectively, and the peripheral equipment comprises a time slot timer, an overtime timer and an interrupt controller;

the DSP receives the control parameters and the first group network data frame parameters issued by the PPC; the PPC determines the control parameters and the first network data frame parameters according to application scenes and task requirements;

the DSP configures the receiving and sending time slot of the time slot timer and the overtime waiting time of the overtime timer according to the control parameters;

the DSP determines a first data frame type according to the first networking data frame parameters, and configures the FPGA according to the first data frame type;

the DSP triggers the time slot timer according to the synchronous pulse generated by the interrupt controller, and enters a networking mode; the networking mode comprises a networking sending thread and a networking receiving thread, and the DSP determines whether to enter the networking sending thread or the networking receiving thread according to the current time slot number of the time slot timer;

the DSP controls the FPGA to transmit data frames in a networking mode;

the DSP determines whether to switch into a networking mode or a data transmission mode according to a zone bit of a data frame transmitted in the networking mode, wherein the data transmission mode comprises a data sending thread and a data receiving thread;

if the data transmission mode is switched into, the DSP controls the FPGA to transmit data frames in the data transmission mode;

when the data frame transmitted by the DSP in the data transmission mode is an end frame, switching into a networking mode;

when the data frame transmitted by the DSP in the data transmission mode is not the end frame, starting the overtime timer according to the data frame; the data frame transmitted by the DSP in the digital transmission mode is determined according to the data frame transmitted by the previous thread;

if the DSP does not finish the data frame transmission within the timeout waiting time which is configured in the timeout timer and matched with the currently transmitted data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data transmission mode;

when the data transmission mode is switched into the networking mode, the DSP enters the networking mode which is entered when the time slot timer is triggered, and under other conditions, the DSP is switched from a sending thread to a receiving thread or from the receiving thread to the sending thread during each switching.

2. The method of claim 1,

the networking sending thread comprises the following steps:

the DSP switches the radio frequency of the FPGA into a sending, receiving and closing of networking frequency points;

the DSP sends a first mode switching instruction to the FPGA to enable the FPGA to be switched to a networking sending mode;

the DSP sends a wave gate starting instruction to the FPGA, and the wave gate is opened to enable the FPGA to send a data frame;

the DSP determines whether to switch into a networking receiving thread or a data receiving thread according to the zone bit of the data frame transmitted under the networking sending thread;

the networking receiving thread comprises the following steps:

the DSP switches the radio frequency of the FPGA into a switch receiving and switching of networking frequency points;

the DSP sends a second mode switching instruction to the FPGA to enable the FPGA to be switched to a networking receiving mode;

the DSP sends a wave gate ending instruction to the FPGA to close the wave gate;

the DSP determines whether to switch into a networking sending thread or a data sending thread according to the zone bit of the data frame transmitted under the networking receiving thread;

the data sending thread comprises:

the DSP switches the radio frequency of the FPGA into a sending, receiving and closing of a data transmission frequency point;

the DSP sends a third mode switching instruction to the FPGA to enable the FPGA to be switched to a data sending mode;

the DSP sends a wave gate starting instruction to the FPGA and opens a wave gate;

the DSP determines a transmitted data frame according to the data frame transmitted by the previous thread;

when the data frame sent by the DSP is an end frame, switching into a networking mode;

when the transmitted data frame is not the end frame, the DSP starts the overtime timer according to the transmitted data frame;

if the DSP does not finish the data frame transmission within the timeout waiting time which is configured in the timeout timer and matched with the currently sent data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data receiving thread;

the data receiving thread comprises:

the DSP switches the radio frequency of the FPGA into a switch receiving and switching of a data transmission frequency point;

the DSP sends a fourth mode switching instruction to the FPGA to enable the FPGA to be switched to a data receiving mode;

the DSP sends a wave gate ending instruction to the FPGA to close the wave gate;

the DSP determines the received data frame according to the data frame transmitted by the previous thread;

the DSP starts the overtime timer according to the received data frame;

if the DSP does not receive the data frame within the timeout waiting time which is configured in the timeout timer and matched with the currently received data frame, determining that the state is abnormal, and switching to a networking mode, otherwise, switching to a data sending thread when the received data frame is not the end frame.

3. The method of claim 2,

the data receiving thread further comprises:

if the local cache is full in the process that the DSP receives the content data frame in the data receiving thread, switching to a data sending thread;

accordingly, the DSP fails to receive the reply full frame when the data sending thread sends data.

4. The method of claim 1, further comprising:

if the DSP receives a second set of network data frame parameters issued by the PPC, the DSP determines a second data frame type according to the second set of network data frame parameters, and configures the FPGA according to the second data frame type, and subsequently, the DSP controls the FPGA to adopt a data frame matched with the second data frame type when the FPGA transmits data frames.

5. The method of any of claims 1 to 4, further comprising:

and the DSP uploads the received data frame to the PPC in a networking receiving thread.

6. A data transmission control system, characterized in that the data transmission control system comprises: the device comprises a Macinton tower processor PPC, a field programmable gate array FPGA and a digital signal processor DSP which is respectively in communication connection with the PPC and the FPGA;

the PPC is used for determining control parameters and first group network data frame parameters according to application scenes and task requirements and issuing the control parameters and the first group network data frame parameters;

the peripheral interface of the DSP is a communication interface between the DSP and the PPC and the FPGA respectively, and the peripheral equipment of the DSP comprises a time slot timer, an overtime timer and an interrupt controller;

the initialized DSP is used for receiving the control parameters and the first group of network data frame parameters sent by the PPC; configuring a receiving and sending time slot of the time slot timer and the overtime waiting time of the overtime timer according to the control parameters; the DSP determines a first data frame type according to the first networking data frame parameters, and configures the FPGA according to the first data frame type; the DSP triggers the time slot timer according to the synchronous pulse generated by the interrupt controller, and enters a networking mode; the networking mode comprises a networking sending thread and a networking receiving thread, and the DSP determines whether to enter the networking sending thread or the networking receiving thread according to the current time slot number of the time slot timer; the DSP controls the FPGA to transmit data frames in a networking mode; the DSP determines whether to switch into a networking mode or a data transmission mode according to a zone bit of a data frame transmitted in the networking mode, wherein the data transmission mode comprises a data sending thread and a data receiving thread; if the data transmission mode is switched into, the DSP controls the FPGA to transmit data frames in the data transmission mode; when the data frame transmitted by the DSP in the data transmission mode is an end frame, switching into a networking mode; when the data frame transmitted by the DSP in the data transmission mode is not the end frame, starting the overtime timer according to the data frame; the data frame transmitted by the DSP in the digital transmission mode is determined according to the data frame transmitted by the previous thread; if the DSP does not finish the data frame transmission within the timeout waiting time which is configured in the timeout timer and matched with the currently transmitted data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data transmission mode;

when the data transmission mode is switched into the networking mode, the DSP enters the networking mode which is entered when the time slot timer is triggered, and under other conditions, the DSP is switched from a sending thread to a receiving thread or from the receiving thread to the sending thread during each switching;

and the FPGA is used for transmitting various data frames under the control of the DSP.

7. The system of claim 6, wherein in the networking send thread, the DSP is configured to:

switching the radio frequency of the FPGA into a sending-receiving switch of a networking frequency point; sending a first mode switching instruction to the FPGA to enable the FPGA to be switched to a networking sending mode; sending a wave gate starting instruction to the FPGA, and opening a wave gate to enable the FPGA to send a data frame; determining whether to switch into a networking receiving thread or a data receiving thread according to a zone bit of a data frame transmitted under the networking sending thread;

in the networking receiving thread, the DSP is configured to:

switching the radio frequency of the FPGA to a transmitting switch receiving of networking frequency points; sending a second mode switching instruction to the FPGA to switch the FPGA to a networking receiving mode; sending a wave gate ending instruction to the FPGA to close the wave gate, and determining whether to switch into a networking sending thread or a data sending thread according to a flag bit of a data frame transmitted under the networking receiving thread;

in the data sending thread, the DSP is configured to:

switching the radio frequency of the FPGA into a sending-receiving switch of a data transmission frequency point; sending a third mode switching instruction to the FPGA to switch the FPGA to a data sending mode; sending a wave gate starting instruction to the FPGA, and opening a wave gate; determining a transmitted data frame according to the data frame transmitted by the previous thread; when the transmitted data frame is an end frame, switching into a networking mode, and when the transmitted data frame is not the end frame, starting the timeout timer according to the transmitted data frame; if the DSP does not finish the data frame transmission within the timeout waiting time which is configured in the timeout timer and matched with the currently sent data frame, determining that the state is abnormal, and switching into a networking mode, otherwise, switching into a data receiving thread;

in a data receiving thread, the DSP, configured to:

switching on and off a transmitter for switching the radio frequency of the FPGA into a data transmission frequency point; sending a fourth mode switching instruction to the FPGA to switch the FPGA to a data receiving mode; sending a wave gate ending instruction to the FPGA to close the wave gate; determining a received data frame according to a data frame transmitted by a previous thread; starting the overtime timer according to the received data frame; if the DSP does not receive the data frame within the timeout waiting time which is configured in the timeout timer and matched with the currently received data frame, determining that the state is abnormal, and switching to a networking mode, otherwise, switching to a data sending thread when the received data frame is not the end frame.

8. The system of claim 7, wherein in the data receiving thread, the DSP is further configured to switch to the data sending thread if the local cache is full during the data receiving thread receiving the content data frame,

accordingly, the DSP fails to receive the reply full frame when the data sending thread sends data.

9. The system of claim 6, wherein the DSP is further configured to:

if the DSP receives a second set of network data frame parameters issued by the PPC, the DSP determines a second data frame type according to the second set of network data frame parameters, and configures the FPGA according to the second data frame type, and subsequently, the DSP controls the FPGA to adopt a data frame matched with the second data frame type when the FPGA transmits data frames.

10. The system of any of claims 6 to 8, wherein in a networking receive thread, the DSP is further configured to upload received data frames to the PPC.

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