CN110391863A - A kind of data transfer control method and system - Google Patents
A kind of data transfer control method and system Download PDFInfo
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- CN110391863A CN110391863A CN201910823324.8A CN201910823324A CN110391863A CN 110391863 A CN110391863 A CN 110391863A CN 201910823324 A CN201910823324 A CN 201910823324A CN 110391863 A CN110391863 A CN 110391863A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1694—Allocation of channels in TDM/TDMA networks, e.g. distributed multiplexers
Abstract
The invention discloses a kind of data transfer control method and systems, the data transfer control system includes PPC, FPGA, and the digital signal processor DSP communicated to connect respectively with PPC and FPGA, the data transfer control method, in PPC processor, under dsp processor and FPGA processor hardware structure, it is shaken hands by DSP using thread frame and realizes the Data Transmission Controlling of TDMA link layer with overtime control mechanism, and the switching between the TDMA data transmission stream journey between the various communication patterns of control, ensure that the workflow between each communication pattern is stably and controllable, so that it is guaranteed that the reliability and communication diversity of data transmission, realize while meeting the reliability and communication diversity of the transmission of the TDMA data between various communication patterns.
Description
Technical field
The present invention relates to fields of communication technology, more specifically to a kind of data transfer control method and system.
Background technique
Dedicated communications network is that relevant department or unit are built because business needs, the telecommunications generally used for inside
Net, such as emergency communication net, electric power, subway private wire network etc..Time division multiple access technology (Time Division Multiple
Access, TDMA) be in a kind of communication technology and dedicated communications network for realizing shared transmission medium or network using than
Wide multiple access technique provides the implementation for being used in conjunction with the same transmission medium for multi-user.
In the prior art, the transmission of TDMA data is realized in dedicated communications network, can be based on diversified hardware frame
Structure and implementation, meanwhile, in order to meet data transmission credibility requirement, the Data Transmission Controlling side of various dedicated communications networks
Formula is confined to particular communications application scene.But the communications applications scene of various dedicated communications networks is not uniquely, this is just
Application demand is proposed to the communication diversity of dedicated communications network, can meet data transmission simultaneously there is presently no one kind can
By property and communicate multifarious data transfer control method.
Summary of the invention
In view of this, the present invention provides a kind of data transfer control method and system, to realize each dedicated communications network
Between TDMA data transmissions enough meet data transmission credibility simultaneously and communicate diversity.
To achieve the goals above, it is proposed that scheme it is as follows:
First aspect present invention discloses a kind of data transfer control method, is suitable for including Macintosh processor PPC, now
Field programmable gate array FPGA and the respectively number with the PPC and FPGA digital signal processor DSP communicated to connect
According to transmission control system, which comprises
The Peripheral Interface and peripheral apparatus of the DSP are initialized, the Peripheral Interface is the DSP and the PPC and institute
The communication interface between FPGA is stated, the peripheral apparatus includes slot timer, overtime timer and interrupt control unit；
The DSP receives the control parameter that the PPC is issued and first group of net data frame parameter；The PPC is according to application
Scene and mission requirements determine the control parameter and first group of net data frame parameter；
The DSP configures the transmitting-receiving time slot and the overtime timer of the slot timer according to the control parameter
The waiting-timeout time；
The DSP determines the first data frame type according to first group of net data frame parameter, and according to first number
According to FPGA described in frame type configuration；
The DSP triggers the slot timer according to the lock-out pulse that the interrupt control unit generates, into networking mould
Formula；Networking model includes that networking transmission thread and networking receiving thread, the DSP are presently according to the slot timer
Timeslot number determination is to enter networking to send thread or enter networking receiving thread；
The DSP controls the FPGA transmitting data frame under networking model；
The DSP is determined according to the flag bit of institute's transmitting data frame under networking model to be switched in networking model or cuts
Number arq mode is changed to, number arq mode includes data transmission line journey and data receiving thread；
If switching in several arq modes, the DSP controls the FPGA transmitting data frame under several arq modes；
The DSP under several arq modes institute's transmitting data frame be end frame when, switch in networking model；
The DSP is fixed according to the data frame starting time-out when institute's transmitting data frame is not end frame under several arq modes
When device；DSP institute's transmitting data frame under several arq modes is determined according to the data frame that a upper thread transmits；
If it is being configured in the overtime timer, with it is not complete in the currently transmitted data frame institute matched waiting-timeout time
At data frame transfer, abnormal state is determined, switch in networking model, otherwise, switch in several arq modes；
Wherein, when several arq modes switch in networking model, the DSP enters to be entered when triggering the slot timer
Networking model, under other situations, receiving thread is switched to from sending thread when switching every time, alternatively, switching from receiving thread
To transmission thread.
Optionally, networking transmission thread includes:
The hair that the radio frequency of the FPGA is switched to networking frequency point is opened receipts and closed by the DSP；
The DSP sends first mode switching command to the FPGA, and the FPGA is made to be switched to networking sending mode；
The DSP opens wave door to the FPGA send wave door initial order, and the FPGA is made to send data frame；
The DSP is to switch in networking to receive line according to the flag bit determination of institute's transmitting data frame in the case where networking sends thread
Journey still switches in data receiver thread；
Networking receiving thread includes:
The hair that the radio frequency of the FPGA is switched to networking frequency point is closed to receive by the DSP to be opened；
The DSP sends second mode switching command to the FPGA, and the FPGA is made to be switched to networking reception pattern；
The DSP closes wave door to the FPGA send wave door END instruction；
The DSP according under networking receiving thread the flag bit determination of institute's transmitting data frame be switch in networking send line
Journey still switches in data transmission line journey；
Data transmission line journey includes:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is opened receipts and closed by the DSP；
The DSP sends the third mode switching command to the FPGA, and the FPGA is made to be switched to data transmission modes；
The DSP opens wave door to the FPGA send wave door initial order；
The DSP determines transmitted data frame according to the data frame that a upper thread transmits；
When data frame transmitted by the DSP is end frame, networking model is switched in；
When transmitted data frame is not end frame, the DSP starts described super the DSP according to transmitted data frame
When timer；
If it is being configured in the overtime timer, with it is not complete in the currently transmitted data frame institute matched waiting-timeout time
At data frame transfer, abnormal state is determined, switch in networking model, otherwise, switch in data receiver thread；
Data receiver thread includes:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is closed to receive by the DSP to be opened；
The DSP sends fourth mode switching command to the FPGA, and the FPGA is made to be switched to data receiver mode；
The DSP closes wave door to the FPGA send wave door END instruction；
The DSP determines received data frame according to the data frame that a upper thread transmits；
The DSP starts the overtime timer according to received data frame；
If it is being configured in the overtime timer, with do not connect in the currently received data frame institute matched waiting-timeout time
Data frame is received, determines abnormal state, switches in networking model, otherwise, the DSP is not end frame in the data frame received
When, switch in data transmission line journey.
Optionally, data receiver thread further include:
If local cache has been expired, and data transmission line is switched in during data receiver thread reception content data frame
Journey；
Correspondingly, sending data in data transmission line journey is not successfully received answer full frame.
Optionally, further includes: if the DSP receives second group of net data frame parameter that the PPC is issued, the DSP
The second data frame type is determined according to second group of net data frame parameter, and according to second data frame type configuration
FPGA, the subsequent DSP are used and the matched data frame of the second data frame type when controlling the FPGA transmitting data frame.
Optionally, further includes: the DSP is uploaded to the PPC in networking receiving thread, by the data frame received.
Second aspect of the present invention discloses a kind of data transfer control system, and the data transfer control system includes: wheat
Quintar processor PPC, on-site programmable gate array FPGA and the number communicated to connect respectively with the PPC and FPGA
Signal processor DSP；
The PPC, for determining control parameter and first group of net data frame parameter according to application scenarios and mission requirements, and
It issues；
Communication interface of the Peripheral Interface of the DSP between the DSP and the PPC and the FPGA, the DSP's
Peripheral apparatus includes slot timer, overtime timer and interrupt control unit；
The DSP after initialization, for receiving the control parameter and first group of net data frame parameter that the PPC is issued；
The waiting-timeout time of the transmitting-receiving time slot and the overtime timer of the slot timer is configured according to the control parameter；Institute
It states DSP and the first data frame type is determined according to first group of net data frame parameter, and matched according to first data frame type
Set the FPGA；The DS triggers the slot timer according to the lock-out pulse that the interrupt control unit generates, into networking
Mode；Networking model includes that networking transmission thread and networking receiving thread, the DSP are presently according to the slot timer
Timeslot number determination be enter networking send thread or enter networking receiving thread；The DSP controls institute under networking model
State FPGA transmitting data frame；The DSP according under networking model the flag bit determination of institute's transmitting data frame be to switch in networking
Mode still switches in several arq modes, and number arq mode includes data transmission line journey and data receiving thread；If switching in number passes mould
Formula, the DSP control the FPGA transmitting data frame under several arq modes；DSP institute's transmitting data frame under several arq modes
When for end frame, networking model is switched in；The DSP is when institute's transmitting data frame is not end frame under several arq modes, according to number
Start the overtime timer according to frame；The DSP number that institute's transmitting data frame is transmitted according to a upper thread under several arq modes
It is determined according to frame；If in data frame institute configured in the overtime timer and currently transmitted matched waiting-timeout time not
Data frame transfer is completed, abnormal state is determined, switches in networking model, otherwise, switch in several arq modes；
Wherein, when several arq modes switch in networking model, the DSP enters to be entered when triggering the slot timer
Networking model, under other situations, receiving thread is switched to from sending thread when switching every time, alternatively, switching from receiving thread
To transmission thread；
The FPGA, for transmitting various data frames under the control of the DSP.
Optionally, it is sent in thread in networking, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to networking frequency point is opened receipts to close；First mode switching is sent to the FPGA to refer to
It enables, the FPGA is made to be switched to networking sending mode；To the FPGA send wave door initial order, wave door is opened, is made described
FPGA sends data frame；Flag bit determination according to institute's transmitting data frame in the case where networking sends thread is to switch in networking to receive line
Journey still switches in data receiver thread；
In networking receiving thread, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to networking frequency point is closed to receive and is opened；The magical finger of second mode is sent to the FPGA
It enables, the FPGA is made to be switched to networking reception pattern；To the FPGA send wave door END instruction, close wave door, Yi Jigen
Determine that switching in networking sends thread or switch in data according to the flag bit of institute's transmitting data frame under networking receiving thread
Send thread；
In data transmission line journey, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is opened receipts to close；The third mode is sent to the FPGA to cut
Instruction is changed, the FPGA is made to be switched to data transmission modes；To the FPGA send wave door initial order, wave door is opened；And
Transmitted data frame is determined according to the data frame of upper thread transmission；When transmitted data frame is end frame, switch in
Networking model, according to transmitted data frame, starts the overtime timer when transmitted data frame is not end frame；If institute
It states and does not complete data frame biography in data frame institute configure in the overtime timer and currently transmitted matched waiting-timeout time
It is defeated, it determines abnormal state, switches in networking model, otherwise, switch in data receiver thread；
In data receiver thread, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is closed to receive and is opened；Fourth mode is sent to the FPGA to cut
Instruction is changed, the FPGA is made to be switched to data receiver mode；To the FPGA send wave door END instruction, close wave door；Root
Received data frame is determined according to the data frame that a upper thread transmits；According to received data frame, start the overtime timer；
If not receiving data in data frame institute configure in the overtime timer and currently received matched waiting-timeout time
Frame determines abnormal state, switches in networking model, otherwise, when the data frame received is not end frame, switches in data hair
Line sending journey.
Optionally, in the data receiver thread, the DSP, if being also used in data receiver thread reception content number
During frame, local cache has been expired, and switches in data transmission line journey,
Correspondingly, the DSP, which sends data in data transmission line journey, is not successfully received answer full frame.
Optionally, the DSP, is also used to:
If the DSP receives second group of net data frame parameter that the PPC is issued, the DSP is according to described second group
Net data frame parameter determines the second data frame type, and configures the FPGA according to second data frame type, subsequent described
DSP is used and the matched data frame of the second data frame type when controlling the FPGA transmitting data frame.
Optionally, in networking receiving thread, the DSP, the data frame for being also used to receive is uploaded to the PPC.
As can be seen from the above technical solutions, the present invention provides a kind of data transfer control method and system, data transmission
Control system includes PPC, FPGA and the digital signal processor DSP with PPC and FPGA communication connection, the data pass respectively
Transmission control method, in PPC processor, under dsp processor and FPGA processor hardware structure, firstly, by DSP according under PPC
The waiting-timeout time of the transmitting-receiving time slot and overtime timer of the control parameter configuration slot timer of hair, and according under PPC
First group of net data frame parameter of hair determines the first data frame type, and configures FPGA according to the first data frame type.Due to control
Parameter processed and first group of net data frame parameter can be according to application scenarios and mission requirements flexible configuration, therefore can satisfy communication
Multifarious requirement.Secondly, the lock-out pulse that DSP is generated according to interrupt control unit triggers slot timer, into networking model,
DSP controls FPGA transmitting data frame under networking model, and is determined according to the flag bit of institute's transmitting data frame under networking model
It switches in networking model or switches in several arq modes, if switching in several arq modes, DSP controls FPGA biography under several arq modes
Transmission of data frame is realized since institute's transmitting data frame is determined according to the data frame of upper thread transmission to DSP under several arq modes
Frame is shaken hands, therefore the reliability of TDMA data between various communication patterns transmission can be improved.Secondly, if the DSP is in number
When institute's transmitting data frame is end frame under arq mode, networking model is switched in, if institute's transmitting data frame is not end frame, according to
Data frame starts overtime timer, if the matched waiting-timeout of data frame configure in overtime timer and currently transmitted institute
Data frame transfer is not completed in time, is determined abnormal state, is switched in networking model, otherwise, switches in several arq modes.Based on this
Timeout mechanism also can be further improved the reliability purpose of the TDMA data transmission between various communication patterns.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of flow diagram of data transfer control method disclosed by the embodiments of the present invention；
Fig. 2 is the flow diagram that a kind of networking disclosed by the embodiments of the present invention sends thread；
Fig. 3 is a kind of flow diagram of networking receiving thread disclosed by the embodiments of the present invention；
Fig. 4 is a kind of structural schematic diagram of data transfer control system disclosed by the embodiments of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art's every other embodiment obtained belong to what the present invention protected
Range.
It can be seen from background technology that in the prior art, the transmission of TDMA data is realized in dedicated communications network, can be based on more
The hardware structure and implementation of kind multiplicity, but to guarantee communication reliability, it is confined to particular communications application scene, each
TDMA data transmission cannot achieve general in particular communications application scene, to be unable to satisfy the multiplicity of dedicated communications network
The application demand of property.
Therefore the invention discloses a kind of data transfer control method and systems so that while meeting communication reliability
In each particular communications application scene TDMA data transmission realize it is general, realize meet dedicated communications network diversity and can
By the purpose of the application demand of property.
As shown in Figure 1, being a kind of flow diagram of data transfer control method disclosed by the embodiments of the present invention, the data
Transfer control method is suitable for including Macintosh processor (PowerPC, PPC), field programmable gate array (Field
Programmable Gate Array, FPGA) and respectively and at the digital signal of the PPC and FPGA communication connection
Manage the data transfer control system of device (Digital Signal Processor, DSP).
It should be noted that entire communication process is divided into networking model sum number arq mode, which is responsible for safeguarding net
The connection of network and the networking of node, carry out the transmission of specific business datum under several arq modes.
The data transfer control method specifically comprises the following steps:
Step S101: the Peripheral Interface and peripheral apparatus of the DSP are initialized.
In step s101, communication interface of the Peripheral Interface between the DSP and the PPC and the FPGA.
The peripheral apparatus includes slot timer, overtime timer and interrupt control unit.
In practical applications, communication interface may include serially rapidly input output interface (Serial RapidIO,
SRIO), high speed peripheral component interconnection standard (Peripheral Component Interconnect Express, PCIE) and
Universal input/output interface (General Purpose Input Output, GPIO).
Wherein, interface of the SRIO and GPIO between DSP and FPGA.Interface of the PCIE between DSP and PPC.
GPIO quantity can be to be multiple, and the setting of specific GPIO quantity is configured according to the actual situation by technical staff.
Step S102: the DSP receives the control parameter that the PPC is issued and first group of net data frame parameter.
In step s 102, the PPC determines the control parameter and described first according to application scenarios and mission requirements
Group net data frame parameter.The control parameter is determined according to application scenarios and mission requirements by PPC in embodiments of the present invention
With first group of net data frame parameter, it is based on this, it can be according to application scenarios and mission requirements flexible configuration control parameter and the
One group of net data frame parameter, so as to meet the multifarious requirement of communication.
Step S103: the DSP configures the transmitting-receiving time slot of the slot timer and described super according to the control parameter
When timer the waiting-timeout time.
In step s 103, optionally, which includes TDMA slot parameter, and data, which are properly received, replies frame
(Acknowledgement, ACK) time-out time and data allow to send frame (Clear to send, CTS) time-out time etc..Institute
DSP is stated according to the transmitting-receiving time slot of the TDMA slot parameter configuration slot timer, according to the CTS time-out time in control parameter
With the waiting-timeout time of ACK time-out time configuration overtime timer.
It should be noted that super by configurations such as the above-mentioned CTS time-out time according in control parameter and ACK time-out times
When timer the waiting-timeout time, subsequent when transmitting a certain data frame, overtime timer can be matched according to the data frame
The waiting-timeout time judge whether there is abnormal state.Specifically, if not completing data within the corresponding waiting-timeout time
Frame transmission, then can acknowledgement state exception.For example, in transmitting data frame ACK, if not completed within the waiting-timeout time of ACK
The transmission of data frame ACK, it is determined that abnormal state.Data are judged in such a way that the waiting-timeout time is set for every kind of data frame
Whether the transmission state of frame is normal, and the reliability of the TDMA data transmission between various communication patterns can be improved.
It should be noted that slot timer is for calculating and keeping TDMA slot.
Overtime timer is used to detect the step of time-out, and is resetted.
Step S104: the DSP determines the first data frame type according to first group of net data frame parameter, and according to institute
It states the first data frame type and configures the FPGA.
In a kind of specific embodiment of step S104, DSP according to PPC send group net data frame parameter in mark
Position determines the type of group net data frame, and configures FPGA by SRIO.
It should be noted that FPGA realizes technology for realizing the Data Transmission Controlling of encoding and decoding and modulation /demodulation.
Interface of the SRIO between DSP and FPGA.
Step S105: the DSP triggers the slot timer according to the lock-out pulse that the interrupt control unit generates, into
Enter networking model.
In step s105, networking model includes that networking sends thread and networking receiving thread.
During executing step S105, the external synchronization clock of interrupt control unit is waited to trigger slot timer.Institute
Stating the timeslot number determination that DSP is presently according to the slot timer is to enter networking to send thread or enter networking reception
Thread.It in practical application, can be communicated to connect by GPIO interface between DSP and interrupt control unit, for example, GPIO1 reality can be passed through
Communication connection between existing DSP and interrupt control unit.
Optionally, the DSP enters when slot timer is triggered according to the timeslot number in the TDMA slot parameter
Corresponding networking model.Wherein, if the timeslot number indicates sending time slots, the DSP enters networking and sends thread, if when described
Gap number instruction receives time slot, and the DSP enters networking receiving thread.
It should be noted that external synchronization clock may have several pulses, DSP only needs to respond first pulse,
Subsequent pulse is without response.
External synchronization clock is to start the slot timer, and close after external pulse for the first time triggering slot timer
Close the external interrupt of response interrupt control unit.
It should be noted that in embodiments of the present invention, it is generally the case that, can be with by being initialized to DSP
The DSP is set to enter networking model.
It should be noted that being currently sending time slots according to current time slots number judgement when DSP first enters networking model
Or receive time slot.
If first time slot is sending time slots, DSP sends the group net data frame being locally stored, and can be after being sent completely
First reception time slot data frame content is updated from PPC.
In sending time slots, DSP switches radio frequency by GPIO and opens transmission interface, closes receiving interface (networking frequency point).DSP
By SRIO to FPGA sending mode switching command, and by GPIO to the FPGA send wave door initial order, so that the FPGA
It is sent out data.
Herein, different GPIO can be configured according to reference demand.For example, DSP can be cut by GPIO2 and GPIO3
It changes radio frequency and opens transmission interface, close receiving interface (networking frequency point).Pass through SRIO to FPGA sending mode switching command in DSP
During, it can be by GPIO4 to the FPGA send wave door initial order, so that the FPGA is sent out data.It needs
Bright, the label of GPIO1, GPIO2, GPIO3 and GPIO4 herein represent different communication interfaces, to lead to different
Letter interface is distinguish, but does not cause to limit to the title of each communication interface.
If first time slot is to receive time slot, DSP enters networking receiving thread, and waits hair as defined in oneself timeslot number
Send time slot to execute again when arriving and send the group net data frame that is locally stored, and first reception time slot after being sent completely from
Data frame content this operation is updated at PPC.
Step S106: the DSP controls the FPGA transmitting data frame under networking model.
In step s 106, networking model includes that networking sends thread and networking receiving thread.Specifically, as shown in Fig. 2,
Networking sends thread
The hair that the radio frequency of the FPGA is switched to networking frequency point is opened receipts by step S201: the DSP to close.
In S201, hair opens receipts pass and specifically refers to open transmission interface, closes receiving interface.
Step S202: the DSP sends first mode switching command to the FPGA, and the FPGA is made to be switched to networking hair
Send mode.
Step S203: the DSP, to the FPGA send wave door initial order, opens wave door, and the FPGA is made to send number
According to frame.
In step S203, when the DSP, which is in the networking, sends thread, the DSP is to the FPGA send wave
Door initial order makes the FPGA send the data frame that is locally stored to other equipment, and the after data frame is sent
One reception time slot obtains current newest data frame from PPC, and is updated by SRIO to FPGA.Wherein, other herein
Equipment is system peripherals.
Step S204: the DSP according in the case where networking sends thread the flag bit determination of institute's transmitting data frame be to switch in
Networking receiving thread still switches in data receiver thread.
In step S204, the DSP judges transmission according to the flag bit of institute's transmitting data frame in the case where networking sends thread
The type of data frame, the data frame type that subsequent basis is judged, which determines, enters networking receiving thread or data receiver thread.
For example, determining that institute's transmitting data frame is networking broadcast frame when the flag bit of institute's transmitting data frame is 0, determining in this transmission
First reception time slot after gap switches in networking receiving thread.When the flag bit of the transmitting data frame is 1, determine
Institute's transmitting data frame is that number passes claim frame (Request To Send, abbreviation RTS), and determination switches after this sending time slots
Enter data receiver thread.What needs to be explained here is that transmission is networking if first time slot after initializing is sending time slots
Broadcast frame, the data frame that subsequent sending time slots are sent can pass claim frame for networking broadcast frame or number, be with specific reference to node
It is no to there are data transfer demands to determine.
When time slot Timer Controlling DSP is switched to reception time slot, the DSP switches in networking receiving thread, such as Fig. 3 institute
Show, networking receiving thread includes:
The hair that the radio frequency of FPGA is switched to networking frequency point is closed to receive by step S301:DSP to be opened.
In step S301, hair, which closes to receive, opens finger closing transmission interface, opens receiving interface.Corresponding in previous embodiment
DSP can switch radio frequency by GPIO2 and GPIO3 and open transmission interface, close receiving interface, DSP can lead in this step
It crosses GPIO2 and GPIO3 switching radio frequency and closes transmission interface, open receiving interface.
Step S302:DSP sends second mode switching command to FPGA, and FPGA is made to be switched to networking reception pattern.
In step s 302, DSP switches FPGA mode by SRIO.
Step S303:DSP closes wave door to FPGA send wave door END instruction.
It can be by GPIO4 to FPGA send wave door initial order, in this step corresponding to the DSP in previous embodiment
DSP can be by GPIO4 to FPGA send wave door END instruction.
Step S304:DSP according under networking receiving thread the flag bit determination of institute's transmitting data frame be to switch in networking
It sends thread and still switches in data transmission line journey.
Optionally, when the DSP is in networking receiving thread, the data frame that the FPGA received is sent is parsed,
Data frame after parsing is uploaded to the PPC.Specifically, when the radio frequency of FPGA receives the data frame of other equipment transmission
Afterwards, baseband signal is converted to by FPGA decoding, parses the data frame that the FPGA received is sent, the data frame after parsing is led to
It crosses SRIO and is sent to DSP, which judges institute's operation to be performed according to the flag bit of the data frame received, and by the data
Frame is uploaded to PPC.In this way, the recording and displaying of data frame can be realized on PPC.
It should be noted that if the DSP receives second group of net data frame parameter that the PPC is issued, the DSP root
The second data frame type is determined according to second group of net data frame parameter, and according to second data frame type configuration
When FPGA, the subsequent DSP control the FPGA transmitting data frame using with the matched data frame of the second data frame type,
To realize the flexible switching of data frame type.In addition, second group of net data frame parameter list here shows data frame type and first
The different group net data frame parameter of the corresponding data frame type of group net data frame parameter.And second group of net data frame ginseng is not being received
When number, continue to execute networking model or number arq mode using the corresponding data frame type of the first data networking data frame parameter.
Step S107: the DSP according under networking model the flag bit determination of institute's transmitting data frame be to switch in networking
Mode still switches in several arq modes, if switching in several arq modes, executes step S108.
Step S108: the DSP controls the FPGA transmitting data frame under several arq modes.
In step S108, number arq mode includes data transmission line journey and data receiving thread.
It should be noted that the control for no longer following slot timer under number arq mode carries out data transmission line journey and data
The switching of receiving thread.
Various transmitting data frames are sent in data transmission line journey, different transmitting data frames corresponds to different shapes
State.
Institute's transmitting data frame includes that CTS, content-data frame, ACK, data are not successfully received answer in data transmission line journey
Full frame ACK BUFF and the data transfer ends frame END.
Wherein, content-data frame can be understood as transmitted valid data, or the target data transmitted, such as in
Holding data frame can be control information, data information etc..
Specifically, data transmission line journey includes:
The hair that the radio frequency of FPGA is switched to data transmission frequency point is opened receipts and closed by A1, DSP.
A2, DSP send the third mode switching command to FPGA, and FPGA is made to be switched to data transmission modes.
A3, DSP open wave door to FPGA send wave door initial order.
A4, DSP determine transmitted data frame according to the data frame that a upper thread transmits.
When data frame transmitted by A5, DSP is end frame, networking model is switched in.
When transmitted data frame is not end frame, DSP starts overtime timer according to transmitted data frame by A6, DSP.
A7, if configured in overtime timer, with it is not complete in the currently transmitted data frame institute matched waiting-timeout time
At data frame transfer, abnormal state is determined, switch in networking model, otherwise, switch in data receiver thread.
Data receiver thread includes:
The hair that the radio frequency of FPGA is switched to data transmission frequency point is closed to receive by B1, DSP to be opened.
B2, DSP send fourth mode switching command to FPGA, and FPGA is made to be switched to data receiver mode.
B3, DSP close wave door to FPGA send wave door END instruction.
B4, DSP determine received data frame according to the data frame that a upper thread transmits.
B5, DSP start overtime timer according to received data frame.
B6, if configured in overtime timer, with do not connect in the currently received data frame institute matched waiting-timeout time
Receive data frame, determine abnormal state, switch in networking model, otherwise, DSP when the data frame received is not end frame,
Switch in data transmission line journey.
Optionally, in data receiver thread, if local cache has been expired, data transmission line journey is switched in, correspondingly, described
DSP sends data in data transmission line journey and is not successfully received answer full frame.
Step S109: judging whether DSP institute's transmitting data frame under several arq modes is end frame, if so, switching
Enter networking model, if it is not, thening follow the steps S110.
In step S109, the DSP data that institute's transmitting data frame is transmitted according to a upper thread under several arq modes
Frame determines.
In the concrete realization, in data transmission line journey the type of institute's transmitting data frame include CTS, content-data frame,
ACK, ACKBUFF and END.Wherein, when DSP is when the data frame that networking receiving thread receives is RTS, in data transmission line journey
Send CTS；When DSP is when the data frame that data receiver thread receives is CTS, in data transmission line journey transmission content-data
Frame；When DSP is when the data frame that networking receiving thread receives is content-data frame, in data transmission line journey transmission ACK；DSP
During data receiver thread reception content data frame, if being locally stored after data buffer expired, ACK BUFF is sent；
When DSP has sent content-data frame, and after data receiver thread receives ACK, END is sent.
The data frame used in received data frame and data transmission line journey in data receiver thread is identical.
Step S110 starts the overtime timer according to data frame.
Step S111, if the matched waiting-timeout of data frame configured in the overtime timer and currently transmitted institute
Data frame transfer is not completed in time, is determined abnormal state, is switched in networking model, otherwise, switches in several arq modes.
In step S111, it should be noted that can be different when the control parameter that aforementioned PPC is issued is arranged
Different time-out times is arranged in data frame.Such as the time-out time of the correspondence CTS in control parameter, the time-out time, interior of corresponding A CK
Hold the time-out time etc. of data frame, and then is that the corresponding waiting-timeout time is arranged in different data frames in overtime timer.
By whether completing data frame transfer in the determining and currently transmitted data frame institute matched waiting-timeout time, if
It does not complete, it is determined that abnormal state promotes the reliability purpose of data transmission using this timeout mechanism.
It should be noted that the DSP enters the triggering slot timer when several arq modes switch in networking model
When the networking model that is entered, under other situations, receiving thread is switched to from sending thread when switching every time, alternatively, from reception
Thread is switched to transmission thread.In addition, the type of each transmitting data frame and the data frame class determined according to group net data frame parameter
Type is identical.
During implementing step S107 to step S111, after switching in several arq modes, for different transmission
Data frame enables the corresponding waiting-timeout time in overtime timer.It is exemplified below:
If the DSP is RTS in the data frame that networking receiving thread receives, DSP is switched in after receiving time slot
When data transmission line journey, DSP will send CTS, and for DSP according to the waiting-timeout time of CTS, whether detection sends CTS overtime, if surpassing
When, DSP switches in networking model by data transmission line journey；If having not timed out, DSP is after CTS is sent by data transmission line journey
Data receiver thread, reception content data frame are switched in, subsequent starting enables matched with content-data frame in overtime timer
The waiting-timeout time carries out overtime judgement.
DSP is during reception content data frame, if after local datastore is full, sending in data transmission line journey DSP
According to the waiting-timeout time of ACK BUFF, whether detection transmission ACKBUFF is overtime by ACK BUFF to FPGA, DSP, if overtime,
DSP switches in networking model by data transmission line journey；If having not timed out, DSP is after ACKBUFF is sent by data transmission line journey
Switch in data receiver thread.
DSP after data transmission line journey has sent content-data frame, will data receiver thread receive ACK, DSP according to
The waiting-timeout time of ACK, detect whether time-out, if overtime, DSP switches in networking model by data receiver thread；If not surpassing
When, DSP switches in data transmission line journey by data receiver thread after data frame is sent.
A kind of data transfer control method disclosed by the embodiments of the present invention, in PPC processor, at dsp processor and FPGA
It manages under device hardware structure, is shaken hands by DSP using thread frame and realize the data transmission control of TDMA link layer with overtime control mechanism
The switching between TDMA data transmission stream journey between system, and the various communication patterns of control, it is ensured that between each communication pattern
Workflow it is stably and controllable, so that it is guaranteed that data transmission reliability and communication diversity, realize at the same meet it is various lead to
The reliability and communication diversity of TDMA data transmission between letter mode.
A kind of data transfer control method disclosed by the embodiments of the present invention, it is first under DSP and FPGA hardware framework in PPC
First, the waiting-timeout of the transmitting-receiving time slot and overtime timer of slot timer is configured according to the control parameter that PPC is issued by DSP
Time, and the first data frame type is determined according to first group of net data frame parameter that PPC is issued, and according to the first data frame class
Type configures FPGA.Since control parameter and first group of net data frame parameter can flexibly match according to application scenarios and mission requirements
It sets, therefore can satisfy the multifarious requirement of communication.Secondly, DSP triggers time slot according to the lock-out pulse that interrupt control unit generates
Timer, into networking model, DSP controls FPGA transmitting data frame under networking model, and is passed according under networking model
The flag bit determination of transmission of data frame switches in networking model or switches in several arq modes, if switching in several arq modes, DSP exists
FPGA transmitting data frame is controlled under number arq mode, since institute's transmitting data frame is passed according to a upper thread to DSP under several arq modes
What defeated data frame determined, be equivalent to frame and shake hands, therefore can be improved the transmission of the TDMA data between various communication patterns can
By property.Secondly, if the DSP under several arq modes institute's transmitting data frame be end frame when, networking model is switched in, if transmitted number
When not being end frame according to frame, overtime timer is started according to data frame, if configure in overtime timer and currently transmitted number
According to data frame transfer is not completed in the frame institute matched waiting-timeout time, determines abnormal state, switch in networking model, otherwise,
Switch in several arq modes.Based on the timeout mechanism, it also may be implemented to improve the TDMA data transmission between various communication patterns
Reliability purpose.
Based on a kind of data transfer control method disclosed in the embodiments of the present invention, the embodiment of the present invention is also corresponding open
A kind of data transfer control system, such as Fig. 4, show the structural schematic diagram of data transfer control system, data transmission control
System 400 processed specifically includes that
PPC401, DSP402 and FPGA403.
Communication of the Peripheral Interface of the DSP402 between the DSP402 and the PPC401 and the FPGA403 connects
Mouthful.
It should be noted that the peripheral apparatus and Peripheral Interface of the DSP402 are initialized.Peripheral Interface is
Communication interface between the DSP and the PPC and the FPGA.The peripheral apparatus includes slot timer, time-out timing
Device and interrupt control unit.
It should be noted that communication interface includes SRIO, PCIE and GPIO.
Wherein, interface of the SRIO and GPIO between DSP and FPGA.
Interface of the PCIE between DSP and PPC.
GPIO quantity can be to be multiple, and the setting of specific GPIO quantity is configured according to the actual situation by technical staff.
The PPC401, for determining control parameter and first group of net data frame ginseng according to application scenarios and mission requirements
Number, and issue.
The DSP402 after initialization, for receiving the control parameter and first group of net data frame that the PPC401 is issued
Parameter；When configuring the waiting-timeout for receiving and dispatching time slot and the overtime timer of the slot timer according to the control parameter
Between；The DSP402 determines the first data frame type according to first group of net data frame parameter, and according to first data
FPGA403 described in frame type configuration；The DSP402 triggers the time slot according to the lock-out pulse that the interrupt control unit generates
Timer, into networking model；Networking model includes that networking sends thread and networking receiving thread, and the DSP402 is according to
The timeslot number determination that slot timer is presently in is to enter networking to send thread or enter networking receiving thread；It is described
DSP402 controls the FPGA403 transmitting data frame under networking model；The DSP402 is transmitted according under networking model
The flag bit determination of data frame switches in networking model or switches in several arq modes, and number arq mode includes data transmission line journey
With data receiving thread；If switching in several arq modes, the DSP402 controls the FPGA403 transmission data under several arq modes
Frame；The DSP402 under several arq modes institute's transmitting data frame be end frame when, switch in networking model；The DSP is passed in number
When institute's transmitting data frame is not end frame under mode, the overtime timer is started according to data frame；The DSP402 is passed in number
Institute's transmitting data frame is determined according to the data frame that a upper thread transmits under mode；If it is being configured in the overtime timer, with
Data frame transfer is not completed in the currently transmitted data frame institute matched waiting-timeout time, abnormal state is determined, switches in group
Otherwise net mode switches in several arq modes.
Wherein, when several arq modes switch in networking model, the DSP402 enters triggering slot timer when institute
The networking model of entrance under other situations, is switched to receiving thread from sending thread when switching every time, alternatively, from receiving thread
It is switched to transmission thread.
Optionally, the DSP402, if being also used to the DSP receives second group of net data frame ginseng that the PPC is issued
Number, the DSP determine the second data frame type according to second group of net data frame parameter, and according to the second data frame class
Type configures the FPGA, and the subsequent DSP is used and second data frame type when controlling the FPGA transmitting data frame
The data frame matched.
The FPGA403, for transmitting various data frames under the control of the DSP402.
It is sent in thread in networking, the DSP402, the hair for the radio frequency of the FPGA403 to be switched to networking frequency point is opened
It receives and closes；First mode switching command is sent to the FPGA403, the FPGA403 is made to be switched to networking sending mode；To described
FPGA403 send wave door initial order opens wave door, and the FPGA403 is made to send data frame；It is sent under thread according in networking
The flag bit determination of institute's transmitting data frame switches in networking receiving thread or switches in data receiver thread.
In networking receiving thread, the DSP402, the hair for the radio frequency of the FPGA to be switched to networking frequency point is closed
Receipts are opened；Second mode switching command is sent to the FPGA, the FPGA is made to be switched to networking reception pattern；It is sent out to the FPGA
Send wave door END instruction, make wave door close, and according under networking receiving thread the flag bit determination of institute's transmitting data frame be
It switches in networking transmission thread and still switches in data transmission line journey.
Optionally, in networking receiving thread, the DSP, the data frame for being also used to receive is uploaded to the PPC.
In data transmission line journey, the DSP402, for the radio frequency of the FPGA to be switched to data transmission frequency point
Hair is opened receipts and is closed；The third mode switching command is sent to the FPGA, the FPGA is made to be switched to data transmission modes；To described
FPGA send wave door initial order opens wave door；And transmitted data frame is determined according to the data frame of upper thread transmission；
When transmitted data frame is end frame, networking model is switched in, when transmitted data frame is not end frame, according to being sent out
Data frame is sent, the overtime timer is started；If being configured in the overtime timer, matched with currently transmitted data frame
The waiting-timeout time in do not complete data frame transfer, determine abnormal state, switch in networking model, otherwise, switch in data
Receiving thread.
In data receiver thread, the DSP402, for the radio frequency of the FPGA403 to be switched to data transmission frequency point
Hair close receive open；Fourth mode switching command is sent to the FPGA403, the FPGA403 is made to be switched to data receiver mode；
To the FPGA403 send wave door END instruction, close wave door；The reception is determined according to the data frame that a upper thread transmits
Data frame；According to received data, start the overtime timer；If it is being configured in the overtime timer, with currently connect
It receives in the data frame institute matched waiting-timeout time and does not receive data frame, determine abnormal state, switch in networking model, it is no
Then, when the data frame received is not end frame, data transmission line journey is switched in.
Optionally, in the data receiver thread, the DSP402, if being also used in data receiver thread reception content
During data frame, local cache has been expired, and switches in data transmission line journey.
Correspondingly, the DSP, which sends data in data transmission line journey, is not successfully received answer full frame.
The embodiment of the invention discloses a kind of data transfer control systems, in PPC processor, at dsp processor and FPGA
It manages under device hardware structure, firstly, configuring the transmitting-receiving time slot of slot timer according to the control parameter that PPC is issued by DSP and surpassing
When timer the waiting-timeout time, and the first data frame type is determined according to first group of net data frame parameter that PPC is issued,
And FPGA is configured according to the first data frame type.Since control parameter and first group of net data frame parameter can be according to application scenarios
With mission requirements flexible configuration, therefore the multifarious requirement of communication can satisfy.Secondly, what DSP was generated according to interrupt control unit
Lock-out pulse triggers slot timer, and into networking model, DSP controls FPGA transmitting data frame under networking model, and according to
The flag bit determination of institute's transmitting data frame switches in networking model or switches in several arq modes under networking model, if switching
Enter several arq modes, DSP controls FPGA transmitting data frame under several arq modes, by DSP under several arq modes institute's transmitting data frame
It is to be determined according to the data frame of upper thread transmission, realizes frame and shake hands, therefore can be improved between various communication patterns
The reliability of TDMA data transmission.Secondly, if the DSP under several arq modes institute's transmitting data frame be end frame when, switch in group
Net mode starts overtime timer according to data frame, if configuring in overtime timer if institute's transmitting data frame is not end frame
, with do not complete data frame transfer in the currently transmitted data frame institute matched waiting-timeout time, determine abnormal state, switch
Enter networking model, otherwise, switches in several arq modes.Based on the timeout mechanism, also can be further improved various communication patterns it
Between TDMA data transmission reliability purpose.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including element
There is also other identical elements in process, method, commodity or equipment.
It will be understood by those skilled in the art that the embodiment of the present invention can provide as method, apparatus or computer program product.
Therefore, complete hardware embodiment, complete software embodiment or embodiment combining software and hardware aspects can be used in the present invention
Form.It is deposited moreover, the present invention can be used to can be used in the computer that one or more wherein includes computer usable program code
The shape for the computer program product implemented on storage media (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.)
Formula.
The above is only the embodiment of the present invention, are not intended to restrict the invention.To those skilled in the art,
The invention may be variously modified and varied.It is all within the spirit and principles of the present invention made by any modification, equivalent replacement,
Improve etc., it should be included within scope of the presently claimed invention.
Claims (10)
1. a kind of data transfer control method, which is characterized in that be suitable for including Macintosh processor PPC, field programmable gate
Array FPGA and the respectively Data Transmission Controlling with the PPC and FPGA digital signal processor DSP communicated to connect
System, which comprises
Initialize the Peripheral Interface and peripheral apparatus of the DSP, the Peripheral Interface is the DSP and PPC and described
Communication interface between FPGA, the peripheral apparatus include slot timer, overtime timer and interrupt control unit；
The DSP receives the control parameter that the PPC is issued and first group of net data frame parameter；The PPC is according to application scenarios
The control parameter and first group of net data frame parameter are determined with mission requirements；
The DSP configures the time-out of the transmitting-receiving time slot and the overtime timer of the slot timer according to the control parameter
Waiting time；
The DSP determines the first data frame type according to first group of net data frame parameter, and according to first data frame
FPGA described in type configuration；
The DSP triggers the slot timer according to the lock-out pulse that the interrupt control unit generates, into networking model；Group
Net mode includes that networking sends thread and networking receiving thread, the time slot that the DSP is presently according to the slot timer
Number determination is to enter networking to send thread or enter networking receiving thread；
The DSP controls the FPGA transmitting data frame under networking model；
The DSP is determined according to the flag bit of institute's transmitting data frame under networking model to be switched in networking model or switches in
Number arq mode, number arq mode includes data transmission line journey and data receiving thread；
If switching in several arq modes, the DSP controls the FPGA transmitting data frame under several arq modes；
The DSP under several arq modes institute's transmitting data frame be end frame when, switch in networking model；
The DSP starts the overtime timer when institute's transmitting data frame is not end frame under several arq modes, according to data frame；
DSP institute's transmitting data frame under several arq modes is determined according to the data frame that a upper thread transmits；
If not completing number in data frame institute configure in the overtime timer and currently transmitted matched waiting-timeout time
It is transmitted according to frame, determines abnormal state, switch in networking model, otherwise, switch in several arq modes；
Wherein, when several arq modes switch in networking model, the DSP enters the group entered when triggering the slot timer
Net mode under other situations, is switched to receiving thread from sending thread when switching every time, alternatively, being switched to hair from receiving thread
Line sending journey.
2. the method according to claim 1, wherein
Networking sends thread
The hair that the radio frequency of the FPGA is switched to networking frequency point is opened receipts and closed by the DSP；
The DSP sends first mode switching command to the FPGA, and the FPGA is made to be switched to networking sending mode；
The DSP opens wave door to the FPGA send wave door initial order, and the FPGA is made to send data frame；
The DSP is to switch in networking receiving thread also according to the flag bit determination of institute's transmitting data frame in the case where networking sends thread
It is to switch in data receiver thread；
Networking receiving thread includes:
The hair that the radio frequency of the FPGA is switched to networking frequency point is closed to receive by the DSP to be opened；
The DSP sends second mode switching command to the FPGA, and the FPGA is made to be switched to networking reception pattern；
The DSP closes wave door to the FPGA send wave door END instruction；
The DSP according under networking receiving thread the flag bit determination of institute's transmitting data frame be switch in networking send thread also
It is to switch in data transmission line journey；
Data transmission line journey includes:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is opened receipts and closed by the DSP；
The DSP sends the third mode switching command to the FPGA, and the FPGA is made to be switched to data transmission modes；
The DSP opens wave door to the FPGA send wave door initial order；
The DSP determines transmitted data frame according to the data frame that a upper thread transmits；
When data frame transmitted by the DSP is end frame, networking model is switched in；
For the DSP when transmitted data frame is not end frame, it is fixed to start the time-out according to transmitted data frame by the DSP
When device；
If not completing number in data frame institute configure in the overtime timer and currently transmitted matched waiting-timeout time
It is transmitted according to frame, determines abnormal state, switch in networking model, otherwise, switch in data receiver thread；
Data receiver thread includes:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is closed to receive by the DSP to be opened；
The DSP sends fourth mode switching command to the FPGA, and the FPGA is made to be switched to data receiver mode；
The DSP closes wave door to the FPGA send wave door END instruction；
The DSP determines received data frame according to the data frame that a upper thread transmits；
The DSP starts the overtime timer according to received data frame；
If it is being configured in the overtime timer, with do not received in the currently received data frame institute matched waiting-timeout time
Data frame determines abnormal state, switches in networking model, otherwise, the DSP when the data frame received is not end frame,
Switch in data transmission line journey.
3. according to the method described in claim 2, it is characterized in that,
Data receiver thread further include:
If local cache has been expired, and data transmission line journey is switched in during data receiver thread reception content data frame；
Correspondingly, sending data in data transmission line journey is not successfully received answer full frame.
4. the method according to claim 1, wherein further include:
If the DSP receives second group of net data frame parameter that the PPC is issued, the DSP is according to second group of netting index
The second data frame type is determined according to frame parameter, and the FPGA, the subsequent DSP control are configured according to second data frame type
It is used and the matched data frame of the second data frame type when making the FPGA transmitting data frame.
5. method according to any one of claims 1 to 4, which is characterized in that further include:
The DSP is uploaded to the PPC in networking receiving thread, by the data frame received.
6. a kind of data transfer control system, which is characterized in that the data transfer control system includes: Macintosh processor
PPC, on-site programmable gate array FPGA and the digital signal processor communicated to connect respectively with the PPC and FPGA
DSP；
The PPC, for determining control parameter and first group of net data frame parameter according to application scenarios and mission requirements, and under
Hair；
Communication interface of the Peripheral Interface of the DSP between the DSP and the PPC and the FPGA, the peripheral hardware of the DSP
Equipment includes slot timer, overtime timer and interrupt control unit；
The DSP after initialization, for receiving the control parameter and first group of net data frame parameter that the PPC is issued；According to
The control parameter configures the waiting-timeout time of the transmitting-receiving time slot and the overtime timer of the slot timer；It is described
DSP determines the first data frame type according to first group of net data frame parameter, and is configured according to first data frame type
The FPGA；The DSP triggers the slot timer according to the lock-out pulse that the interrupt control unit generates, into networking mould
Formula；Networking model includes that networking transmission thread and networking receiving thread, the DSP are presently according to the slot timer
Timeslot number determination is to enter networking to send thread or enter networking receiving thread；Described in the DSP is controlled under networking model
FPGA transmitting data frame；The DSP according under networking model the flag bit determination of institute's transmitting data frame be to switch in networking mould
Formula still switches in several arq modes, and number arq mode includes data transmission line journey and data receiving thread；If switching in several arq modes,
The DSP controls the FPGA transmitting data frame under several arq modes；DSP institute's transmitting data frame under several arq modes is knot
When beam frame, networking model is switched in；The DSP is when institute's transmitting data frame is not end frame under several arq modes, according to data frame
Start the overtime timer；The DSP data frame that institute's transmitting data frame is transmitted according to a upper thread under several arq modes
It determines；If not completed in data frame institute configured in the overtime timer and currently transmitted matched waiting-timeout time
Data frame transfer determines abnormal state, switches in networking model, otherwise, switches in several arq modes；
Wherein, when several arq modes switch in networking model, the DSP enters the group entered when triggering the slot timer
Net mode under other situations, is switched to receiving thread from sending thread when switching every time, alternatively, being switched to hair from receiving thread
Line sending journey；
The FPGA, for transmitting various data frames under the control of the DSP.
7. system according to claim 6, which is characterized in that sent in thread in networking, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to networking frequency point is opened receipts to close；First mode switching command is sent to the FPGA,
The FPGA is set to be switched to networking sending mode；To the FPGA send wave door initial order, wave door is opened, sends out the FPGA
Send data frame；According to networking send thread under institute's transmitting data frame flag bit determine switch in networking receiving thread or
Switch in data receiver thread；
In networking receiving thread, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to networking frequency point is closed to receive and is opened；Second mode switching command is sent to the FPGA,
The FPGA is set to be switched to networking reception pattern；To the FPGA send wave door END instruction, close wave door, and according to
The flag bit of institute's transmitting data frame determines that switching in networking sends thread or switch in data transmission under networking receiving thread
Thread；
In data transmission line journey, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is opened receipts to close；The third mode switching is sent to the FPGA to refer to
It enables, the FPGA is made to be switched to data transmission modes；To the FPGA send wave door initial order, wave door is opened；And according to
The data frame of upper thread transmission determines transmitted data frame；When transmitted data frame is end frame, networking is switched in
Mode, according to transmitted data frame, starts the overtime timer when transmitted data frame is not end frame；If described super
When timer in configure, with do not complete data frame transfer in the currently transmitted data frame institute matched waiting-timeout time, really
Determine abnormal state, switch in networking model, otherwise, switches in data receiver thread；
In data receiver thread, the DSP is used for:
The hair that the radio frequency of the FPGA is switched to data transmission frequency point is closed to receive and is opened；Fourth mode switching is sent to the FPGA to refer to
It enables, the FPGA is made to be switched to data receiver mode；To the FPGA send wave door END instruction, close wave door；According to upper
The data frame of one thread transmission determines received data frame；According to received data frame, start the overtime timer；If institute
It states in data frame institute configured in the overtime timer and currently received matched waiting-timeout time and does not receive data frame,
It determines abnormal state, switches in networking model, otherwise, when the data frame received is not end frame, switch in data transmission
Thread.
8. system according to claim 7, which is characterized in that in the data receiver thread, the DSP is also used to
If local cache has been expired during data receiver thread reception content data frame, data transmission line journey is switched in,
Correspondingly, the DSP, which sends data in data transmission line journey, is not successfully received answer full frame.
9. system according to claim 6, which is characterized in that the DSP is also used to:
If the DSP receives second group of net data frame parameter that the PPC is issued, the DSP is according to second group of netting index
The second data frame type is determined according to frame parameter, and the FPGA, the subsequent DSP control are configured according to second data frame type
It is used and the matched data frame of the second data frame type when making the FPGA transmitting data frame.
10. according to the described in any item systems of claim 6 to 8, which is characterized in that in networking receiving thread, the DSP,
The data frame for being also used to receive is uploaded to the PPC.
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| CN111031196A (en) * | 2019-12-25 | 2020-04-17 | 普世(南京)智能科技有限公司 | Low-power-consumption one-way feedback-free image transmission method and system based on mark frame |
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| CN111031196B (en) * | 2019-12-25 | 2024-04-26 | 普世(南京)智能科技有限公司 | Low-power-consumption unidirectional feedback-free image transmission method and system based on mark frame |
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| CN110391863B (en) | 2020-12-01 |
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