CN110391797B - D trigger circuit based on IGZO TFT - Google Patents
D trigger circuit based on IGZO TFT Download PDFInfo
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- CN110391797B CN110391797B CN201910546215.6A CN201910546215A CN110391797B CN 110391797 B CN110391797 B CN 110391797B CN 201910546215 A CN201910546215 A CN 201910546215A CN 110391797 B CN110391797 B CN 110391797B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
In order to solve the problems of large quantity, large area and high power consumption of D flip-flop transistors in the prior art, the invention provides a D flip-flop circuit based on an IGZO TFT, which comprises two pure N-type D latches with the same structure, and the technical scheme is as follows: the two pure N-type D latches are connected through a proportional structure. The invention is formed by connecting two D latches by a ratio circuit, wherein the ratio circuit determines the output voltage by the difference of the resistances presented by the difference of the width-length ratios of the pull-up and pull-down network transistors, the output of the circuit is the result of voltage division of the pull-up and pull-down tubes and is related to the ratio of the width-length ratios, so as long as the ratio is proper, the transistors with smaller width-length ratios can be used for reducing the whole area. The invention has the advantages of simple structure, small number of transistors, small area and low power consumption.
Description
Technical Field
The invention relates to the field of triggers, in particular to a D trigger circuit of an all-N-type IGZO TFT.
Background
A TFT (Thin-film transistor), which is a Thin film transistor, is an insulated gate field effect transistor. Compared with the traditional transistor, the transistor has the greatest characteristic that the transistor can be manufactured and integrated on a substrate such as glass, plastic and the like, and is not limited by a traditional silicon plate. Compared with the conventional CMOS, the TFT has higher integration level, more flexible shape and lower manufacturing cost because the substrate is glass or plastic.
In recent years, with the development of flexible electronic technology and the demand for bendable, high integration of electronic devices, the application of TFTs is no longer limited to display screens, but it is expected that each module in a circuit system can be reconfigured. However, the relatively low electron mobility of TFTs relative to CMOS makes their constituent circuits less than ideal.
Compared with the traditional a-Si (amorphous silicon) TFT, the IGZO (indium gallium zinc oxide) TFT has the advantages of greatly improved electron mobility, good mobility and reliability, uniform device in large-area manufacturing and low cost of large-scale production. Therefore, IGZO TFTs are the most promising new devices for building circuitry.
Because the TFT circuit only has N type pipes, the D trigger built by the IGZO TFT is mainly based on a pseudo cmos structure, and has the defects of large quantity of transistors, large area, high power consumption and the like.
Disclosure of Invention
In order to solve the problems of large quantity, large area and high power consumption of D flip-flop transistors in the prior art, the invention provides a D flip-flop circuit based on IGZO TFTs.
The technical scheme adopted by the invention to solve the technical problems is as follows: a D flip-flop circuit based on IGZO TFT includes two pure N-type D latches with the same structure, and the technical scheme is as follows: the two pure N-type D latches are connected through a proportional structure.
The invention has the beneficial effects that: the invention is formed by connecting two D latches by a ratio circuit, wherein the ratio circuit determines the output voltage by the difference of the resistances presented by the difference of the width-length ratios of the pull-up and pull-down network transistors, the output of the circuit is the result of voltage division of the pull-up and pull-down tubes and is related to the ratio of the width-length ratios, so as long as the ratio is proper, the transistors with smaller width-length ratios can be used for reducing the whole area. The invention has the advantages of simple structure, small number of transistors, small area and low power consumption.
Drawings
FIG. 1 is a schematic view of the structure of the present invention.
Fig. 1 (a) is a part of the circuit of the present invention.
FIG. 1 (b) shows another part of the circuit of the present invention.
Fig. 2 is a timing diagram of fig. 1.
It is to be understood that: fig. 1a and 1b are combined to form fig. 1.
Detailed Description
The present application is further described below with reference to the accompanying drawings.
As shown in fig. 1, a D flip-flop circuit based on IGZO TFT includes two pure N-type D latches with the same structure, and its technical solution is: the two pure N-type D latches are connected through a proportional structure.
Specific example 1: the invention comprises a first field effect tube M1, a second field effect tube M2, a third field effect tube M3, a fourth field effect tube M4, a fifth field effect tube M5, a sixth field effect tube M6, a seventh field effect tube M7, an eighth field effect tube M8, a ninth field effect tube M9, a tenth field effect tube M10, an eleventh field effect tube M11, a twelfth field effect tube M12, a thirteenth field effect tube M13, a fourteenth field effect tube M14, a fifteenth field effect tube M15, a sixteenth field effect tube M16, a seventeenth field effect tube M17, an eighteenth field effect tube M18, a nineteenth field effect tube M19, a twentieth field effect tube M20, a first phase inverter Inv1 and a second phase inverter Inv2;
wherein, the grid of the first field effect transistor M1 is connected with a Ctrl terminal; the source electrode of the first field effect tube M1 is connected with the drain electrodes of the second field effect tube M2 and the fourth field effect tube M4 at the same time; the source electrode of the second field effect tube M2 is connected with the drain electrode of the third field effect tube M3; the source electrode of the fourth field effect transistor M4 is connected with the drain electrode of the fifth field effect transistor M5; the source electrode of the third field effect transistor M3 is connected with the source electrode of the fifth field effect transistor M5 and then grounded; the grid electrode of the sixth field effect transistor M6 is connected with the source electrode of the first field effect transistor M1; the drain electrode of the sixth field effect tube M6 is connected with the drain electrode of the first field effect tube M1 and then is connected with the power supply; the drain electrode of the seventh field-effect tube M7 is connected with the drain electrode of the ninth field-effect tube M9 and then connected with the source electrode of the sixth field-effect tube M6; the source electrode of the seventh field effect transistor M7 is connected with the drain electrode of the eighth field effect transistor M8; the source electrode of the ninth field effect transistor M9 is connected with the drain electrode of the tenth field effect transistor M10; the source electrode of the eighth field-effect tube M8 is connected with the source electrode of the tenth field-effect tube M10 and then grounded; a first inverter Inv1 is connected between the drain of the seventh field-effect tube M7 and the drain of the ninth field-effect tube M9;
wherein, the grid of the eleventh field effect transistor M11 is connected with a Ctrl terminal; the source electrode of the eleventh field effect transistor M11 is simultaneously connected with the drain electrodes of the twelfth field effect transistor M12 and the fourteenth field effect transistor M14; the source electrode of the twelfth field effect transistor M12 is connected with the drain electrode of the thirteenth field effect transistor M13; the source electrode of the fourteenth field effect transistor M14 is connected with the drain electrode of the fifteenth field effect transistor M15; the source electrode of the thirteenth field effect transistor M13 is connected with the source electrode of the fifteenth field effect transistor M15 and then grounded; the grid electrode of the sixteenth field-effect tube M16 is connected with the source electrode of the eleventh field-effect tube M11; the drain electrode of the sixteenth field effect transistor M16 is connected with the drain electrode of the eleventh field effect transistor M11 and then is connected with the power supply; the drain electrode of the seventeenth field-effect tube M17 is connected with the drain electrode of the nineteenth field-effect tube M19 and then connected with the source electrode of the sixteenth field-effect tube M16; the source electrode of the seventeenth field effect transistor M17 is connected with the drain electrode of the eighteenth field effect transistor M18; the source electrode of the nineteenth field effect transistor M19 is connected with the drain electrode of the twentieth field effect transistor M20; the source electrode of the eighteenth field effect transistor M18 is connected with the source electrode of the twentieth field effect transistor M20 and then grounded; a second inverter Inv2 is connected between the drain of the seventeenth field-effect transistor M17 and the drain of the nineteenth field-effect transistor M19;
wherein, the grid of the first field effect tube M1 is connected with a test signal Ctrl;
the grid electrode of the second field effect transistor M2 and the grid electrode of the seventh field effect transistor M7 are simultaneously connected with a clock signal CK;
the grid electrode of the fourth field effect transistor M4 and the grid electrode of the ninth field effect transistor M9 are simultaneously connected with an inverted signal CK _ n of the clock signal;
the grid electrode of the fifth field effect transistor M5 and the grid electrode of the tenth field effect transistor M10 are simultaneously connected with an input signal D;
the grid of the third field effect transistor M3, the grid of the eighth field effect transistor M8 and the output end of the first inverter Inv1 are connected to output the first signal Y;
wherein, the grid electrode of the eleventh field effect transistor M11 is connected with a test signal Ctrl;
the grid electrode of the twelfth field effect transistor M2 and the grid electrode of the seventeenth field effect transistor M17 are simultaneously connected with an inverted signal CK _ n of the clock signal;
the grid electrode of the fourteenth field effect transistor M14 and the grid electrode of the nineteenth field effect transistor M19 are simultaneously connected with a clock signal CK;
wherein, the grid of the fifteenth field effect transistor M15 is connected with the grid of the twentieth field effect transistor M20 to output a first signal Y;
the grid of the thirteenth field-effect tube M13, the grid of the eighteenth field-effect tube M18 and the output end of the second inverter Inv2 are connected to output the second signal Q; when the clock signal CK is at a low level, the grid electrode of the fifth field effect transistor M5 and the grid electrode of the tenth field effect transistor M10 are simultaneously connected with the input signal D, so that the input signal D is equal to the first signal Y; the first signal is latched at a high level of the clock signal CK so that the second signal Q is equal to the first signal Y.
The principle of the invention is as follows: the invention is composed of an upper D latch and a lower D latch, and the work flow is also divided into two stages. Firstly, latching an input signal D at a low level of a clock signal CK by a first field effect transistor M1 to a tenth field effect transistor M10 to ensure that an output first signal Y is the same as the input signal D; after a time sequence, the eleventh field effect transistor M11 to the twentieth field effect transistor M20 latch the output first signal Y when the clock signal CK is at a high level, so that the output second signal Q is the same as the output first signal Y; therefore, the output second signal Q will be equal to the input signal D at the last clock signal CK low level when the clock signal CK is high level. According to the circuit working principle, the pull-down circuit is cut off when the pull-up circuit is switched on, the pull-up circuit is cut off when the pull-down circuit is switched on, and only a part of transistors are switched on when the circuit works, so that the power consumption of the circuit can be reduced.
Under the control of the timing chart shown in fig. 2, the specific operation principle of the present invention will be described by taking the first to tenth fets M1 to M10 as an example.
Let Ctrl = Vdd, the first fet M1 is always on. When the clock signal CK is at a low level, the second field effect transistor M2 and the seventh field effect transistor M7 are turned off, the fourth field effect transistor M4 and the ninth field effect transistor M9 are turned on, at this time, if the input signal D is at a low level, the fifth field effect transistor M5 and the tenth field effect transistor M10 are turned off, the pull-down circuit is turned off, and since the first field effect transistor M1 is turned on and the point a is at a high level, the sixth field effect transistor M6 is turned on, so that the negation signal Y _ n of the first signal is at a high level, and after negation of the first phase inverter Inv1, the first signal Y is at a low level, and the input signal D is equal to the first signal Y; if the input signal D is at a high level, the fifth fet M5 and the tenth fet M10 are turned on, so that the pull-down circuit is turned on, the point a is pulled to a low level, so that the sixth fet M6 is turned off, the inverted signal Y _ n of the first signal becomes a low level, after being inverted by the first inverter Inv1, the first signal Y is at a high level, the input signal D is equal to the first signal Y, and the input signal D is latched when the clock signal CK is at a low level. The third fet M3 and the eighth fet M8 are configured to keep the first signal Y unchanged when the clock signal CK is at a high level. When the clock signal CK is at a high level, the eleventh to twentieth field effect transistors M11 to M20 and the second inverter Inv2 make the second signal Q identical to the output first signal Y, thereby realizing a high-level triggered D flip-flop.
According to the invention, only the N-type tube is arranged, and the on-off of the pull-up tube is controlled, so that when one of the pull-up circuit and the pull-down circuit is switched on, the other one is switched off, and the power consumption of the circuit is reduced. Because the output of the circuit is related to the size ratio of the transistors, the use of large-sized transistors can be avoided, and the circuit area can be reduced by using the transistors with smaller width-length ratio and proper ratio.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included therein.
Claims (1)
1. A D flip-flop circuit based on IGZO TFT comprises two pure N-type D latches with the same structure, and is characterized in that: the two pure N-type D latches are connected through a proportional structure: the two pure N-type D latches are respectively: a first pure N-type D latch and a second pure N-type D latch;
the first pure N-type D latch comprises a first field effect tube (M1), a second field effect tube (M2), a third field effect tube (M3), a fourth field effect tube (M4), a fifth field effect tube (M5), a sixth field effect tube (M6), a seventh field effect tube (M7), an eighth field effect tube (M8), a ninth field effect tube (M9), a tenth field effect tube (M10) and a first phase inverter (Inv 1);
wherein, the grid of the first field effect transistor (M1) is connected with a Ctrl terminal; the source electrode of the first field effect transistor (M1) is simultaneously connected with the drain electrodes of the second field effect transistor (M2) and the fourth field effect transistor (M4); the source electrode of the second field effect transistor (M2) is connected with the drain electrode of the third field effect transistor (M3); the source electrode of the fourth field effect transistor (M4) is connected with the drain electrode of the fifth field effect transistor (M5); the source electrode of the third field effect transistor (M3) is connected with the source electrode of the fifth field effect transistor (M5) and then grounded; the grid electrode of the sixth field effect transistor (M6) is connected with the source electrode of the first field effect transistor (M1); the drain electrode of the sixth field effect tube (M6) is connected with the drain electrode of the first field effect tube (M1) and then is connected with a power supply; the drain electrode of the seventh field effect tube (M7) is connected with the drain electrode of the ninth field effect tube (M9) and then connected with the source electrode of the sixth field effect tube (M6); the source electrode of the seventh field effect transistor (M7) is connected with the drain electrode of the eighth field effect transistor (M8); the source electrode of the ninth field effect transistor (M9) is connected with the drain electrode of the tenth field effect transistor (M10); the source electrode of the eighth field effect transistor (M8) is connected with the source electrode of the tenth field effect transistor (M10) and then grounded; a first inverter (Inv 1) is connected between the drain electrode of the seventh field-effect tube (M7) and the drain electrode of the ninth field-effect tube (M9);
wherein, the grid of the first field effect tube (M1) is connected with a test signal (Ctrl);
wherein, the grid of the second field effect transistor (M2) and the grid of the seventh field effect transistor (M7) are simultaneously connected with a clock signal (CK);
the grid electrode of the fourth field effect transistor (M4) and the grid electrode of the ninth field effect transistor (M9) are simultaneously connected with an inverted signal (CK _ n) of the clock signal;
wherein, the grid of the fifth field effect transistor (M5) and the grid of the tenth field effect transistor (M10) are simultaneously connected with the input signal (D);
the grid electrode of the third field effect transistor (M3), the grid electrode of the eighth field effect transistor (M8) and the output end of the first inverter (Inv 1) are connected and then output a first signal (Y);
the second pure N-type D latch comprises an eleventh field-effect tube (M11), a twelfth field-effect tube (M12), a thirteenth field-effect tube (M13), a fourteenth field-effect tube (M14), a fifteenth field-effect tube (M15), a sixteenth field-effect tube (M16), a seventeenth field-effect tube (M17), an eighteenth field-effect tube (M18), a nineteenth field-effect tube (M19), a twentieth field-effect tube (M20) and a second phase inverter (Inv 2);
wherein, the grid of the eleventh field effect transistor (M11) is connected with the Ctrl terminal; the source electrode of the eleventh field effect transistor (M11) is simultaneously connected with the drain electrodes of the twelfth field effect transistor (M12) and the fourteenth field effect transistor (M14); the source electrode of the twelfth field effect transistor (M12) is connected with the drain electrode of the thirteenth field effect transistor (M13); the source electrode of the fourteenth field effect transistor (M14) is connected with the drain electrode of the fifteenth field effect transistor (M15); the source electrode of the thirteenth field effect transistor (M13) is connected with the source electrode of the fifteenth field effect transistor (M15) and then grounded; the grid electrode of the sixteenth field effect transistor (M16) is connected with the source electrode of the eleventh field effect transistor (M11); the drain electrode of the sixteenth field effect transistor (M16) is connected with the drain electrode of the eleventh field effect transistor (M11) and then is connected with a power supply; the drain electrode of the seventeenth field effect transistor (M17) is connected with the drain electrode of the nineteenth field effect transistor (M19) and then connected with the source electrode of the sixteenth field effect transistor (M16); the source electrode of the seventeenth field effect transistor (M17) is connected with the drain electrode of the eighteenth field effect transistor (M18); the source electrode of the nineteenth field effect transistor (M19) is connected with the drain electrode of the twentieth field effect transistor (M20); the source electrode of the eighteenth field effect transistor (M18) is connected with the source electrode of the twentieth field effect transistor (M20) and then grounded; a second inverter (Inv 2) is connected between the drain electrode of the seventeenth field-effect tube (M17) and the drain electrode of the nineteenth field-effect tube (M19);
wherein, the grid of the eleventh field effect transistor (M11) is connected with the test signal (Ctrl);
wherein, the grid of the twelfth field effect tube (M2) and the grid of the seventeenth field effect tube (M17) are simultaneously connected with the inverted signal (CK _ n) of the clock signal;
wherein, the grid of the fourteenth field effect transistor (M14) and the grid of the nineteenth field effect transistor (M19) are simultaneously connected with a clock signal (CK);
wherein, the grid of the fifteenth field effect transistor (M15) is connected with the grid of the twentieth field effect transistor (M20) to output a first signal (Y);
the grid electrode of the thirteenth field effect transistor (M13), the grid electrode of the eighteenth field effect transistor (M18) and the output end of the second inverter (Inv 2) are connected and then output a second signal (Q);
when the clock signal (CK) is low, the grid of the fifth field effect transistor (M5) and the grid of the tenth field effect transistor (M10) are simultaneously connected with the input signal (D), so that the input signal (D) is equal to the first signal (Y); the first signal is latched at a high level of the clock signal (CK) so that the second signal (Q) is equal to the first signal (Y).
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| CN201910546215.6A CN110391797B (en) | 2019-06-20 | 2019-06-20 | D trigger circuit based on IGZO TFT |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910546215.6A CN110391797B (en) | 2019-06-20 | 2019-06-20 | D trigger circuit based on IGZO TFT |
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| CN110391797A CN110391797A (en) | 2019-10-29 |
| CN110391797B true CN110391797B (en) | 2023-04-18 |
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| CN108649927A (en) * | 2018-07-05 | 2018-10-12 | 华南理工大学 | A kind of low-power consumption d type flip flop |
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| JP3958322B2 (en) * | 2004-01-28 | 2007-08-15 | シャープ株式会社 | Shift register and active matrix display device |
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| JP2000187994A (en) * | 1998-04-28 | 2000-07-04 | Sharp Corp | Latch circuit, shift register circuit, and picture display device |
| CN1664903A (en) * | 2004-03-06 | 2005-09-07 | 鸿富锦精密工业（深圳）有限公司 | Mixed latch trigger |
| WO2017084217A1 (en) * | 2015-11-16 | 2017-05-26 | 东南大学 | E-tspc structure-based low-power-consumption 2/3 frequency divider circuit |
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