CN110386585A - Preparation method of porous silicon substrate and porous silicon substrate - Google Patents

Preparation method of porous silicon substrate and porous silicon substrate Download PDF

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Publication number
CN110386585A
CN110386585A CN201810358053.9A CN201810358053A CN110386585A CN 110386585 A CN110386585 A CN 110386585A CN 201810358053 A CN201810358053 A CN 201810358053A CN 110386585 A CN110386585 A CN 110386585A
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silicon substrate
porous
layer
silicon
porosity
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李光宇
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Shanghai Industrial Utechnology Research Institute
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Shanghai Industrial Utechnology Research Institute
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B1/00Devices without movable or flexible elements, e.g. microcapillary devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444Surface micromachining, i.e. structuring layers on the substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523Etching material
    • B81C1/00539Wet etching

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Weting (AREA)

Abstract

The invention relates to the field of porous silicon substrate materials in MEMS (micro-electromechanical systems) technology, in particular to a preparation method of a porous silicon substrate and the porous silicon substrate. The preparation method of the porous silicon substrate comprises the following steps: providing a silicon substrate; and carrying out layered electrochemical corrosion on the silicon substrate to form a multi-layer porous structure arranged along the longitudinal direction of the silicon substrate, wherein the porosity of the surface layer porous structure is less than or equal to that of any other layer porous structure. The invention ensures that the substrate not only can keep high porosity on the whole, but also has good structural stability, so that the porous silicon substrate realizes good coverage of a deposition layer on the basis of ensuring good heat insulation performance.

Description

The preparation method at porous silicon-base bottom and porous silicon-base bottom
Technical field
The present invention relates to porous silicon-base bottom material field in MEMS technology more particularly to a kind of preparation sides at porous silicon-base bottom Method and porous silicon-base bottom.
Background technique
In recent years, the rapid development of MEMS (Micro-Electro-Mechanical System) technology has benefited from it Electronics and mechanical property are combined.Since the sense of chemical reaction, electrical effect and realization to heat can occurs in it simultaneously Know, makes it possible to the function of being performed simultaneously physics, chemistry, biology etc..
Currently, passing through the heat or utilization heat that aware circuit generates in the sensing technology realized using MEMS technology Radiation is its important branch as signal perception approach, and this requires the substrates of senser element to have good insulation special Property, stability and processing compatibility.The quick sensor-based system of low-grade fever is mainly made of low-grade fever dependent sensor and its control circuit, main Using low-grade fever dependent sensor to the sensitive perception principle of temperature, to such as IR (Infrared Radiation, infra-red radiation), UV The non-electrical such as (Ultraviolet radiation, ultraviolet radioactive), gas flow, gas componant, high frequency power or blood flow The physical quantity of amount is detected, such as miniature heating plate, and low-grade fever dependent sensor is the gas flow based on low-grade fever amount difference principle The non electrical quantity physical quantity detected is simultaneously changed into electric quantity signal by sensor, using exporting after the processing of control circuit.
Mechanics design requirement to low-grade fever dependent sensor is mechanical strength with higher, and emphasis is the machine of support membrane substrate Tool stability;Thermal design requires the problem of being then thermal response rates to be solved, temperature distribution evenness and thermal conductivity low aspect. Existing MEMS technology often needs to use insulation substrate to manufacture device.Current technique generally select to the back side of wafer into Row deep silicon etching, to generate local hanging structure to carry out thermal insulation.But there is stability difference in this technique, This is because sensitive membrane Stress Control is bad to be easily deformed rupture, the failure of device is eventually led to.Also there is utilization in the prior art SIO layers or SIN layers as heat insulation layer, but heat insulation is poor, causes heat loss very fast, reduces thermal response rates.Also it adopts The lower material of the thermal conductivities such as organic polymer is used as heat insulation layer to realize thermal insulation, however non-silicon material and IC (Integrated Circuit, integrated circuit) technique is incompatible, this, which will lead to sensor, can not push the limitation of volume production.
Therefore, how to make the substrate of semiconductor devices be provided simultaneously with good heat-insulating property and structural stability, be mesh Preceding technical problem urgently to be resolved.
Summary of the invention
The present invention provides preparation method and the porous silicon-base bottom at a kind of porous silicon-base bottom, to solve in the prior art half Conductor device substrate cannot be provided simultaneously with the problem of good heat-insulating property and structural stability.
To solve the above-mentioned problems, the present invention provides a kind of preparation method at porous silicon-base bottom, include the following steps:
One silicon substrate is provided;
Layering electrochemical corrosion is carried out to the silicon substrate, to form the multi-layer porous of the longitudinal arrangement along the silicon substrate Property structure, and the porosity of surface layer cellular structure be less than or equal to other any layer cellular structures porosity.
Preferably, layering electrochemical corrosion is carried out to the silicon substrate using the different corrosion parameter of multiple groups, so that being formed Multi-layer porous property structure at least two layers cellular structure porosity and/or thickness it is different.
Preferably, the corrosion parameter includes current density.
Preferably, layering electrochemical corrosion is carried out to the silicon substrate respectively using a variety of different current densities, and applied The current density for being added on surface layer is less than or equal to other layers.
Preferably, the corrosion parameter further includes etching time;Using a variety of different current densities and with each electricity The corresponding etching time of current density carries out layering electrochemical corrosion to the silicon substrate.
Preferably, carrying out layering electrochemical corrosion before to the silicon substrate using the different corrosion parameter of multiple groups further includes Following steps:
One layer of silicon nitride film is deposited in the surface of silicon;
The silicon nitride film is performed etching, to form patterned mask layer.
Preferably, the specific steps of layering electrochemical corrosion are carried out to the silicon substrate using the different corrosion parameter of multiple groups Include:
A pair of electrodes is provided;
Etching liquid is mixed to get using the hydrofluoric acid, ethyl alcohol and deionized water of preset ratio;
The electrode and the silicon substrate are placed in the etching liquid, and using the different corrosion parameter of multiple groups to described Silicon substrate carries out layering electrochemical corrosion.
Preferably, the volume ratio of hydrofluoric acid, ethyl alcohol and deionized water is V in etching liquidHydrofluoric acid: VEthyl alcohol: VDeionized water=(1:1:1) ~(1:1:4).
Preferably, carrying out layering electrochemical corrosion later to the silicon substrate using the different corrosion parameter of multiple groups further includes Following steps:
The silicon substrate with multi-layer porous property structure is rinsed using deionized water;
The silicon substrate through rinsing is impregnated into preset time in organic solvent;
The soaking silicon substrate is dried up, using dry gas to remove remaining organic solvent in the silicon substrate.
To solve the above-mentioned problems, the present invention also provides a kind of porous silicon-base bottom, including silicon substrate, the silicon substrate tools Have along its longitudinally disposed multi-layer porous property structure, and the porosity of surface layer cellular structure is more less than or equal to other any layers The porosity of permeability structure.
Preferably, the porosity of at least two layers cellular structure is different in multi-layer porous property structure.
Preferably, multi-layer porous property structure includes surface layer cellular structure, middle layer cellular structure and underlying porous Structure, and the porosity of middle layer cellular structure is higher than the porosity of surface layer cellular structure.
Preferably, the thickness of at least two layers cellular structure is different in multi-layer porous property structure.
Preferably, multi-layer porous property structure includes surface layer cellular structure, middle layer cellular structure and underlying porous Structure, and the thickness of middle layer cellular structure is greater than the thickness of surface layer cellular structure.
The preparation method at porous silicon-base bottom provided by the invention and porous silicon-base bottom, by carrying out layering electrification to silicon substrate Corrosion is learned, forms multi-layer porous property structure in the silicon substrate, and the porosity of surface layer cellular structure is less than or equal to it The porosity of his any layer cellular structure so that the porous silicon-base bottom can keep on the whole high porosity and With good structural stability, i.e., the good covering of sedimentary is realized on the basis of ensuring good thermo-insulation properties.
Detailed description of the invention
Attached drawing 1 is the preparation method flow chart at the porous silicon-base bottom of the specific embodiment of the invention;
Attached drawing 2 is the porous silicon-base bottom that the preparation method at the porous silicon-base bottom of the specific embodiment of the invention is prepared Structural schematic diagram;
Attached drawing 3 is the electrochemical corrosion device structural schematic diagram of the specific embodiment of the invention;
Attached drawing 4 is the scanning electron microscope (SEM) photograph of multi-layer porous property structure in the porous silicon-base bottom of the specific embodiment of the invention;
Attached drawing 5 is the scanning electron microscope of two layers of cellular structure interface in the porous silicon-base bottom of the specific embodiment of the invention Figure;
Attached drawing 6 is the porous silicon-base bottom surface topography scan electron microscope of the specific embodiment of the invention.
Specific embodiment
The specific implementation at the preparation method to porous silicon-base bottom provided by the invention and porous silicon-base bottom with reference to the accompanying drawing Mode elaborates.
Present embodiment provides a kind of preparation method at porous silicon-base bottom, and attached drawing 1 is specific embodiment party of the present invention The preparation method flow chart at the porous silicon-base bottom of formula, attached drawing 2 are the preparation sides at the porous silicon-base bottom of the specific embodiment of the invention The structural schematic diagram at the porous silicon-base bottom that method is prepared.As shown in Figure 1, the porous silicon-base bottom that present embodiment provides Preparation method includes the following steps:
Step S11 provides a silicon substrate 21.The physical parameter of the silicon substrate 21 is preferably silicon wafer crystal orientation (100), resistance The 0.01 Ω cm of Ω cm~0.02 of rate, and boron doping (B-dropped) has been carried out in the silicon substrate 21.
Step S12 carries out layering electrochemical corrosion to the silicon substrate 21, to form the longitudinal direction row along the silicon substrate 21 The multi-layer porous property structure of column, and the porosity of surface layer cellular structure is less than or equal to the hole of other any layer cellular structures Gap rate.Wherein, surface layer cellular structure refers to the porosity knot for being used to deposit the surface of other film layers positioned at the silicon substrate 21 Structure layer;Other layer of cellular structure refers to the cellular structure layer in multi-layer porous property structure except skim-coat cellular structure.
Preferably, it includes: different using multiple groups for carrying out the specific steps of layering electrochemical corrosion to the silicon substrate 21 Corrosion parameter carries out layering electrochemical corrosion to the silicon substrate 21, so that in the multi-layer porous property structure formed at least more than two layers The porosity and/or thickness of permeability structure are different.Specifically, in the mistake for carrying out electrochemical corrosion to the silicon substrate 21 Cheng Zhong corrodes journey to different zones in the silicon substrate 21 to realize by adjusting the corrosion parameter in electrochemical corrosion course The adjustment of degree, to obtain the multi-layer porous property structure along its longitudinal arrangement in the silicon substrate 21.
By the way that the porosity and/or thickness of every layer of cellular structure is rationally arranged, so that the hole of porous silicon-base bottom entirety Rate keeps optimal level, so that it is guaranteed that the good heat-insulating property in porous silicon-base bottom;Meanwhile keeping surface layer cellular structure Porosity is less than or equal to other layers, facilitates the surface apertures for controlling the porous silicon-base bottom, realizes the good of subsequent deposited layers Good covering.
The trend of inverse ratio is presented in the thermal conductivity and the thickness of cellular structure, porosity at porous silicon-base bottom, however excessively The cellular structure number of plies will increase the complexity of technique.Generally, 3-4 layers of cellular structure can meet applied to thermal insulation It can substrate.For example, multi-layer porous property structure includes 4 layers of cellular structure, this 4 layers of cellular structures are along the vertical of the silicon substrate 21 To arrangement, and it is used separately as membrane structure supporting layer, main heat insulation layer, secondary heat insulation layer and silicon structure transition zone from top to bottom. There is other function, such as the application with other performances such as sacrificial layer, adsorption layers if necessary to the porous silicon-base bottom, then root According to the number of plies for needing to increase accordingly cellular structure.
For example, as shown in Fig. 2, the multi-layer porous property structure include along the longitudinal direction of the silicon substrate 21 from top to bottom successively Surface layer 231, middle layer 232 and the bottom 233 of stacking, wherein surface layer 231 is used as membrane structure supporting layer, middle layer 232 is used as absolutely Thermosphere, bottom 233 are used as silicon structure transition zone.In order to enable the heat insulation layer has good insulation effect, the surface layer 231 Porosity be lower than the middle layer 232 porosity.Wherein, the porosity of middle layer 232 can be less than, be more than or equal to The porosity of bottom 233, present embodiment are not construed as limiting this.On the basis of with above-mentioned porosity relationship, each layer The thickness of cellular structure can be configured according to actual needs.
For another example as shown in Fig. 2, the multi-layer porous property structure include along the longitudinal direction of the silicon substrate 21 from top to bottom according to Surface layer 231, middle layer 232 and the bottom 233 of secondary stacking.Wherein, surface layer 231 with a thickness of 3um~10um, for use as subsequent The membrane structure supporting layer of MEMS technology;Middle layer 232 with a thickness of 40um~80um, be mainly used for embodying the porous silicon-base The good heat-insulating property in bottom, thus the heat insulation layer as porous silicon-base bottom;Bottom 233 with a thickness of 30um-60um, be used for more Stabilization transition between permeability structure and other silicon structures of silicon substrate 21, thus it is used as silicon structure transition zone.It is above only to lift Example explanation, the specific thickness of each layer of cellular structure, those skilled in the art may set according to actual needs.
By the study found that can be served as a contrast in the silicon using different corrosion parameters to silicon substrate progress electrochemical corrosion The cellular structure with different porosities is formed in bottom.Silicon substrate with cellular structure have excellent thermal property and Mechanical performance, while can also continue the characteristic of silicon materials Yu IC process compatible, having in the production of MEMS basal layer can not The advantage of analogy provides possibility to improve the performance of low-grade fever dependent sensor.Due in the cellular structure of the silicon substrate 21 There are the microchannels of many sponge hole shapes, form the microcavity of storage air, air is as best thermal resistance substance, so that having The silicon substrate of cellular structure has good heat-insulating property, plays certain barrier action to the conduction of heat.Usually, Porosity in cellular structure is higher, and air is more in microcavity, and the heat-insulating property of silicon substrate will be better;But high hole The aperture that rate will lead to the surface of silicon is larger, therefore, in order to ensure the structural stability at porous silicon-base bottom, in subsequent work Complete and good coverage rate could be had by needing to deposit thicker film layer in skill, and it is whole that this not only will increase the porous silicon-base bottom The thickness of body, the volume for increasing porous silicon-base bottom, but also the process time can be extended, increase manufacturing cost.
In this embodiment, by forming the longitudinal arrangement along the silicon substrate 21 in the silicon substrate 21 Multi-layer porous property structure, and make the porosity of surface layer cellular structure less than or equal to the hole of other any layer cellular structures Gap rate.It is reduced although making the porosity of surface layer cellular structure, but as long as the hole of other layer of cellular structure is rationally arranged The number of plies of rate, thickness or cellular structure still can make the silicon substrate 21 be able to maintain higher hole on the whole Gap rate.Meanwhile the cellular structure porosity on 21 surface layer of silicon substrate is lower, and well covering for subsequent deposited layers may be implemented Lid;21 bottom of silicon substrate then has the cellular structure of higher porosity, then may insure that porous silicon-base bottom is good absolutely Hot property.
Preferably, further include following steps before carrying out layering electrochemical corrosion to the silicon substrate 21:
I) one layer of silicon nitride film is deposited on 21 surface of silicon substrate.Silicon nitride film have excellent mechanical performance and Inactivating performance, can to its bottom silicon substrate 21 formation be effectively protected.Wherein, in the 21 surface cvd nitride of silicon substrate The method of silicon thin film, preferably plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD).
II) silicon nitride film is performed etching, to form patterned mask layer 22.It specifically, is to deposition The silicon nitride film carry out photoetching, etching, degumming process, formed using silicon nitride as the graphic structure of exposure mask, to expose State region to be etched in silicon substrate 21.
In order to obtain satisfactory porosity in each layer of cellular structure of the silicon substrate, it is preferred that described Corrosion parameter includes current density, carries out the tool of layering electrochemical corrosion to the silicon substrate using the different corrosion parameter of multiple groups Body step includes:
Layering electrochemical corrosion is carried out to the silicon substrate 21 respectively using a variety of different current densities, and is applied to table Lyer current density is less than or equal to other layers.Wherein, surface layer refers to the table for being used to deposit other film layers positioned at the silicon substrate 21 The layer in face.This is because the current density being applied on silicon substrate is bigger during carrying out electrochemical corrosion, obtain The porosity of cellular structure is bigger.Therefore, it by the control to current density, can simple, convenient, accurately control each The porosity of layer cellular structure.Specifically, the silicon substrate 21 is divided respectively using a variety of different current densities During layer electrochemical corrosion, the current density of current source generation is adjusted flexibly, to realize to every layer of cellular structure The control of porosity.
For example, current density can be set to gradually being increased along 21 longitudinal direction of silicon substrate by the direction on surface layer to bottom Greatly;It can also will be applied to the smaller of the current density setting on surface layer and bottom, and be applied to the centre between surface layer and bottom The current density of layer is arranged larger.The above is only for example, those skilled in the art should control application according to actual needs Current density on each layer.
In order to preferably control the porosity of each honeycomb sandwich, it is furthermore preferred that the corrosion parameter further includes corrosion Time includes: to adopt using the specific steps that the different corrosion parameter of multiple groups carries out layering electrochemical corrosion to the silicon substrate 21 Layering electricity is carried out to the silicon substrate 21 with a variety of different current densities and etching time corresponding with each current density Chemical attack.Wherein, the specific value of etching time corresponding with each current density depends on cellular structure to be formed The thickness of layer.
For example, increased by controlling the etching time with the increase of current density, higher hole can be made The cellular structure layer of rate has biggish thickness, and then has lesser thickness compared with the cellular structure layer of low porosity, into One step is ensuring that the silicon substrate 21 while keeping whole high porosity, reduces the aperture on its surface layer.For example, to the silicon Multilayer in substrate 21 is respectively according to the current density successively applied along the longitudinal direction from top to bottom of the silicon substrate 21 5mA/cm2、10mA/cm2、25mA/cm2、45mA/cm2, etching time corresponding with above-mentioned current density be respectively 300s, The whole porosity of 500s, 900s, 1800s, the porous silicon-base bottom obtained at this time may remain in 50%~70%.Pass through control Adding up for different current densities and etching time, can obtain the pore appearance multi-layer porous silicon base different with structure.
Attached drawing 3 is the electrochemical corrosion device structural schematic diagram of the specific embodiment of the invention.Preferably, not using multiple groups With corrosion parameter to the silicon substrate 21 carry out layering electrochemical corrosion specific steps include:
(S13-1) a pair of electrodes 31 is provided.In order to obtain preferable electrochemical corrosion effect, the ruler of the preferably described electrode 31 It is very little identical as the size of the silicon substrate 21.The specific material of the electrode, those skilled in the art can be according to actual needs It is selected, platinum electrode can be but not limited to.
(S13-2) etching liquid 32 is mixed to get using hydrofluoric acid, ethyl alcohol and the deionized water of preset ratio.
(S13-3) electrode 31 is placed in the etching liquid 32 with the silicon substrate 21, and different using multiple groups Corrosion parameter carries out layering electrochemical corrosion to the silicon substrate 21.
Specifically, as shown in figure 3, carrying out providing an etching tank in electrochemical corrosion course to the silicon substrate 21 34, the etching tank 34 is divided into two pilot trench 342 by partition 341, filled with equivalent, isoconcentration in two pilot trench 342 The etching liquid 32 is provided with an opening in the partition 341, and the opening is for accommodating 21 (the i.e. described silicon of silicon substrate Substrate 21 is not connected directly with power supply), etching liquid in two pilot trench 342 is realized with the silicon substrate 21 by the partition 341 Physical isolation.Two electrodes 31 are respectively placed in two pilot trench 342, and two electrodes 31 respectively with power supply 33 anode, cathode connection, using the etching liquid as medium, the bias voltage of the output of power supply 33 passes through each parallel to institute Two electrodes 31 for stating silicon substrate 21 are applied to the silicon substrate 21, realize the electrochemical corrosion to the silicon substrate 21.
In order to ensure the etching homogeneity of each layer of cellular structure in electrochemical corrosion course, it is required that corrosion is each The constant current density of layer, the constant concentration and temperature of the etching liquid are controlled at 20 DEG C.
Preferably, the volume ratio of hydrofluoric acid, ethyl alcohol and deionized water is V in the etching liquidHydrofluoric acid: VEthyl alcohol: VDeionized water=(1: 1:1)~(1:1:4).
Preferably, the silicon substrate 21 also wrap after layering electrochemical corrosion using multiple groups different corrosion parameter Include following steps:
A) silicon substrate 21 with multi-layer porous property structure is rinsed using deionized water.In order to ensure completely removing The reaction products such as the silicate generated in electrochemical corrosion course need to serve as a contrast the silicon with cellular structure using deionized water Bottom 21 elutes 10min~20min repeatedly.
B) silicon substrate 21 through rinsing is impregnated into preset time in organic solvent.Wherein, the organic solvent can To be but not limited to ethyl alcohol or IPA (Isopropyl Alcohol, isopropanol).The preset time be preferably 10min~ 20min。
C) the soaking silicon substrate 21 is dried up using dry gas, it is remaining organic in the silicon substrate 21 to remove Solvent.In order to avoid the property to the silicon substrate 21 impacts, it is preferred that the dry gas is nitrogen or indifferent gas Body.During drying up silicon substrate 21 using dry gas, surface can be reduced by the quick volatilization of organic solvent Stress when dehydration avoids causing to damage to the multi-layer porous property structure in the silicon substrate 21.
Attached drawing 4 is the scanning electron microscope (SEM) photograph of multi-layer porous property structure in the porous silicon-base bottom of the specific embodiment of the invention, attached Fig. 5 is the scanning electron microscope (SEM) photograph of two layers of cellular structure interface in the porous silicon-base bottom of the specific embodiment of the invention, and attached drawing 6 is The porous silicon-base bottom surface topography scan electron microscope of the specific embodiment of the invention.As shown in Figure 4, using different corrosion parameters After carrying out electrochemical corrosion to the different layers in silicon substrate, the gap pattern multi-layer porous property structure different with structure is obtained. As shown in Figure 5, after carrying out electrochemical corrosion to the different layers in silicon substrate using different corrosion parameters, adjacent two layers porosity The interface of structure is clear and contact is complete.It will be appreciated from fig. 6 that carrying out electricity to the different layers in silicon substrate using different corrosion parameters After chemical attack, silicon substrate surface layer aperture is 20nm~50nm, can be realized the good covering of subsequent deposited layers.
To solve the above-mentioned problems, present embodiment additionally provides a kind of porous silicon-base bottom, including silicon substrate, described Silicon substrate has along its longitudinally disposed multi-layer porous property structure, and the porosity of surface layer cellular structure is less than or equal to other The porosity of any layer cellular structure.
Preferably, the porosity of at least two layers cellular structure is different in multi-layer porous property structure.It is furthermore preferred that more Layer cellular structure includes surface layer cellular structure, middle layer cellular structure and underlying porous structure, and middle layer porosity The porosity of structure is higher than the porosity of surface layer cellular structure.
Preferably, the thickness of at least two layers cellular structure is different in multi-layer porous property structure.It is furthermore preferred that multilayer Cellular structure includes surface layer cellular structure, middle layer cellular structure and underlying porous structure, and middle layer porosity knot The thickness of structure is greater than the thickness of surface layer cellular structure.
Porous silicon-base bottom with multi-layer porous property structure, can be used as the new material in low-grade fever dependent sensor.It is used as The semiconductor devices of micro- heating plate can reduce thermal diffusion, realize the characteristic of low-power consumption;For passing through infrared heat response principle system The coefficient of thermal response can be improved using the porous silicon-base bottom with multi-layer porous property structure for standby sensor, to improve half The sensitivity of conductor device.Therefore, had using the semiconductor devices of the porous silicon-base bottom preparation with multi-layer porous property structure Small in size, high sensitivity, at low cost, small power consumption, easy mass production, mechanical electric be strong and stable processing technology etc. is excellent Point.
The preparation method at the porous silicon-base bottom that present embodiment provides and porous silicon-base bottom, by using a variety of differences Corrosion parameter layering electrochemical corrosion is carried out to silicon substrate, to form multi-layer porous property structure, surface layer in the silicon substrate The porosity of cellular structure is less than or equal to the porosity of other layer of cellular structure, so that the substrate can be on the whole High porosity is kept, and there can be good structural stability, so that porous silicon-base bottom is in the base for guaranteeing good thermo-insulation properties The good covering of sedimentary is realized on plinth.
Embodiment 1
The preparation method for present embodiments providing a kind of porous silicon-base bottom with high heat dispersion, specifically includes following step It is rapid:
(1-1) provides a silicon substrate, and deposits a patterned silicon nitride film as exposure mask in the surface of silicon Layer.
(1-2) takes hydrofluoric acid, ethyl alcohol and deionized water to be sufficiently mixed, and obtains etching liquid, and hydrofluoric acid, ethyl alcohol and deionization The volume ratio of water is VHydrofluoric acid: VEthyl alcohol: VDeionized water=1:1:4.
(1-3) using a pair of electrodes of size identical as silicon substrate to be corroded come to the silicon substrate into layering electrochemistry Corrosion, wherein longitudinal current density applied from surface layer to bottom along the silicon substrate is followed successively by 5mA/cm2、25mA/cm2、 45mA/cm2, the etching time from surface layer to bottom is followed successively by 300s, 500s, 900s.By electrochemical corrosion course, can obtain To three layers of cellular structure with different porosities, different hole densities and different-thickness.
It is the uniformity for guaranteeing etching during carrying out electrochemical corrosion, needs to form each layer of porosity in corrosion Current density is kept constant during structure, and the concentration of etching liquid is kept constant and temperature control is at 20 DEG C.
(1-4) using deionized water to the silicon substrate with three layers of cellular structure elute repeatedly 10min~ 20min。
The silicon substrate through rinsing is impregnated displacement 10min~20min by (1-5) in ethyl alcohol or IPA, uses nitrogen later Gas dries up the silicon substrate.
Embodiment 2
The preparation method for present embodiments providing a kind of porous silicon-base bottom with high mechanical strength, specifically includes following step It is rapid:
(2-1) provides a silicon substrate, and deposits a patterned silicon nitride film as exposure mask in the surface of silicon Layer;
(2-2) takes hydrofluoric acid, ethyl alcohol and deionized water to be sufficiently mixed, and obtains etching liquid, and hydrofluoric acid, ethyl alcohol and deionization The volume ratio of water is VHydrofluoric acid: VEthyl alcohol: VDeionized water=1:1:2.
(2-3) using a pair of electrodes of size identical as silicon substrate to be corroded come to the silicon substrate into layering electrochemistry Corrosion, wherein longitudinal current density applied from surface layer to bottom along the silicon substrate is followed successively by 5mA/cm2、10mA/cm2、 45mA/cm2, the etching time from surface layer to bottom is followed successively by 300s, 900s, 1800s.It, can be with by electrochemical corrosion course Obtain three layers of cellular structure with different porosities, different hole densities and different-thickness.
It is the uniformity for guaranteeing etching during carrying out electrochemical corrosion, needs to form each layer of porosity in corrosion Current density is kept constant during structure, and the concentration of etching liquid is kept constant and temperature control is at 20 DEG C.
(2-4) using deionized water to the silicon substrate with three layers of cellular structure elute repeatedly 10min~ 20min。
The silicon substrate through rinsing is impregnated displacement 10min~20min by (2-5) in ethyl alcohol or IPA, uses nitrogen later Gas dries up the silicon substrate.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as Protection scope of the present invention.

Claims (14)

1. a kind of preparation method at porous silicon-base bottom, which comprises the steps of:
One silicon substrate is provided;
Layering electrochemical corrosion is carried out to the silicon substrate, to form the multi-layer porous property knot of the longitudinal arrangement along the silicon substrate Structure, and the porosity of surface layer cellular structure is less than or equal to the porosity of other any layer cellular structures.
2. the preparation method at porous silicon-base bottom according to claim 1, which is characterized in that joined using the different corrosion of multiple groups It is several that layering electrochemical corrosion is carried out to the silicon substrate, so that at least two layers of cellular structure in the multi-layer porous property structure formed Porosity and/or thickness it is different.
3. the preparation method at porous silicon-base bottom according to claim 2, which is characterized in that the corrosion parameter includes electric current Density.
4. the preparation method at porous silicon-base bottom according to claim 3, which is characterized in that close using a variety of different electric currents Degree carries out layering electrochemical corrosion to the silicon substrate respectively, and the current density for being applied to surface layer is less than or equal to other layers.
5. the preparation method at porous silicon-base bottom according to claim 3, which is characterized in that the corrosion parameter further includes corruption Lose the time;Using a variety of different current densities and etching time corresponding with each current density to the silicon substrate into Row layering electrochemical corrosion.
6. the preparation method at porous silicon-base bottom according to claim 1, which is characterized in that be layered to the silicon substrate Further include following steps before electrochemical corrosion:
One layer of silicon nitride film is deposited in the surface of silicon;
The silicon nitride film is performed etching, to form patterned mask layer.
7. the preparation method at porous silicon-base bottom according to claim 1, which is characterized in that be layered to the silicon substrate The specific steps of electrochemical corrosion include:
A pair of electrodes is provided;
Etching liquid is mixed to get using the hydrofluoric acid, ethyl alcohol and deionized water of preset ratio;
The electrode and the silicon substrate are placed in the etching liquid, and layering electrochemical corrosion is carried out to the silicon substrate.
8. the preparation method at porous silicon-base bottom according to claim 7, which is characterized in that hydrofluoric acid, ethyl alcohol in etching liquid Volume ratio with deionized water is VHydrofluoric acid: VEthyl alcohol: VDeionized water=(1:1:1)~(1:1:4).
9. the preparation method at porous silicon-base bottom according to claim 1, which is characterized in that be layered to the silicon substrate Further include following steps after electrochemical corrosion:
The silicon substrate with multi-layer porous property structure is rinsed using deionized water;
The silicon substrate through rinsing is impregnated into preset time in organic solvent;
The soaking silicon substrate is dried up, using dry gas to remove remaining organic solvent in the silicon substrate.
10. a kind of porous silicon-base bottom, which is characterized in that including silicon substrate, the silicon substrate has along its longitudinally disposed multilayer Cellular structure, and the porosity of surface layer cellular structure is less than or equal to the porosity of other any layer cellular structures.
11. porous silicon-base bottom according to claim 10, which is characterized in that in multi-layer porous property structure at least two layers it is porous The porosity of property structure is different.
12. porous silicon-base bottom according to claim 11, which is characterized in that multi-layer porous property structure includes surface layer porosity Structure, middle layer cellular structure and underlying porous structure, and the porosity of middle layer cellular structure is higher than surface layer porosity The porosity of structure.
13. porous silicon-base bottom according to claim 10, which is characterized in that in multi-layer porous property structure at least two layers it is porous The thickness of property structure is different.
14. porous silicon-base bottom according to claim 13, which is characterized in that multi-layer porous property structure includes surface layer porosity Structure, middle layer cellular structure and underlying porous structure, and the thickness of middle layer cellular structure is greater than surface layer porosity knot The thickness of structure.
CN201810358053.9A 2018-04-20 2018-04-20 Preparation method of porous silicon substrate and porous silicon substrate Pending CN110386585A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331492A (en) * 2020-11-02 2021-02-05 马鞍山安慧智电子科技有限公司 Preparation method of self-supporting porous silicon/ZnO composite material

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10133048A (en) * 1996-10-30 1998-05-22 Kyocera Corp Production of optical waveguide
US6277662B1 (en) * 1999-06-03 2001-08-21 Seiichi Nagata Silicon substrate and forming method thereof
CN1620402A (en) * 2002-01-24 2005-05-25 “德默克里托斯”国家科学研究中心 Low power silicon thermal sersors and microfluidic devices based on the use of porus silicon sealed air cavity technology or microchannel technology
CN1889276A (en) * 2006-07-25 2007-01-03 天津大学 Porous silicon-base vanadium oxide thin film with excellent heat insulating performance and producing method
US20080206952A1 (en) * 2004-09-30 2008-08-28 Seiichi Nagata Silicon Substrate Processing Method
TW201110223A (en) * 2009-09-11 2011-03-16 Phoenix Silicon Int Corp Method of manufacturing cavity body with vibrating membrane on silicon wafer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10133048A (en) * 1996-10-30 1998-05-22 Kyocera Corp Production of optical waveguide
US6277662B1 (en) * 1999-06-03 2001-08-21 Seiichi Nagata Silicon substrate and forming method thereof
CN1620402A (en) * 2002-01-24 2005-05-25 “德默克里托斯”国家科学研究中心 Low power silicon thermal sersors and microfluidic devices based on the use of porus silicon sealed air cavity technology or microchannel technology
US20080206952A1 (en) * 2004-09-30 2008-08-28 Seiichi Nagata Silicon Substrate Processing Method
CN1889276A (en) * 2006-07-25 2007-01-03 天津大学 Porous silicon-base vanadium oxide thin film with excellent heat insulating performance and producing method
TW201110223A (en) * 2009-09-11 2011-03-16 Phoenix Silicon Int Corp Method of manufacturing cavity body with vibrating membrane on silicon wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331492A (en) * 2020-11-02 2021-02-05 马鞍山安慧智电子科技有限公司 Preparation method of self-supporting porous silicon/ZnO composite material

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Application publication date: 20191029