CN110377972B - Automatic integrated sequencing method and device for hardware schematic diagram - Google Patents
Automatic integrated sequencing method and device for hardware schematic diagram Download PDFInfo
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- CN110377972B CN110377972B CN201910567428.7A CN201910567428A CN110377972B CN 110377972 B CN110377972 B CN 110377972B CN 201910567428 A CN201910567428 A CN 201910567428A CN 110377972 B CN110377972 B CN 110377972B
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- 238000010586 diagram Methods 0.000 title claims abstract description 105
- 238000012163 sequencing technique Methods 0.000 title claims abstract description 22
- 238000013461 design Methods 0.000 claims abstract description 18
- 230000010354 integration Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 238000012986 modification Methods 0.000 claims description 9
- 230000004048 modification Effects 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000005457 optimization Methods 0.000 abstract description 4
- 238000011161 development Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 4
- 230000008676 import Effects 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009960 carding Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an automatic integrated sequencing method of a hardware schematic diagram, which comprises the following steps: sequentially acquiring a plurality of hardware schematic diagram modules; reading attribute information of a hardware schematic diagram module; the document name and page number variables of the circuit schematic diagram contained in each module are modified one by one. The invention solves the problem that the development of the existing circuit design project usually needs to be integrated into the stacked integrated hardware module circuit schematic diagrams one by one, and then the subsequent circuit optimization design project can be carried out after each schematic diagram is manually integrated and reordered in sequence.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to an automatic integrated sequencing method and device for a hardware schematic diagram.
Background
The invention relates to a schematic diagram automatic integrated sequencing method oriented to circuit design in the technical field of circuit design automation (EDA). With decades of electronic industry developments and evolutions, traditional manual circuit Layout (Layout) is advanced to automated circuit design Layout (EDA) software tools, and the most common current circuit design Layout software cadence is capable of providing a developer design Layout hardware schematic (CSA) and simultaneously providing a circuit schematic function integrated into other hardware modules for manual integration.
In current hardware design of electronic product projects, developers often need to call and stack integrated hardware module circuit schematics, and each time when integrating other hardware module circuit schematics into a circuit layout software tool (cadence Allegro) for local end integration, page ordering disorder or repeated conflict of the circuit schematic is caused, while in the prior art, developers are required to manually reorder each page schematic of each integrated hardware module by using EDA software tools.
Each electronic product today is produced by integrating a plurality of hardware modules, each of which comprises a plurality of pages of circuit schematic integration, and thus it is time-consuming to manually reorder each page of circuit schematic.
Disclosure of Invention
The invention aims to provide an automatic integrated sequencing method and device for a hardware schematic diagram, which solve the technical problems of easy error and time consumption in the prior art by integrating and carding the circuit schematic diagram manually.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the first aspect of the invention provides an automatic integrated sequencing method for a hardware schematic diagram, which comprises the following steps:
sequentially acquiring a plurality of hardware schematic diagram modules;
reading attribute information of a hardware schematic diagram module;
the document name and page number variables of the circuit schematic diagram contained in each module are modified one by one.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the sequentially obtaining a plurality of hardware schematic modules specifically includes:
and sequentially inputting the output hardware circuit schematic modules of the general circuit design layout tool software into the integrated unit.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the reading attribute information of the hardware schematic module specifically includes:
the integrated unit acquires the input sequence of the input hardware schematic diagram module, the circuit schematic diagram document name included in the hardware schematic diagram module and the storage path of the hardware schematic diagram module.
With reference to the first aspect, in a third possible implementation manner of the first aspect, the modifying, one by one, a circuit schematic document name and a page number variable included in each module specifically includes:
reading the order of hardware schematic modules;
reading circuit schematic diagrams contained in the module according to the storage path of the hardware schematic diagram module in sequence;
the sequentially read schematic circuit diagrams are uniformly modified with document names and page number variables.
With reference to the first aspect, in a fourth possible implementation manner of the first aspect, after the step of uniformly modifying the document name and the page number variable by using the sequentially read schematic circuit diagram, the method further includes:
and packaging and modifying the circuit schematic diagram of the document name and the page number variable, and outputting.
The second aspect of the present invention provides an automated hardware schematic integrated sequencing device, which is characterized by comprising:
the hardware schematic diagram importing module sequentially acquires a plurality of hardware schematic diagram modules;
the attribute reading module is used for reading attribute information of the hardware schematic diagram module;
and the sorting modification module modifies the document names and page number variables of the circuit schematic diagram contained in each module one by one.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the attribute reading module includes:
the input order reading unit is used for acquiring the input order of the input hardware schematic diagram module by the integration unit;
the document name reading unit is used for sequentially acquiring the document names of the circuit schematic diagrams included in the hardware schematic diagram module by the integration unit;
and the path reading unit and the integration unit sequentially acquire the storage paths of the hardware schematic diagram modules.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the ranking modification module includes:
the schematic diagram acquisition unit reads the circuit schematic diagrams contained in the module according to the storage path of the hardware schematic diagram module in sequence;
and the schematic diagram attribute modifying unit uniformly modifies the document name and the page number variable of the sequentially read circuit schematic diagrams.
The network service control device according to the second aspect of the present invention can implement the methods according to the first aspect and the respective implementation manners of the first aspect, and achieve the same effects.
The effects provided in the summary of the invention are merely effects of embodiments, not all effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
the invention solves the problem that the development of the existing circuit design project always needs to be integrated into the circuit schematic diagrams of the stacked integrated hardware modules one by one, and then a great deal of time is needed for the subsequent circuit optimization design project after manually integrating and re-ordering the schematic diagrams sequentially.
Drawings
FIG. 1 is a flow chart of a method of an embodiment of the present invention;
FIG. 2 is a flow chart of a second method of the present invention;
FIG. 3 is a flow chart of a method according to an embodiment of the invention;
FIG. 4 is a schematic view of an embodiment of the apparatus of the present invention;
FIG. 5 is a schematic diagram of an attribute reading module architecture;
fig. 6 is a schematic diagram of a ranking modification module architecture.
Detailed Description
In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below with reference to the following detailed description and the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily obscure the present invention.
Example 1
As shown in fig. 1, an automated hardware schematic integrated ordering method includes the following steps:
s1, sequentially acquiring a plurality of hardware schematic modules.
S2, reading attribute information of the hardware schematic diagram module.
S3, modifying the document name and the page number variable of the circuit schematic diagram contained in each module one by one.
Example two
As shown in fig. 2, the hardware schematic diagram automatic integrated ordering method comprises the following steps:
s1, sequentially inputting the hardware circuit schematic diagram modules output by the general circuit design layout tool software into the integrated unit.
S2, the integrated unit acquires the input sequence of the input hardware schematic diagram module, the circuit schematic diagram document name included in the hardware schematic diagram module and the storage path of the hardware schematic diagram module.
S3, reading the order of the hardware schematic modules;
s4, reading a circuit schematic diagram contained in the module according to a storage path of the hardware schematic diagram module in sequence;
s5, uniformly modifying the document name and the page number variable according to the sequentially read circuit schematic diagrams.
S6, packaging and modifying the circuit schematic diagram of the document name and the page number variable, and outputting the circuit schematic diagram.
Example III
As shown in fig. 3, first, the most general circuit design layout tool software (cadence allegro) is used to output the schematic circuit diagram (CSA), and the operator sequentially imports the schematic circuit diagram (CSA) of the hardware module to be integrated (e.g., leading into the CPU module and then importation into the DIMM module) to the automated integrated sequencing schematic software.
And then, the automatic integrated sequencing schematic diagram software realized by Java or other high-level cross-platform sentences is respectively imported into more than two hardware modules to carry out local end integration and re-sequencing, the execution software carries out automatic integrated sequencing, and a software program automatically acquires information such as the sequence of the import module, the file names of the circuit schematic diagram, the storage path and the like.
And (3) modifying the document names and PAGE NUMBER variables (Page_NUMBER) of all the circuit schematic diagrams in each module one by one according to the hardware module import sequence, so that the automatic integrated sequencing result of the circuit schematic diagrams of the plurality of hardware modules can be output.
An operator can import the integrated and ordered project schematic into circuit design layout tool software (cadence allegro) for subsequent optimization of circuit design engineering.
The invention achieves the requirement by constructing the automatic integrated sequencing software of the circuit schematic diagrams, so that hardware developers can firstly respectively gather a plurality of hardware module schematic diagrams into the automatic software, then read and analyze the circuit schematic diagrams (CSA) through the automatic software program and refresh page numbers for re-sequencing, and the output result can re-sequence the circuit schematic diagrams of a plurality of hardware modules into the circuit schematic diagram integration of a required project, and the circuit Layout (Layout) and the hardware developers can easily lead in the circuit schematic diagram integration of the project to carry out subsequent circuit detail design and optimization engineering, thereby greatly improving the manual re-sequencing, the management and the stacking time required by the integration of a plurality of hardware modules.
As shown in fig. 4, a hardware schematic automation integrated sequencing device includes:
the hardware schematic diagram importing module 11 sequentially acquires a plurality of hardware schematic diagram modules;
an attribute reading module 12 for reading attribute information of the hardware schematic module;
the sorting and modifying module 13 modifies the document name and the page number variable of the schematic circuit diagram contained in each module one by one.
As shown in fig. 5, the attribute reading module includes:
an input order reading unit 121, the integration unit acquiring an input order of the input hardware schematic block;
the document name reading unit 122, the integration unit sequentially obtains the document names of the circuit schematic diagram included in the hardware schematic diagram module;
and the path reading unit 123, wherein the integrated unit sequentially acquires the storage paths of the hardware schematic modules.
As shown in fig. 6, the order modification module includes:
the schematic diagram obtaining unit 131 reads the circuit schematic diagrams included in the module according to the storage path of the hardware schematic diagram module in order;
the schematic attribute modification unit 132 uniformly modifies the sequentially read schematic circuit diagrams by document name and page number variables.
While the foregoing description of the embodiments of the present invention has been presented in conjunction with the drawings, it should be understood that it is not intended to limit the scope of the invention, but rather, it is intended to cover all modifications or variations within the scope of the invention as defined by the claims of the present invention.
Claims (4)
1. The automatic integrated sequencing method for the hardware schematic diagram is characterized by comprising the following steps of:
sequentially acquiring a plurality of hardware schematic diagram modules;
reading attribute information of a hardware schematic diagram module;
the document names and page number variables of the circuit schematic diagrams contained in each module are modified one by one according to the importing sequence of the hardware schematic diagram modules, and then the automatic integrated sequencing results of the circuit schematic diagrams of the plurality of hardware modules can be output;
the method comprises the steps of modifying the document name and the page number variable of the circuit schematic diagram contained in each module one by one according to the importing sequence of the hardware schematic diagram modules, and specifically comprises the following steps:
reading the input sequence of a hardware schematic diagram module;
reading circuit schematic diagrams contained in the module according to the storage path of the hardware schematic diagram module in sequence;
uniformly modifying the document name and page number variable of the sequentially read circuit schematic diagram;
the reading of the hardware schematic module attribute information specifically includes:
the integrated unit acquires the input sequence of the input hardware schematic diagram module, the circuit schematic diagram document name included in the hardware schematic diagram module and the storage path of the hardware schematic diagram module.
2. The method for automatically integrating and sequencing hardware schematic according to claim 1, wherein the sequentially acquiring a plurality of hardware schematic modules specifically comprises:
and sequentially inputting the output hardware circuit schematic modules of the general circuit design layout tool software into the integrated unit.
3. The automated integrated ordering method of hardware schematics according to claim 1, wherein after the step of uniformly modifying the document names and the page number variables by the sequentially read circuit schematics, the method further comprises:
and packaging and modifying the circuit schematic diagram of the document name and the page number variable, and outputting.
4. An automated integrated sequencing device for a hardware schematic, comprising:
the hardware schematic diagram importing module sequentially acquires a plurality of hardware schematic diagram modules;
the attribute reading module is used for reading attribute information of the hardware schematic diagram module;
the sequencing modification module modifies the circuit schematic document names and page number variables contained in each module one by one according to the hardware schematic module importing sequence, so that a plurality of hardware module circuit schematic automation integration sequencing results can be output;
the order modification module comprises:
the schematic diagram acquisition unit reads a circuit schematic diagram contained in the module according to a storage path of the hardware schematic diagram module according to the importing sequence of the hardware schematic diagram module;
the schematic diagram attribute modification unit uniformly modifies the document name and the page number variable of the sequentially read circuit schematic diagrams;
the attribute reading module includes:
the input order reading unit is used for acquiring the input order of the input hardware schematic diagram module by the integration unit;
the document name reading unit is used for sequentially acquiring the document names of the circuit schematic diagrams included in the hardware schematic diagram module by the integration unit;
and the path reading unit and the integration unit sequentially acquire the storage paths of the hardware schematic diagram modules.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106535483A (en) * | 2016-12-29 | 2017-03-22 | 广州兴森快捷电路科技有限公司 | PCB plug hole aluminum sheet making automatic scheduling system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106535483A (en) * | 2016-12-29 | 2017-03-22 | 广州兴森快捷电路科技有限公司 | PCB plug hole aluminum sheet making automatic scheduling system and method |
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