CN110377296B - System and method for supporting Flash burning of server main control board - Google Patents
System and method for supporting Flash burning of server main control board Download PDFInfo
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- CN110377296B CN110377296B CN201910568554.4A CN201910568554A CN110377296B CN 110377296 B CN110377296 B CN 110377296B CN 201910568554 A CN201910568554 A CN 201910568554A CN 110377296 B CN110377296 B CN 110377296B
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- 238000012360 testing method Methods 0.000 claims abstract description 17
- 238000013461 design Methods 0.000 description 8
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Abstract
A system and a method for supporting Flash burning of a server main control board are provided, the system comprises a mainboard supporting 2 paths of central processing units, the mainboard is provided with a central processing unit, an integrated south bridge, a substrate management controller, a complex programmable logic device, a central processing unit Flash memory and a substrate management controller Flash memory, the substrate management controller and the integrated south bridge are electrically connected with the complex programmable logic device, the complex programmable logic device is connected with the central processing unit Flash memory and the substrate management controller Flash memory through the same bus, and the complex programmable logic device realizes the read-write operation of the central processing unit Flash memory or the substrate management controller Flash memory through the state selection of a chip selection bus. The invention removes the chip holder for installing the flash memory in the traditional server, and when the flash memory needs to be burned, the main control board only needs to be connected to the upper computer through the joint test workgroup link for operation, thereby fundamentally solving the problems caused by using the chip holder.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a system and a method for supporting Flash burning of a server main control board.
Background
At present, a main control board of a universal server is provided with two Flash memory Flash chips, one of which is used for storing a BIOS, and the other is used for storing a baseboard management controller BMC operating system, and the two chips are usually installed on a chip Socket in a board design and verification stage, and are detached for burning when the BIOS and the baseboard management controller BMC operating system are updated.
Referring to fig. 1 in the hardware connection, the Flash memory Flash chip is attached to the lower side of the main control chip, the main control chip may be a BMC or an integrated south bridge PCH, and the Flash memory Flash chip must be a device of an SPI interface.
The existing hardware connection mode has the advantage that when the fault debug is eliminated in the product design verification stage, the flash memory chip is convenient to disassemble so as to burn the BIOS and the BMC operating system. However, the following problems still remain unsolved:
1. in the product verification stage, firstly, a Socket is attached to a main control board, and then a flash memory chip is fixed in the Socket; when the product is manufactured in a mass production way, socket needs to be removed, and the flash memory chip is pasted on the mainboard; the process is complicated, and the problem of Socket omission removal is easy to occur;
2. in the product design verification stage, a Socket support is required to fix the Flash chip, so that the risk of failure that the Flash chip is fixed unstably and cannot be started is easy to occur, and the research and development time cost is increased;
3. from the aspect of flash memory device type selection, only a flash memory with an SPI interface can be selected;
4. in the system starting stage, the integrated south bridge PCH reads the BIOS through the SPI bus and loads the BIOS into the memory to operate, and the hardware environment is initialized, and the bandwidth of the SPI bus is low, so that the reading and writing performance of the PCH on the flash memory is limited, and the system starting time is prolonged.
5. In the product verification stage, if the BIOS and the BMC operating system are updated iteratively frequently, burning operation needs to be performed on the flash memory frequently, so that the Socket support can be plugged and pulled to a certain extent, a risk of damage to the Socket due to improper operation is also likely to occur, and material and time costs are increased.
Disclosure of Invention
The invention provides a system and a method for supporting Flash burning of a server main control board, which are used for solving the problem that a Flash chip of a Flash memory of the existing server main control board is troublesome.
The invention is realized by the following technical scheme:
a system for supporting Flash burning of a main control board of a server comprises a mainboard supporting 2 paths of central processing units, wherein the mainboard is provided with a central processing unit, an integrated south bridge, a substrate management controller, a complex programmable logic device, a central processing unit Flash memory and a substrate management controller Flash memory, the substrate management controller and the integrated south bridge are electrically connected with the complex programmable logic device, the complex programmable logic device is connected with the central processing unit Flash memory and the substrate management controller Flash memory through the same bus, and the complex programmable logic device realizes the read-write operation of the central processing unit Flash memory or the substrate management controller Flash memory through the state selection of a chip selection bus.
According to the system for supporting Flash burning of the server main control board, the complex programmable logic device is connected with the system joint test workgroup link and the jumper, and when the complex programmable logic device is informed of burning actions of the substrate management controller Flash memory chip or the central processing unit Flash memory chip through state selection of the jumper, a burning mode is performed on the substrate management controller on line or manually through the joint test workgroup link.
According to the system for supporting Flash burning of the server main control board, the complex programmable logic device is electrically connected with the substrate management controller, the integrated south bridge, the central processing unit Flash memory and the substrate management controller Flash memory by the SPI bus or the I0 bus.
In the system for supporting Flash burning of the server main control board, the Flash memory of the central processing unit and the Flash memory of the substrate management controller are SPI interfaces or I0 interfaces Flash.
The invention also provides a method for supporting Flash burning of the server main control board, which comprises the system, and the method comprises the following steps:
s1, interconnecting devices to construct the system;
s2, electrifying the system to start;
and S3, the complex programmable logic device realizes the read-write operation of the central processing unit flash memory or the substrate management controller flash memory through the state selection of the chip selection bus.
According to the method for supporting Flash burning of the server main control board, the complex programmable logic device is connected with the system joint test workgroup link and the jumper, and when the complex programmable logic device is informed of burning actions of the substrate management controller Flash memory chip or the central processing unit Flash memory chip through state selection of the jumper, a burning mode is carried out on-line burning of the substrate management controller or manually through the joint test workgroup link.
According to the method for supporting Flash burning of the server main control board, the Flash memory of the central processing unit and the Flash memory of the substrate management controller are SPI interfaces or I0 interfaces Flash.
Compared with the prior art, the invention has the advantages that:
1. the server main board removes sockets of BMCFlash and CPUFlash installed in the traditional server, the flash memory chip mounting process does not need to be changed in the design verification stage and the mass production stage, and when a design verification worker needs to burn the flash memory, the main control board is connected to the upper computer through the joint test workgroup link for operation, so that the problems in the process, design, verification and mass production caused by the use of the Socket in the prior art are solved fundamentally.
2. The flash memory device is more flexible in type selection, and an SPI (serial peripheral interface) or a high-bit-width and high-speed IO (input/output) interface type can be selected, so that adaptation can be more flexibly carried out according to actual needs, and the performance of a server system is improved.
3. The invention has strong practicability and low cost, firstly interconnects the devices, and then burns BMCFlash and CPUFlash through a complex programmable logic device CPLD or distinguishes BMCFlash and CPUFlash through SJTAG burning and selects BMCFlash and CPUFlash by the CPLD.
4. The invention has great practical value for the design, production and use of the flash memory of the universal server main control board system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a schematic diagram of a Flash system of a conventional main control board;
FIG. 2 is a schematic diagram of the system of the present invention;
FIG. 3 is a flow chart of the method of the present invention;
reference numerals: 1-main control chip, 2-flash memory, 3-chip holder, 4-SPI bus, 5-complex programmable logic device, 6-central processor flash memory, 7-baseboard management controller flash memory, 8-baseboard management controller, 9-integrated south bridge, 10-memory, 11-jumper, 12-joint test workgroup link and 13-chip selection bus.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
As shown in fig. 1, a main control board of an existing universal server is provided with two flash memories 2, one flash memory 2 is used for storing a BIOS program, and the other flash memory 2 is used for storing an operating system of a BMC (baseboard management controller), and usually, the two flash memories 2 are installed on a chip socket 3 at a stage of board design and verification, and are detached for burning when the BIOS and the operating system of the BMC are updated. The main control chip 1 can be a baseboard management controller BMC or an integrated south bridge PCH, a Flash memory Flash chip is hung below the main control chip, and the Flash memory Flash chip must be a device of an SPI interface and carries out data transmission through an SPI bus 4.
As shown in fig. 2-fig. 3, this embodiment discloses a system for supporting Flash burning of a server main control board, the system includes a main board supporting 2 paths of central processing units, the main board is provided with a central processing unit, an integrated south bridge 9, a substrate management controller 8, a complex programmable logic device 5, a central processing unit Flash memory 6, and a substrate management controller Flash memory 7, wherein the substrate management controller 8 and the integrated south bridge 9 are respectively connected to a memory 10
The substrate management controller 8 and the integrated south bridge 9 are electrically connected with the complex programmable logic device 5, the complex programmable logic device 5 is connected with the central processor flash memory 6 and the substrate management controller flash memory 7 through the same bus, and the complex programmable logic device 5 realizes the read-write operation of the central processor flash memory 6 or the substrate management controller flash memory 7 through the state selection of the chip selection bus 13.
Specifically, in this embodiment, the BMC, the Flash memory Flash, and the integrated south bridge PCH interface interconnected with the CPLD may be a high speed IO interface, an SPI interface, or other interfaces, which is specifically determined according to a system design scheme; the chip selection bus CS <0 > is used for selecting chips of BMCFlash and CPUFlash by a complex programmable logic device CPLD and selecting which Flash is subjected to burning action.
Meanwhile, the complex programmable logic device CPLD coding realizes the distinction of BMC burning and the burning through the joint test workgroup link 12 and the chip selection of the CPLD on the BMCFlash and the CPUFlash; the link 12 of the joint test workgroup mainly plays a role in performing version burning on the BMCFlash and the CPUFlash, the BMC Flash stores a BMC operating system, the CPUFlash stores a BIOS of the CPU, and the jumper 11 informs the CPLD that when the BMCFlash and the CPUFlash are currently burned, the BMC is burned online or is manually burned through the link 12 of the joint test workgroup.
The system is simple to realize and low in cost, the devices are interconnected through hardware connection, and FW burning and SJTAG burning are distinguished through the CPLD device, and BMCFlash and CPUFlash are selected by the CPLD; meanwhile, the architecture can avoid numerous problems brought by the traditional Socket, and can also enable system developers to flexibly select the Flash of various interfaces according to system requirements, thereby improving the system performance; the method provided by the invention has great application value for the Flash storage architecture design of the universal server;
in this embodiment, the complex programmable logic device 5, the baseboard management controller 8, the integrated south bridge 9, the cpu flash memory 5, and the baseboard management controller flash memory 6 are electrically connected by an SPI bus or an I0 bus. Further, the central processing unit Flash memory and the substrate management controller Flash memory are SPI interfaces or I0 interfaces Flash.
The invention also provides a method for supporting Flash burning of the server main control board, which comprises the system, and the method comprises the following steps:
s1, interconnecting devices to construct the system;
s2, electrifying the system to start;
and S3, the complex programmable logic device realizes the read-write operation of the flash memory of the central processing unit or the flash memory of the substrate management controller through the state selection of the chip selection bus.
Specifically, in this embodiment, the BMC, the Flash memory Flash, and the integrated south bridge PCH interface interconnected with the CPLD may be high-speed IO interfaces, SPI interfaces, or other interfaces, which is determined specifically according to a system design scheme; the chip selection bus CS <0 >.
Meanwhile, the complex programmable logic device CPLD codes realize the distinction of BMC burning and the burning through the joint test workgroup link 12 and the chip selection of the CPLD on the BMCFlash and the CPUFlash; the joint test workgroup link 12 mainly functions to perform version burning on the BMCFlash and the CPUFlash, the BMC Flash stores the BMC operating system, the CPUFlash stores the BIOS of the CPU, and the jumper 11 informs the CPLD that when the BMCFlash and the CPUFlash are currently burned, the BMC is burned online or manually through the joint test workgroup link 12.
The system is simple to realize and low in cost, the devices are interconnected through hardware connection, and FW burning and SJTAG burning are distinguished through the CPLD device, and BMCFlash and CPUFlash are selected by the CPLD; meanwhile, the architecture can avoid numerous problems brought by the traditional Socket, and can also enable system developers to flexibly select the Flash of various interfaces according to system requirements, thereby improving the system performance; the method provided by the invention has great application value for the Flash storage architecture design of the universal server;
the technical contents not described in detail in the present invention are all known techniques.
Claims (6)
1. A system for supporting Flash burning of a server main control board is characterized by comprising a mainboard supporting a 2-path central processing unit, wherein the mainboard is provided with a central processing unit, an integrated south bridge, a substrate management controller, a complex programmable logic device, a central processing unit Flash memory and a substrate management controller Flash memory;
the complex programmable logic device is connected with a system joint test workgroup link and a jumper, and when the state selection of the jumper informs the complex programmable logic device to perform burning action on the substrate management controller flash memory chip or the central processor flash memory chip, the substrate management controller is subjected to online burning or manual burning through the joint test workgroup link.
2. The system for supporting Flash burning of the server main control board according to claim 1, wherein the complex programmable logic device is electrically connected with the baseboard management controller, the integrated south bridge, the central processor Flash memory and the baseboard management controller Flash memory by an SPI bus or an I0 bus.
3. The system for supporting Flash burning of the main control board of the server according to claim 1, wherein the Flash memory of the central processing unit and the Flash memory of the baseboard management controller are SPI interfaces or I0 interfaces Flash.
4. A method for supporting Flash burning of a server main control board, comprising the system of any one of claims 1 to 3, wherein the method comprises the following steps:
s1, interconnecting devices to construct the system;
s2, electrifying the system to start;
and S3, the complex programmable logic device realizes the read-write operation of the central processing unit flash memory or the substrate management controller flash memory through the state selection of the chip selection bus.
5. The method for supporting Flash burning of the server main control board according to claim 4, wherein a system joint test workgroup link and a jumper are connected to the complex programmable logic device, and when the status of the jumper is selected to inform the complex programmable logic device to perform burning operation on the baseboard management controller Flash memory chip or the CPU Flash memory chip, the method is used for online burning of the baseboard management controller or manually performing burning through the joint test workgroup link.
6. The method for supporting Flash burning of the server main control board according to claim 4, wherein the central processing unit Flash memory and the baseboard management controller Flash memory are SPI interfaces or I0 interfaces Flash.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110825454B (en) * | 2019-10-30 | 2021-07-16 | 苏州浪潮智能科技有限公司 | JTAG link device of server mainboard and design method |
| CN111045866B (en) * | 2019-12-06 | 2023-06-16 | 锐捷网络股份有限公司 | BMC fault processing method and device, electronic equipment and storage medium |
| CN111158710B (en) * | 2019-12-30 | 2023-08-25 | 杭州迪普科技股份有限公司 | Program programming method, device and network equipment |
| CN111625266A (en) * | 2020-05-28 | 2020-09-04 | 北京天海微电子信息技术有限公司 | Firmware burning device |
| CN116466968B (en) * | 2023-05-25 | 2023-11-24 | 合芯科技(苏州)有限公司 | Access method and device of main board flash memory and firmware burning method and device |
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