CN110365334A - A kind of design method improving the answering machine coherent transponding signal phase precision that tests the speed - Google Patents

A kind of design method improving the answering machine coherent transponding signal phase precision that tests the speed Download PDF

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Publication number
CN110365334A
CN110365334A CN201910635943.4A CN201910635943A CN110365334A CN 110365334 A CN110365334 A CN 110365334A CN 201910635943 A CN201910635943 A CN 201910635943A CN 110365334 A CN110365334 A CN 110365334A
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answering machine
bit wide
phase
error
speed
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CN110365334B (en
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叶雷
李忞詝
杨振
梁琴琴
崔颖升
马金鑫
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Shanghai Aerospace Measurement Control Communication Institute
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Shanghai Aerospace Measurement Control Communication Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/105—Resetting the controlled oscillator when its frequency is outside a predetermined limit

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The invention discloses a kind of design methods for improving the answering machine coherent transponding signal phase precision that tests the speed, one kind is intended to provide in answering machine digital processing part of testing the speed, the key variables bit wide range of choice for influencing phase error is obtained by calculation, realize not wasting) 3* computing resource utilization rate in the case where reduce phase error, so that forward signal phase accuracy is limited solely by the external hardwares such as frequency source stability and refer to calibration method.The technical scheme is that: the relationship between quantization error calculated according to forward signal phase error and Digital Coherent forwarding obtains the key variables for influencing phase error；The bit wide range of choice of key variables is calculated in conjunction with the external hardwares index such as answering machine technical requirements and frequency source stability that tests the speed, it is chosen by bit wide, utmostly reduce) phase error that the digital circuits such as 3* $ introduce, improves forward signal phase accuracy.The present invention has engineering practicability, can significantly reduce phase error, improves the precision for the answering machine forward signal that tests the speed.

Description

A kind of design method improving the answering machine coherent transponding signal phase precision that tests the speed
Technical field
The present invention relates to space telemetry and control technology fields, in particular to a kind of to improve the answering machine coherent transponding signal phase that tests the speed The design method of precision.
Background technique
Coherent transponding system is applied to Aerospace Tracking & Control more, and generally requiring makes in the aerospace crafts such as satellite, rocket With answering machine, tie surface radar either satellite-signal realizes coherent transponding, completes TT&C task, such as C-band continuous wave Answering machine, S-band TT&C Transponder, detector Ka S-Band Transponder S etc..With the development of digital technology, response is digitized Machine gradually becomes answering machine mainstream, by realizing the forwarding of coherent frequency using Digital Coherent forward mode in conjunction with FPGA.Cause This, reduces forward signal phase error, improve measurement accuracy and reliability be answering machine improve performance indicator major demands it One.
Currently, there are two the factor for influencing coherent transponding signal phase precision is main:
One is answering machine hardware performance, and such as the phase error that component performance introduces, predominantly frequency source stability refers to Mark influences forward signal phase error bring, which is limited to component performance, cannot be carried out by the method for design Inhibit；
Another is in software digital treatment process, to the frequency error that the digital quantization of frequency introduces, the error Certain constraint can be obtained by program optimization.
The design is analyzed for second influence factor, and the angle optimized from programmed algorithm improves forward signal phase Precision, balancing software resources occupation rate, phase error and component performance introduce the relationship between error, this method practicability It is relatively strong, forwarding precision can be significantly improved by the optimization of digital processing, promoted and applied in the answering machine that tests the speed.
" improvement method of answering machine range accuracy " (patent No. CN105548995 A, inventor Li Zhaofei, Chen Xia) is proposed The improvement method of answering machine range accuracy.This method realizes clock compensation function by programming in fpga chip, uses Modulating clock of the FPGA system clock as downlink generates signaling clock by DDS, and generates edge after downlink synchronization Pulse, is used for synchronized sampling uplink signal, and this method combination digital algorithm passes through the synchronous ranging for improving answering machine of clock Precision.But this method is analyzed mainly for range accuracy, does not propose to combine hardware component performance evaluation digital processing Part, the improvement method for the answering machine coherent transponding signal phase precision that is also not directed to test the speed.
Summary of the invention
In order to overcome the shortcomings in the prior art, the present invention provides a kind of raising and tests the speed answering machine coherent transponding signal phase The design method of precision can reduce the systematic error and random error of coherent transponding signal, improve forwarding precision.
In order to achieve the above object of the invention, it is as follows to solve technical solution used by its technical problem:
A kind of design method improving the answering machine coherent transponding signal phase precision that tests the speed, comprising the following steps:
Step 1: according to the relationship between quantization error and forward signal phase error, obtaining the key for influencing phase error The bit wide range of choice lower limit of key variables is calculated in conjunction with the answering machine technical requirements that test the speed in variable；
Step 2: in conjunction with the corresponding calculating key variables bit wide range of choice upper limit of Stability index of frequency source component；
Step 3: suitable variable bit wide can be got according to calculated upper and lower limits, realization makes in not waste of resource It is limited to the hardware index of crystal oscillator external component with the answering machine phase error that makes to test the speed under conditions of rate, reduces phase Error influence factor.
Further, in step 1, after each parameter quantization in FPGA, intermediate frequency forward signal is exported
In formula, ρ is the intermediate-freuqncy signal forwarding ratio after quantization, fclkFor local oscillator clock frequency, KPLLTo be received after semaphore lock Phase-lock-ring output frequency control word, n are the cut position digit that gain control generates, bDDSBit wide is exported for DDS；
Ideally, the quantized value that signal processing operation should be each parameter is managed plus the corresponding error component cast out The intermediate frequency forward signal thought is
In formula, KITThe frequency control word of output signal, ε are forwarded for intermediate frequencyDDSQuantify to introduce error for output frequency；
Meanwhile the signal frequency control word obtained after semaphore lock is KIT=(ρ+ερ)·(KPLL+εPLL)/2n,
In formula, ερTo forward ratio error, εPLLThe error introduced for the quantization of digital phase-locked loop intermediate ring road oscillator digital；
Remember εFPGA=fIT0-fITThe phase error generated is calculated for FPGA, is had
Wherein, bPLLTo receive phase-lock-ring output frequency control word bit wide, b after semaphore lockDDSBit wide, b are exported for DDSρ To forward ratio bit wide, fclkAnswering machine forwarding is influenced in the case where local oscillator clock frequency is fixed for local oscillator clock frequency The key variables of signal phase error are bPLL、bDDS、bρ, by improving key variables digital quantization digit, given up after reducing quantization Frequency error caused by the fractional part of abandoning.
Further, in step 1, further combined with the technical requirement of answering machine forward signal phase accuracy, meter Calculate the key variables b that phase accuracy is influenced in FPGAPLL、bDDS、bρBit wide value, i.e. range of choice lower limit.
Further, in step 2, according to the Stability index of frequency source component, the phase error of introducing is calculated εcomp, when answering machine forward signal phase accuracy takes (1/3) εcompWhen, in conjunction with key variables quantization bit wide and phase in FPGA The relational expression of error calculates phase accuracy and is limited solely by corresponding key variables bit wide value when frequency source stability.
Further, in step 3:
When the key variables bit wide in digital processing selects more than the variable bit wide being calculated according to technical requirement When minimum value, answering machine forward signal phase accuracy index can be met, continue to optimize and then improve forwarding phase accuracy；
When key variables bit wide is more than the variable bit wide value being calculated according to frequency source component Stability index, The phase accuracy of numerical calculation part, answering machine forward signal can increase, and start to be limited to frequency source stability to refer to Mark.
The present invention due to using the technology described above, is allowed to compared with prior art, have the following advantages that and actively imitate Fruit:
1, the present invention is obtained by analyzing the test the speed software section of answering machine coherent transponding signal phase precision of influence To the key variables of answering machine forward signal phase accuracy of testing the speed are influenced, in conjunction with answering machine technical requirement and component Energy index calculates key variables, obtains the range of choice of digital quantization Partial key variable bit wide, improves forward signal Phase accuracy.
2, the present invention provides a kind of variable bit wide choosing method based on digital processing, can reduce answering machine forward signal Phase error chooses the calculating variable of reasonable bit wide, is analyzed in conjunction with frequency source component performance for stability index, realizes Do not waste) make under conditions of 3* $ resource utilization the systematic error of forward signal and random error be limited solely by frequency source to stablize The external hardwares indexs such as degree have engineering practicability, can significantly reduce phase error, improve the essence for the answering machine forward signal that tests the speed Degree.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment Attached drawing be briefly described.It is clear that drawings in the following description are only some embodiments of the invention, for ability For field technique personnel, without creative efforts, it is also possible to obtain other drawings based on these drawings.It is attached In figure:
Fig. 1, which is that the present invention is a kind of, improves the number described in the design method of answering machine coherent transponding signal phase precision that tests the speed Word coherent transponding flow diagram；
Fig. 2 is a kind of process signal of design method for improving the answering machine coherent transponding signal phase precision that tests the speed of the present invention Figure.
Specific embodiment
Below with reference to attached drawing of the invention, the technical scheme in the embodiment of the invention is clearly and completely described And discussion, it is clear that as described herein is only a part of example of the invention, is not whole examples, based on the present invention In embodiment, those of ordinary skill in the art's every other implementation obtained without making creative work Example, belongs to protection scope of the present invention.
It refering to fig. 1, is Digital Coherent forwarding process block diagram described in the invention.According to the present invention, after down coversion Received IF signal phase is carried out by the all-digital phase-locked loop that is made of digital phase discriminator, loop filter, digital controlled oscillator Position tracks, and after PGC demodulation, the loop filter output frequency control word equal with signal frequency is received passes through intermediate-freuqncy signal and turn Hair carries out the signal frequency control word that forwarding is calculated than ρ to frequency control word, and numerical control vibration is input to after controlling by gain It swings generation intermediate frequency forward signal in device to be exported, the clock f that whole flow process is provided in crystal oscillatorclkLower progress.
As shown in Fig. 2, the invention discloses a kind of design sides for improving the answering machine coherent transponding signal phase precision that tests the speed Method, comprising the following steps:
Step 1: according to the relationship between quantization error and forward signal phase error, obtaining the key for influencing phase error The bit wide range of choice lower limit of key variables is calculated in conjunction with the answering machine technical requirements that test the speed in variable；
Step 2: in conjunction with the corresponding calculating key variables bit wide range of choice upper limit of Stability index of frequency source component；
Step 3: suitable variable bit wide can be got according to calculated upper and lower limits, realization makes in not waste of resource It is limited to the hardware index of crystal oscillator external component with the answering machine phase error that makes to test the speed under conditions of rate, reduces phase Error influence factor.
In coherent transponding calculating process, the part that digital quantization is cast out will necessarily introduce calculating phase error.It is being retouched In the method stated, the Frequency Locking of input signal, forwarding are calculated and the processing such as cut position, output pass through respective frequencies control Word is calculated.Specifically, in step 1, after each parameter quantization in FPGA, exporting intermediate frequency forward signal
In formula, ρ is the intermediate-freuqncy signal forwarding ratio after quantization, fclkFor local oscillator clock frequency, KPLLTo be received after semaphore lock Phase-lock-ring output frequency control word, n are the cut position digit that gain control generates, bDDSBit wide is exported for DDS；
Ideally, the quantized value that signal processing operation should be each parameter is managed plus the corresponding error component cast out The intermediate frequency forward signal thought is
In formula, KITThe frequency control word of output signal, ε are forwarded for intermediate frequencyDDSQuantify to introduce error for output frequency；
Meanwhile the signal frequency control word obtained after semaphore lock is KIT=(ρ+ερ)·(KPLL+εPLL)/2n,
In formula, ερTo forward ratio error, εPLLThe error introduced for the quantization of digital phase-locked loop intermediate ring road oscillator digital；
Output error can be obtained in associated ideal forward signal and practical forward signal expression formulaRemember semaphore lock Phase-lock-ring output frequency control word bit wide is b afterwardsPLL, forwarding ratio bit wide is dρ, due toThe higher order term ignored in error expression can Obtain influence error primary variables beWork as fclkAfter determination, forwarding frequency Rate error is mainly determined by loop oscillator frequency, DDS output frequency and the ratio error of forwarding.
Wherein, bPLLTo receive phase-lock-ring output frequency control word bit wide, b after semaphore lockDDSBit wide, b are exported for DDSρ To forward ratio bit wide, fclkAnswering machine forwarding is influenced in the case where local oscillator clock frequency is fixed for local oscillator clock frequency The key variables of signal phase error are bPLL、bDDS、bρ, by improving key variables digital quantization digit, given up after reducing quantization Frequency error caused by the fractional part of abandoning.
Further, in step 1, further combined with the technical requirement of answering machine forward signal phase accuracy, meter Calculate the key variables b that phase accuracy is influenced in FPGAPLL、bDDS、bρBit wide value, i.e. range of choice lower limit.
Further, in step 2, according to the Stability index of frequency source component, the phase error of introducing is calculated εcomp, when answering machine forward signal phase accuracy takes (1/3) εcompWhen, in conjunction with key variables quantization bit wide and phase in FPGA The relational expression of error calculates phase accuracy and is limited solely by corresponding key variables bit wide value when frequency source stability.
Further, in step 3:
When the key variables bit wide in digital processing selects more than the variable bit wide being calculated according to technical requirement When minimum value, answering machine forward signal phase accuracy index can be met, but can continue to optimize, improve forwarding phase accuracy；
When key variables bit wide is more than the variable bit wide value being calculated according to frequency source component Stability index, The phase accuracy of numerical calculation part, forward signal can increase, but the phase accuracy of answering machine forward signal has started It is limited to frequency source Stability index, so the phase of answering machine forward signal can't be optimized by continuing raising numerical variable bit wide Precision can consume software resource instead, improve software resource utilization rate.
Embodiment:
By taking phase error≤10 °/s product design index request as an example, it can be obtained in conjunction with error calculation formula in loop Oscillator frequency, DDS output frequency and the ratio digit of forwarding can meet design objective when taking 34bit；In conjunction with mesh Preceding crystal oscillator (frequency source) stability indicator 1 × 10-11/ 10ms, the phase error that crystal oscillator is obtained under 100MHz Clock are 0.001Hz.According to error expression it is available when phaselocked loop and forwarding than variable, export DDS bit wide be 40 when, number It is 0.00027Hz that word, which forwards the phase error of computing module, less than the 1/3 of the phase error that crystal oscillator introduces, thus it is digital in FPGA Quantify variable bit wide to can use range to be [34:40].During calculating forward signal, the frequency using bit wide for 40bit is selected Rate control word and quantization forwarding can reduce FPGA in the smallest situation of software resource occupancy at this time than generating forward signal Influence of the numerical calculation to forward signal phase accuracy makes the factor for influencing phase accuracy be limited to crystal oscillator Stability index, real The raising of the answering machine that now tests the speed coherent transponding phase accuracy.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto, In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art, It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of protection of the claims Subject to.

Claims (5)

  1. The design method of answering machine coherent transponding signal phase precision 1. a kind of raising is tested the speed, which is characterized in that including following step It is rapid:
    Step 1: according to the relationship between quantization error and forward signal phase error, obtaining, which influences the crucial of phase error, becomes Amount, in conjunction with the answering machine technical requirements that test the speed, is calculated the bit wide range of choice lower limit of key variables；
    Step 2: in conjunction with the corresponding calculating key variables bit wide range of choice upper limit of Stability index of frequency source component；
    Step 3: suitable variable bit wide can be got according to calculated upper and lower limits, realized in not waste of resource utilization rate Under conditions of the answering machine phase error that makes to test the speed be limited to the hardware index of crystal oscillator external component, reduce phase error Influence factor.
  2. The design method of answering machine coherent transponding signal phase precision 2. a kind of raising according to claim 1 is tested the speed, It is characterized in that, in step 1, after each parameter quantization in FPGA, exports intermediate frequency forward signal
    In formula, ρ is the intermediate-freuqncy signal forwarding ratio after quantization, fclkFor local oscillator clock frequency, KPLLTo receive locking phase after semaphore lock Ring output frequency control word, n are the cut position digit that gain control generates, bDDSBit wide is exported for DDS；
    Ideally, the quantized value that signal processing operation should be each parameter adds the corresponding error component cast out, i.e., preferably Intermediate frequency forward signal is
    In formula, KITThe frequency control word of output signal, ε are forwarded for intermediate frequencyDDSQuantify to introduce error for output frequency；
    Meanwhile the signal frequency control word obtained after semaphore lock is KIT=(ρ+ερ)·(KPLL+εPLL)/2n,
    In formula, ερTo forward ratio error, εPLLThe error introduced for the quantization of digital phase-locked loop intermediate ring road oscillator digital；
    Remember εFPGA=fIT0-fITThe phase error generated is calculated for FPGA, is had
    Wherein, bPLLTo receive phase-lock-ring output frequency control word bit wide, b after semaphore lockDDSBit wide, b are exported for DDSρFor forwarding Ratio bit wide, fclkAnswering machine forward signal phase is influenced in the case where local oscillator clock frequency is fixed for local oscillator clock frequency The key variables of position error are bPLL、bDDS、bρ, by improving key variables digital quantization digit, give up after reduction quantization small Frequency error caused by number part.
  3. The design method of answering machine coherent transponding signal phase precision 3. a kind of raising according to claim 2 is tested the speed, It is characterized in that, in step 1, further combined with the technical requirement of answering machine forward signal phase accuracy, calculates in FPGA Influence the key variables b of phase accuracyPLL、bDDS、bρBit wide value, i.e. range of choice lower limit.
  4. The design method of answering machine coherent transponding signal phase precision 4. a kind of raising according to claim 3 is tested the speed, It is characterized in that, in step 2, according to the Stability index of frequency source component, calculates the phase error of introducingcomp, when answering It answers machine forward signal phase accuracy and takes (1/3) εcompWhen, in conjunction with the pass of key variables quantization bit wide and phase error in FPGA It is formula, calculates phase accuracy and be limited solely by corresponding key variables bit wide value when frequency source stability.
  5. The design method of answering machine coherent transponding signal phase precision 5. a kind of raising according to claim 4 is tested the speed, It is characterized in that, in step 3:
    When the key variables bit wide in digital processing selects more than the variable bit wide minimum being calculated according to technical requirement When value, answering machine forward signal phase accuracy index can be met, continue to optimize and then improve forwarding phase accuracy；
    When key variables bit wide is more than the variable bit wide value being calculated according to frequency source component Stability index, in number The phase accuracy of calculating section, answering machine forward signal can increase, and start to be limited to frequency source Stability index.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113567912A (en) * 2021-06-30 2021-10-29 上海航天电子有限公司 High-precision beacon forwarding method applied to deep space measurement and control communication system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102025388A (en) * 2010-11-12 2011-04-20 北京航空航天大学 Emulational USB intermediate frequency responser used for satellite test and control
CN103762978A (en) * 2014-01-20 2014-04-30 东南大学 Broadband low-phase noise frequency synthesizer without frequency divider based on harmonic mixing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102025388A (en) * 2010-11-12 2011-04-20 北京航空航天大学 Emulational USB intermediate frequency responser used for satellite test and control
CN103762978A (en) * 2014-01-20 2014-04-30 东南大学 Broadband low-phase noise frequency synthesizer without frequency divider based on harmonic mixing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113567912A (en) * 2021-06-30 2021-10-29 上海航天电子有限公司 High-precision beacon forwarding method applied to deep space measurement and control communication system

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