CN110363301A - Processing method, device, storage medium and the electronic device of quantum wire - Google Patents
Processing method, device, storage medium and the electronic device of quantum wire Download PDFInfo
- Publication number
- CN110363301A CN110363301A CN201910626565.3A CN201910626565A CN110363301A CN 110363301 A CN110363301 A CN 110363301A CN 201910626565 A CN201910626565 A CN 201910626565A CN 110363301 A CN110363301 A CN 110363301A
- Authority
- CN
- China
- Prior art keywords
- quantum
- logic gates
- quantum logic
- control bit
- double
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
The invention discloses a kind of processing method of quantum wire, device, storage medium and electronic devices.Wherein, this method comprises: in the case that the operation of double Quantum logic gates in quantum wire to be converted is controlled by single Quantum logic gates, the control bit of double Quantum logic gates is stored into design variables；Double Quantum logic gates by control bit number in design variables more than or equal to 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained；Export target quantum wire, wherein include Quantum logic gates of the control bit number less than 1 in target quantum wire, and target quantum wire supports quantum chip instruction set.The present invention solves can not achieve the technical issues of converting to the dibit logic gate of quantum wire in the related technology.
Description
This application claims in the submission Patent Office of the People's Republic of China on the 02nd of August in 2018, application No. is 201810872386.3, invention names
The referred to as priority of the Chinese patent application of " processing method, device, storage medium and the electronic device of quantum wire ", whole
Content is hereby incorporated by reference in the application.
Technical field
The present invention relates to the communications fields, in particular to a kind of processing method of quantum wire, device, storage medium
And electronic device.
Background technique
The instruction set of quantum chip is the set for the quantum operation that quantum chip or quantum bit are supported.Wherein comprising amount
The set for the single quantum bit logic gate that sub- bit is supported, the set of dibit Quantum logic gates, quantum ratio on quantum chip
Special link information.
In the programming of actual quantum, the expression of Quantum logic gates is often height parameter, which means that similar
Quantum logic gates are possible to be not belonging to the instruction set that the quantum bit is supported.It may be implemented to decompose any digital ratio in the related technology
Special logic gate is to H, in the set of S, T compositions.But the scheme or other more complicated (greater than 2 amounts of dibit door can not be decomposed
Sub- bit) Quantum logic gates scheme.It can not achieve the dibit logic gate conversion to quantum wire.
For above-mentioned problem, currently no effective solution has been proposed.
Summary of the invention
The embodiment of the invention provides a kind of processing method of quantum wire, device, storage medium and electronic devices, so that
It is few to solve to can not achieve the technical issues of converting the dibit logic gate of quantum wire in the related technology.
According to an aspect of an embodiment of the present invention, a kind of processing method of quantum wire is provided, comprising: to be converted
In the case that the operation of double Quantum logic gates in quantum wire is controlled by single Quantum logic gates, by double Quantum logic gates
Control bit store into design variables；Double quantum by control bit number in the design variables more than or equal to 1 are patrolled
It collects door to be decomposed, obtains Quantum logic gates of the control bit number less than 1；Export target quantum wire, wherein the aim parameter
It include the Quantum logic gates of the control bit number less than 1 in sub-line road, and the target quantum wire supports quantum chip
Instruction set.
Optionally, before the control bit of double Quantum logic gates being stored into the design variables, the method
Further include: the Quantum logic gates in the conversion quantum wire to be converted, wherein the Quantum logic gates after conversion include double quantum
Logic gate and single Quantum logic gates.
Optionally, converting the Quantum logic gates in the quantum wire to be converted includes: the shape in the Quantum logic gates
In the case that formula is greater than the form of double Quantum logic gates, the form of the Quantum logic gates is decomposed into double quantum and is patrolled
Collect the form of door and single Quantum logic gates combination.
Optionally, double Quantum logic gates by control bit number in the design variables more than or equal to 1 are decomposed,
Obtain Quantum logic gates of the control bit number less than 1, comprising: traverse control bit number in the design variables and be greater than 1 or wait
In 1 double Quantum logic gates；Double quantum of the control bit number greater than 1 in the design variables are decomposed using preset decomposition algorithm to patrol
Door is collected, Quantum logic gates of the control bit number less than 1 are obtained.
Optionally, the Quantum logic gates include: operation matrix, control bit, transposition conjugation label.
Optionally, the quantum chip instruction set includes: the connection figure of quantum chip, in the quantum chip connection figures with
The single-bit operation that each vertex is supported；The dibit operation that each side is supported in the quantum chip connection figures.
According to another embodiment of the invention, a kind of processing unit of quantum wire is also provided, comprising: memory module,
It, will be described in the case that operation for double Quantum logic gates in quantum wire to be converted is controlled by single Quantum logic gates
The control bit of double Quantum logic gates is stored into design variables；Decomposing module is used for control bit in the design variables
Double Quantum logic gates of the number more than or equal to 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained；Export mould
Block, for exporting target quantum wire, wherein include the quantum of the control bit number less than 1 in the target quantum wire
Logic gate, and the target quantum wire supports quantum chip instruction set.
Optionally, described device further include: conversion module, for the control bit storage of double Quantum logic gates to be arrived
Before in the design variables, the Quantum logic gates in the quantum wire to be converted are converted, wherein the quantum logic after conversion
Door includes double Quantum logic gates and single Quantum logic gates.
Optionally, the conversion module includes: the first decomposition unit, is greater than institute for the form in the Quantum logic gates
In the case where the form for stating double Quantum logic gates, the form of the Quantum logic gates is decomposed into double Quantum logic gates and institute
State the form of single Quantum logic gates combination.
Optionally, the decomposing module includes: Traversal Unit, is greater than for traversing control bit number in the design variables
1 or double Quantum logic gates equal to 1；Second decomposition unit, for being decomposed in the design variables using preset decomposition algorithm
Control bit number is greater than 1 double Quantum logic gates, obtains Quantum logic gates of the control bit number less than 1.
According to another embodiment of the invention, a kind of storage medium is also provided, calculating is stored in the storage medium
Machine program, wherein the computer program is arranged to execute method among the above when operation.
According to another embodiment of the invention, a kind of electronic device, including memory and processor are also provided, it is described to deposit
Computer program is stored in reservoir, the processor is arranged to run the computer program to execute side among the above
Method.
In embodiments of the present invention, using the operation of double Quantum logic gates in quantum wire to be converted by single quantum
In the case that logic gate controls, the control bit of double Quantum logic gates is stored into design variables；It will be controlled in design variables
Double Quantum logic gates of the bit number more than or equal to 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained；It is defeated
Target quantum wire out, wherein include Quantum logic gates of the control bit number less than 1, and aim parameter in target quantum wire
Support quantum chip instruction set in sub-line road.Reach and has not supported the quantum in quantum chip instruction set to patrol for all in quantum wire
The purpose that door is converted to the Quantum logic gates supported in quantum chip instruction set is collected, is fitted to quantum wire to realize
The technical effect of arbitrary quantum chip instruction set, and then solve the dibit that can not achieve in the related technology to quantum wire
The technical issues of logic gate is converted.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is a kind of hardware block diagram of the mobile terminal of the processing method of quantum wire of the embodiment of the present invention；
Fig. 2 is the flow diagram of the processing method of the quantum wire provided according to embodiments of the present invention；
Fig. 3 is the algorithm flow chart of the present embodiment；
Fig. 4 is the structural schematic diagram of the processing unit of the quantum wire provided according to embodiments of the present invention.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work
It encloses.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to
Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product
Or other step or units that equipment is intrinsic.
According to embodiments of the present invention, a kind of embodiment of the processing method of quantum wire is provided, it should be noted that
The step of process of attached drawing illustrates can execute in a computer system such as a set of computer executable instructions, also,
It, in some cases, can be to be different from shown in sequence execution herein although logical order is shown in flow charts
The step of out or describing.
Embodiment of the method provided by the embodiment of the present invention can be in mobile terminal, terminal or similar operation
It is executed in device.For running on mobile terminals, Fig. 1 is a kind of processing method of quantum wire of the embodiment of the present invention
The hardware block diagram of mobile terminal.As shown in Figure 1, mobile terminal 10 may include that one or more (only shows one in Fig. 1
It is a) (processor 102 can include but is not limited to the processing of Micro-processor MCV or programmable logic device FPGA etc. to processor 102
Device) and memory 104 for storing data, optionally, above-mentioned mobile terminal can also include the biography for communication function
Transfer device 106 and input-output equipment 108.It will appreciated by the skilled person that structure shown in FIG. 1 is only to show
Meaning, does not cause to limit to the structure of above-mentioned mobile terminal.For example, mobile terminal 10 may also include it is more than shown in Fig. 1
Perhaps less component or with the configuration different from shown in Fig. 1.
Memory 104 can be used for storing computer program, for example, the software program and module of application software, such as this hair
The corresponding computer program of the processing method of quantum wire in bright embodiment, processor 102 are stored in memory by operation
Computer program in 104 realizes above-mentioned method thereby executing various function application and data processing.Memory 104
May include high speed random access memory, may also include nonvolatile memory, as one or more magnetic storage device, flash memory,
Or other non-volatile solid state memories.In some instances, memory 104 can further comprise relative to processor 102
Remotely located memory, these remote memories can pass through network connection to mobile terminal 10.The example packet of above-mentioned network
Include but be not limited to internet, intranet, local area network, mobile radio communication and combinations thereof.
Transmitting device 106 is used to that data to be received or sent via a network.Above-mentioned network specific example may include
The wireless network that the communication providers of mobile terminal 10 provide.In an example, transmitting device 106 includes a Network adaptation
Device (Network Interface Controller, referred to as NIC), can be connected by base station with other network equipments to
It can be communicated with internet.In an example, transmitting device 106 can for radio frequency (Radio Frequency, referred to as
RF) module is used to wirelessly be communicated with internet.
Fig. 2 is the flow diagram of the processing method of the quantum wire provided according to embodiments of the present invention, as shown in Fig. 2,
This method comprises the following steps:
Step S202, what the operation of double Quantum logic gates in quantum wire to be converted was controlled by single Quantum logic gates
In the case of, the control bit of double Quantum logic gates is stored into design variables；
Step S204, double Quantum logic gates by control bit number in design variables more than or equal to 1 are decomposed, are obtained
Quantum logic gates to control bit number less than 1；
Step S206 exports target quantum wire, wherein includes amount of the control bit number less than 1 in target quantum wire
Sub- logic gate, and target quantum wire supports quantum chip instruction set.
Through the above steps, using the operation of double Quantum logic gates in quantum wire to be converted by single quantum logic
In the case where door control, the control bit of double Quantum logic gates is stored into design variables；By control bit in design variables
Double Quantum logic gates of the number more than or equal to 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained；Export mesh
Mark quantum wire, wherein include Quantum logic gates of the control bit number less than 1, and target quantum wire in target quantum wire
Support quantum chip instruction set in road.Reach the Quantum logic gates that do not support in quantum chip instruction set all in quantum wire
Quantum wire, is fitted to arbitrarily by the purpose for being converted to the Quantum logic gates supported in quantum chip instruction set to realize
Quantum chip instruction set technical effect, and then solve the dibit logic that can not achieve in the related technology to quantum wire
The technical issues of door is converted.
It should be noted that executing subject among the above can be computer program, but not limited to this.
It in the present embodiment, include the Quantum logic gates for not supporting quantum chip instruction set in quantum wire to be converted, i.e.,
Either it is greater than the logic gate of dibit including dibit logic gate.The present embodiment takes the form of one section of computer program,
Quantum wire to be transformed and quantum chip instruction set including input, output be conversion after quantum wire (i.e. aim parameter
Sub-line road), the Quantum logic gates being arranged in order including one or more.
Optionally, the quantum wire to be transformed of input and the form of expression of target quantum wire can be a chain
Table, array, JS object numbered musical notation (JavaScript Object Notation, referred to as JSON) character string etc..In addition, quantum
Route is made of Quantum logic gates, wherein each Quantum logic gates include three information: operation matrix, control bit,
Transposition conjugation label.
Optionally, the present embodiment further includes before by the storage of the control bit of double Quantum logic gates into design variables
Convert the Quantum logic gates in quantum wire to be converted, wherein the Quantum logic gates after conversion include double Quantum logic gates and list
Quantum logic gates.In the case where the form of Quantum logic gates is greater than the form of double Quantum logic gates, by the shape of Quantum logic gates
Formula is decomposed into the form of double Quantum logic gates and single Quantum logic gates combination.For example, operation matrix assumes with most 4 × 4 shape
Formula provides, and if more than 4 × 4 matrix, to matrix as each, first carries out decomposition algorithm in advance, it is decomposed most 4 ×
4 matrix.Decomposition algorithm can be according to the known skill of " Arbitrary Matrix is segmented into 2 × 2 matrix and 4 × 4 matrix combines "
Art is configured, and since Arbitrary Matrix is segmented into 2 × 2 matrix and the combination of 4 × 4 matrix, constructs 4 × 4 matrixes, complete
Be entirely can by 2 × 2 and 4 × 4 matrix construction (it is practical be exactly controlled-not gate (Controlled Not Gate, referred to as
CNOT) door and single-bit quantum door are generic gates, and any door may be converted into the combination of these two types of doors).
Design variables in the present embodiment can be customized ControlQubitVec vector, for indicating control amount
Sub- bit vectors are also possible to other vectors.
Optionally, control bit number in design variables is more than or equal to 1 double Quantum logic gates in the following manner
Decomposed, obtain Quantum logic gates of the control bit number less than 1: control bit number is greater than 1 or waits in traversal design variables
In 1 double Quantum logic gates；Double quantum logics that control bit number in design variables is greater than 1 are decomposed using preset decomposition algorithm
Door, obtains Quantum logic gates of the control bit number less than 1.Double Quantum logic gates of the control bit number greater than 1 refer to all operations
Matrix is not the logic gate of C-U, and Quantum logic gates of the control bit number less than 1 are the Quantum logic gates and/or list quantum ratio of C-U
Te Men.The logic gate that all operation matrix are 4 × 4 is traversed, is not the logic gate of C-U by all operation matrix, is converted into C-U's
The combination of Quantum logic gates and single quantum bit door.Specifically, not being that (control unitary transformation, controls U to C-U by all operation matrix
Door, for example, CNOT be control NOT gate, CZ be control Z) logic gate, be converted into the Quantum logic gates and single quantum bit of C-U
The combination of door, wherein converting algorithm is well-known technique, does not do excessive description herein, after this step, 4 × 4 all amounts
Sub- logic gate is all C-U type operations.The logic gate of all ControlQubitVec.size () > 1 is traversed, " more bits are executed
Control door decomposition algorithm ", the quantum wire that the logic gate that logic gate replaces with ControlQubitVec.size ()≤1 is indicated
Road (being here actually exactly to be converted to the form of Universal Quantum logic gate).Then, traversal is all
ControlQubitVec.size ()==1 logic gate.Wherein: more bits control door decomposition algorithms are the prior art, can be with
Play the effect for reducing the complexity of Quantum logic gates.Control bit number is greater than 1 in decomposition design variables described in the present embodiment
Double Quantum logic gates decomposition algorithm and more bits control door decomposition algorithm thought can be according to Michael.A.Nielsen
" quantum calculation with quantum information " chapter 4 content in conjunction with computer code realize, therefore do not do excessive description herein.
Optionally, quantum chip instruction set includes: the connection figure of quantum chip, in quantum chip connection figures with each vertex
The single-bit operation supported；The dibit operation that each side is supported in quantum chip connection figures.
Quantum logic gates not only may include single-bit door in quantum wire, can also include dibit door, more bit gates.
Each Quantum logic gates can also have multiple control bits and transposition conjugation label.The quantum wire of generation is according to defeated
What the quantum chip instruction set entered was adapted to, wherein each Quantum logic gates are that the element for including is concentrated in instruction, so can
To be run on chip.
Below with reference to a preferred embodiment, the present invention is described in detail:
The main purpose of the present embodiment is all quantum logics that do not support in quantum chip instruction set by quantum wire
Door is converted to the Quantum logic gates supported in quantum chip instruction set.
Fig. 3 is the algorithm flow chart of the present embodiment, specifically includes the following steps:
S301: algorithm starts, and takes the form of one section of computer program (quantum program).
S302: the input that quantum program has is [1. 2. quantum chip instruction set of quantum wire to be transformed], it has
Output be [quantum wire (one or more Quantum logic gates being arranged in order) after conversion].
The form of expression that the quantum wire of input has can be a chained list, array, JSON character string etc..The program
Output be the same form of expression quantum wire.Quantum wire is made of Quantum logic gates, and wherein each quantum is patrolled
Collecting door includes three information: operation matrix, control bit, transposition conjugation label.
S303: operation matrix hypothesis is provided in most 4 × 4 form, if more than 4 × 4 matrix, as each
Matrix first carries out decomposition algorithm in advance, it is decomposed to most 4 × 4 matrix.Decomposition algorithm can be according to " Arbitrary Matrix can be with
Be divided into 2 × 2 matrix and 4 × 4 matrix combination " well-known technique be configured, since Arbitrary Matrix is segmented into 2 × 2
Matrix and 4 × 4 matrix combination, therefore construct 4 × 4 matrixes, being entirely can be (practical by 2 × 2 and 4 × 4 matrix construction
It is exactly CNOT gate and single-bit quantum door is generic gate, any door may be converted into the combination of these two types of doors).
S304-S305: traversing the logic gate that all operation matrix are 4 × 4, is not C-U (the control tenth of the twelve Earthly Branches by all operation matrix
Transformation controls U, such as CNOT is control NOT gate, and CZ is to control Z) logic gate, be converted into the Quantum logic gates of C-U with
The combination of single quantum bit door.After this step, 4 × 4 all Quantum logic gates are all C-U type operations.
S306-S308: to all 4 × 4 logic gate, by C-U operate in control bit be moved to
(if it does not exist, then establish a ControlQubitVec) in ControlQubitVec, by C-U operate in U (held by control
Capable matrix) matrix is as new operation matrix.After the end of the step, the operation matrix of all Quantum logic gates is all 2 × 2
's.
S309-S310: traversing the logic gate of all ControlQubitVec.size () > 1, executes " more bits control doors
Decomposition algorithm ", quantum wire (this that the logic gate that logic gate replaces with ControlQubitVec.size ()≤1 is indicated
In be actually exactly to be converted to the form of Universal Quantum logic gate).
S311: all ControlQubitVec.size ()==1 logic gate, referenced patent are traversed
201811082315.X, the applying date on 09 17th, 2018, title: the processing method and processing device of two quantum bit logic gates, it will
Logic gate and quantum instruction set execute algorithm shown in referenced patent 201811082315.X Fig. 4 as input, with each defeated
Quantum wire out replaces the single-bit door.Here the operation matrix of logic gate is 2 × 2 matrixes, and includes a control ratio
Spy, therefore generally dibit operates.The scheme that can use the patent, the dibit door being converted directly into instruction set, and
And dibit door here is expressed as 4 × 4 matrixes.After this end of the step, ControlQubitVec.size ()==it 0 must
Be it is true, it must meet quantum to refer to that operation matrix, which includes 4 × 4 and 2 × 2 form, also, 4 × 4 all operation matrix
Enable the dibit operation of collection.
S312: quantum wire is input in optimization algorithm, the expression that available one kind more optimizes.Life can be optimized
At quantum wire, reduce final quantum route in logic gate.
S313-S314: output quantum wire, algorithm terminate.
It can be seen from the above, arbitrary quantum wire can be fitted in arbitrary quantum chip instruction set by the present embodiment.
It should be noted that the executing subject of above-mentioned steps can be above-mentioned terminal shown in FIG. 1, but it is not limited to this.
The embodiment of the invention also provides a kind of processing unit of quantum wire, Fig. 4 is to provide according to embodiments of the present invention
Quantum wire processing unit structural schematic diagram, as shown in figure 4, the device includes:
Memory module 42, the operation for double Quantum logic gates in quantum wire to be converted is by single Quantum logic gates
In the case where control, the control bit of double Quantum logic gates is stored into design variables；
Decomposing module 44 is carried out for double Quantum logic gates by control bit number in design variables more than or equal to 1
It decomposes, obtains Quantum logic gates of the control bit number less than 1；
Output module 46, for exporting target quantum wire, wherein include that control bit number is less than in target quantum wire
1 Quantum logic gates, and target quantum wire supports quantum chip instruction set.
By above-mentioned apparatus, using the operation of double Quantum logic gates in quantum wire to be converted by single quantum logic
In the case where door control, the control bit of double Quantum logic gates is stored into design variables；By control bit in design variables
Double Quantum logic gates of the number more than or equal to 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained；Export mesh
Mark quantum wire, wherein include Quantum logic gates of the control bit number less than 1, and target quantum wire in target quantum wire
Support quantum chip instruction set in road.Reach the Quantum logic gates that do not support in quantum chip instruction set all in quantum wire
Quantum wire, is fitted to arbitrarily by the purpose for being converted to the Quantum logic gates supported in quantum chip instruction set to realize
Quantum chip instruction set technical effect, and then solve the dibit logic that can not achieve in the related technology to quantum wire
The technical issues of door is converted.
In an alternative embodiment, above-mentioned apparatus further includes conversion module, for by the control of double Quantum logic gates
Before bit storage is into design variables, the Quantum logic gates in quantum wire to be converted are converted, wherein the quantum after conversion is patrolled
Collecting door includes double Quantum logic gates and single Quantum logic gates.Conversion module includes: the first decomposition unit, in Quantum logic gates
Form be greater than the forms of double Quantum logic gates in the case where, the form of Quantum logic gates is decomposed into double Quantum logic gates and list
The form of Quantum logic gates combination.
In an alternative embodiment, decomposing module includes: Traversal Unit, for traversing control bit in design variables
Number is greater than 1 or double Quantum logic gates equal to 1；Second decomposition unit, for decomposing design variables using preset decomposition algorithm
Middle control bit number is greater than 1 double Quantum logic gates, obtains Quantum logic gates of the control bit number less than 1.
It in the present embodiment, include the Quantum logic gates for not supporting quantum chip instruction set in quantum wire to be converted, i.e.,
Either it is greater than the logic gate of dibit including dibit logic gate.The present embodiment takes the form of one section of computer program,
Quantum wire to be transformed and quantum chip instruction set including input, output be conversion after quantum wire (i.e. aim parameter
Sub-line road), the Quantum logic gates being arranged in order including one or more.
Optionally, the quantum wire to be transformed of input and the form of expression of target quantum wire can be a chain
Table, array, JS object numbered musical notation (JavaScript Object Notation, referred to as JSON) character string etc..In addition, quantum
Route is made of Quantum logic gates, wherein each Quantum logic gates include three information: operation matrix, control bit,
Transposition conjugation label.
Optionally, the present embodiment further includes before by the storage of the control bit of double Quantum logic gates into design variables
Convert the Quantum logic gates in quantum wire to be converted, wherein the Quantum logic gates after conversion include double Quantum logic gates and list
Quantum logic gates.In the case where the form of Quantum logic gates is greater than the form of double Quantum logic gates, by the shape of Quantum logic gates
Formula is decomposed into the form of double Quantum logic gates and single Quantum logic gates combination.For example, operation matrix assumes with most 4 × 4 shape
Formula provides, and if more than 4 × 4 matrix, to matrix as each, first carries out decomposition algorithm in advance, it is decomposed most 4 ×
4 matrix.Decomposition algorithm can be according to the known skill of " Arbitrary Matrix is segmented into 2 × 2 matrix and 4 × 4 matrix combines "
Art is configured, and since Arbitrary Matrix is segmented into 2 × 2 matrix and the combination of 4 × 4 matrix, constructs 4 × 4 matrixes, complete
Be entirely can by 2 × 2 and 4 × 4 matrix construction (practical is exactly CNOT gate and single-bit quantum door is generic gate, any door
It may be converted into the combination of these two types of doors).
Design variables in the present embodiment can be customized ControlQubitVec vector, for indicating control amount
Sub- bit vectors are also possible to other vectors.
Optionally, control bit number in design variables is more than or equal to 1 double Quantum logic gates in the following manner
Decomposed, obtain Quantum logic gates of the control bit number less than 1: control bit number is greater than 1 or waits in traversal design variables
In 1 double Quantum logic gates；Double quantum logics that control bit number in design variables is greater than 1 are decomposed using preset decomposition algorithm
Door, obtains Quantum logic gates of the control bit number less than 1.Such as: the logic gate that all operation matrix are 4 × 4 is traversed, will be owned
Operation matrix is not the logic gate of C-U, is converted into the Quantum logic gates of C-U and the combination of single quantum bit door.It walked at this
Afterwards, 4 × 4 all Quantum logic gates are all C-U type operations.Traverse all ControlQubitVec.size () > 1
Logic gate executes " more bits control door decomposition algorithm ", logic gate is replaced with ControlQubitVec.size's ()≤1
The quantum wire (being here actually exactly to be converted to the form of Universal Quantum logic gate) that logic gate indicates.Then, institute is traversed
There is ControlQubitVec.size ()==1 logic gate.
Optionally, quantum chip instruction set includes: the connection figure of quantum chip, in quantum chip connection figures with each vertex
The single-bit operation supported；The dibit operation that each side is supported in quantum chip connection figures.
Quantum logic gates not only may include single-bit door in quantum wire, can also include dibit door, more bit gates.
Each Quantum logic gates can also have multiple control bits and transposition conjugation label.The quantum wire of generation is according to defeated
What the quantum chip instruction set entered was adapted to, wherein each Quantum logic gates are that the element for including is concentrated in instruction, so can
To be run on chip.
It should be noted that above-mentioned apparatus can be located in above-mentioned terminal shown in FIG. 1, but it is not limited to this.
The embodiments of the present invention also provide a kind of storage medium, computer program is stored in the storage medium, wherein
The computer program is arranged to execute the step in any of the above-described embodiment of the method when operation.
Optionally, in the present embodiment, above-mentioned storage medium can be set to store by executing based on following steps
Calculation machine program:
The case where operation of S1, double Quantum logic gates in quantum wire to be converted are controlled by single Quantum logic gates
Under, the control bit of double Quantum logic gates is stored into design variables；
S2, double Quantum logic gates by control bit number in design variables more than or equal to 1 are decomposed, are controlled
Quantum logic gates of the bit number less than 1；
S3 exports target quantum wire, wherein includes quantum logic of the control bit number less than 1 in target quantum wire
Door, and target quantum wire supports quantum chip instruction set.
Optionally, in the present embodiment, above-mentioned storage medium can include but is not limited to: USB flash disk, read-only memory (Read-
Only Memory, referred to as ROM), it is random access memory (Random Access Memory, referred to as RAM), mobile hard
The various media that can store computer program such as disk, magnetic or disk.
The embodiments of the present invention also provide a kind of electronic device, including memory and processor, stored in the memory
There is computer program, which is arranged to run computer program to execute the step in any of the above-described embodiment of the method
Suddenly.
Optionally, above-mentioned electronic device can also include transmission device and input-output equipment, wherein the transmission device
It is connected with above-mentioned processor, which connects with above-mentioned processor.
Optionally, in the present embodiment, above-mentioned processor can be set to execute following steps by computer program:
The case where operation of S1, double Quantum logic gates in quantum wire to be converted are controlled by single Quantum logic gates
Under, the control bit of double Quantum logic gates is stored into design variables；
S2, double Quantum logic gates by control bit number in design variables more than or equal to 1 are decomposed, are controlled
Quantum logic gates of the bit number less than 1；
S3 exports target quantum wire, wherein includes quantum logic of the control bit number less than 1 in target quantum wire
Door, and target quantum wire supports quantum chip instruction set.
Optionally, the specific example in the present embodiment can be with reference to described in above-described embodiment and optional embodiment
Example, details are not described herein for the present embodiment.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
In the above embodiment of the invention, it all emphasizes particularly on different fields to the description of each embodiment, does not have in some embodiment
The part of detailed description, reference can be made to the related descriptions of other embodiments.
In several embodiments provided herein, it should be understood that disclosed technology contents can pass through others
Mode is realized.Wherein, the apparatus embodiments described above are merely exemplary, such as the division of the unit, Ke Yiwei
A kind of logical function partition, there may be another division manner in actual implementation, for example, multiple units or components can combine or
Person is desirably integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Between coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or communication link of unit or module
It connects, can be electrical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
On unit.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can for personal computer, server or network equipment etc.) execute each embodiment the method for the present invention whole or
Part steps.And storage medium above-mentioned includes: that USB flash disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
Reservoir (RAM, Random Access Memory), mobile hard disk, magnetic or disk etc. be various to can store program code
Medium.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (12)
1. a kind of processing method of quantum wire characterized by comprising
It, will be described in the case that the operation of double Quantum logic gates in quantum wire to be converted is controlled by single Quantum logic gates
The control bit of double Quantum logic gates is stored into design variables；
Double Quantum logic gates by control bit number in the design variables more than or equal to 1 are decomposed, and control ratio is obtained
Quantum logic gates of the special number less than 1；
Export target quantum wire, wherein include the quantum logic of the control bit number less than 1 in the target quantum wire
Door, and the target quantum wire supports quantum chip instruction set.
2. the method according to claim 1, wherein by the control bit storage of double Quantum logic gates to institute
Before stating in design variables, the method also includes:
Convert the Quantum logic gates in the quantum wire to be converted, wherein the Quantum logic gates after conversion include that double quantum are patrolled
Collect door and single Quantum logic gates.
3. according to the method described in claim 2, it is characterized in that, converting the Quantum logic gates in the quantum wire to be converted
Include:
In the case where the form of the Quantum logic gates is greater than the form of double Quantum logic gates, by the Quantum logic gates
Form be decomposed into the forms of double Quantum logic gates and single Quantum logic gates combination.
4. the method according to claim 1, wherein control bit number in the design variables to be greater than or wait
Double Quantum logic gates in 1 are decomposed, and Quantum logic gates of the control bit number less than 1 are obtained, comprising:
It traverses control bit number in the design variables and is greater than 1 or double Quantum logic gates equal to 1；
Double Quantum logic gates that control bit number in the design variables is greater than 1 are decomposed using preset decomposition algorithm, are controlled
Quantum logic gates of the bit number less than 1.
5. the method according to claim 1, wherein the Quantum logic gates include:
Operation matrix, control bit, transposition conjugation label.
6. the method according to claim 1, wherein the quantum chip instruction set includes:
The connection figure of quantum chip, the single-bit supported in the quantum chip connection figures with each vertex operate；The amount
The dibit operation that each side is supported in sub- chip connection figures.
7. a kind of processing unit of quantum wire characterized by comprising
Memory module, what the operation for double Quantum logic gates in quantum wire to be converted was controlled by single Quantum logic gates
In the case of, the control bit of double Quantum logic gates is stored into design variables；
Decomposing module is divided for double Quantum logic gates by control bit number in the design variables more than or equal to 1
Solution, obtains Quantum logic gates of the control bit number less than 1；
Output module, for exporting target quantum wire, wherein include control bit number in the target quantum wire less than 1
The Quantum logic gates, and the target quantum wire support quantum chip instruction set.
8. device according to claim 7, which is characterized in that described device further include:
Conversion module, for converting institute before storing the control bit of double Quantum logic gates into the design variables
State the Quantum logic gates in quantum wire to be converted, wherein the Quantum logic gates after conversion include double Quantum logic gates and single amount
Sub- logic gate.
9. device according to claim 8, which is characterized in that the conversion module includes:
First decomposition unit, for the form in the Quantum logic gates be greater than double Quantum logic gates form the case where
Under, the form of the Quantum logic gates is decomposed into the form of double Quantum logic gates and single Quantum logic gates combination.
10. device according to claim 7, which is characterized in that the decomposing module includes:
Traversal Unit is greater than 1 or double Quantum logic gates equal to 1 for traversing control bit number in the design variables；
Second decomposition unit, for decomposing double amounts that control bit number in the design variables is greater than 1 using preset decomposition algorithm
Sub- logic gate obtains Quantum logic gates of the control bit number less than 1.
11. a kind of storage medium, which is characterized in that be stored with computer program in the storage medium, wherein the computer
Program is arranged to execute method described in any one of claim 1 to 6 when operation.
12. a kind of electronic device, including memory and processor, which is characterized in that be stored with computer journey in the memory
Sequence, the processor are arranged to run the computer program to execute side described in any one of claim 1 to 6
Method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810872386.3A CN109165741A (en) | 2018-08-02 | 2018-08-02 | Processing method, device, storage medium and the electronic device of quantum wire |
| CN2018108723863 | 2018-08-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110363301A true CN110363301A (en) | 2019-10-22 |
| CN110363301B CN110363301B (en) | 2021-06-08 |
Family
ID=64898736
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810872386.3A Pending CN109165741A (en) | 2018-08-02 | 2018-08-02 | Processing method, device, storage medium and the electronic device of quantum wire |
| CN201910626565.3A Active CN110363301B (en) | 2018-08-02 | 2019-07-11 | Quantum line processing method, quantum line processing device, storage medium, and electronic device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810872386.3A Pending CN109165741A (en) | 2018-08-02 | 2018-08-02 | Processing method, device, storage medium and the electronic device of quantum wire |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN109165741A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111461334A (en) * | 2020-03-30 | 2020-07-28 | 北京百度网讯科技有限公司 | Quantum circuit processing method, device and equipment |
| CN112073126A (en) * | 2020-08-14 | 2020-12-11 | 合肥本源量子计算科技有限责任公司 | Method and device for ordering network node importance |
| CN113222155A (en) * | 2020-01-21 | 2021-08-06 | 合肥本源量子计算科技有限责任公司 | Quantum line construction method and device, electronic device and storage medium |
| CN114970872A (en) * | 2021-02-26 | 2022-08-30 | 合肥本源量子计算科技有限责任公司 | Quantum line compiling method, device, medium, and electronic device |
| CN115618955A (en) * | 2022-12-19 | 2023-01-17 | 量子科技长三角产业创新中心 | Quantum line optimization method, device, equipment and storage medium |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109754087B (en) * | 2019-01-11 | 2020-12-04 | 合肥本源量子计算科技有限责任公司 | Quantum program conversion method and device and electronic equipment |
| CN109615079B (en) * | 2019-01-30 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum bit control signal generation system |
| US11783217B2 (en) | 2019-02-21 | 2023-10-10 | IonQ, Inc. | Quantum circuit optimization |
| CN109858628B (en) * | 2019-02-28 | 2021-04-27 | 北京百度网讯科技有限公司 | Method, apparatus, device and computer readable storage medium for compiling quantum circuit |
| CN110188885B (en) * | 2019-06-28 | 2021-04-06 | 合肥本源量子计算科技有限责任公司 | Quantum calculation simulation method and device, storage medium and electronic device |
| CN110826719B (en) * | 2019-10-14 | 2022-08-16 | 合肥本源量子计算科技有限责任公司 | Quantum program processing method and device, storage medium and electronic device |
| CN111415011B (en) * | 2020-02-10 | 2022-04-26 | 北京百度网讯科技有限公司 | Quantum pulse determination method, device, equipment and readable storage medium |
| CN114511089B (en) * | 2020-10-23 | 2024-06-14 | 本源量子计算科技（合肥）股份有限公司 | Quantum connectivity spectrum connectivity optimization method, device, terminal and storage medium |
| CN112230818A (en) * | 2020-10-30 | 2021-01-15 | 合肥本源量子计算科技有限责任公司 | Method and device for editing quantum logic gate on terminal interface |
| WO2022247887A1 (en) | 2021-05-28 | 2022-12-01 | 合肥本源量子计算科技有限责任公司 | Method and apparatus for constructing quantum circuit corresponding to linear function |
| CN114970873A (en) * | 2022-06-14 | 2022-08-30 | 浪潮集团有限公司 | Method for inserting operation of three-bit gate in graphic programming in quantum computing cloud platform |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8190553B2 (en) * | 2007-12-20 | 2012-05-29 | Routt Thomas J | Methods and systems for quantum search, computation and memory |
| US20150186587A1 (en) * | 2012-07-19 | 2015-07-02 | Microsoft Technology Licensing, Llc | Method and system for optimal decomposition of single-qubit quantum circuits using standard quantum gates |
| CN107977541A (en) * | 2018-01-17 | 2018-05-01 | 合肥本源量子计算科技有限责任公司 | A kind of method for optimizing quantum wire emulation |
| CN108334952A (en) * | 2017-11-24 | 2018-07-27 | 南京航空航天大学 | A kind of novel universal quantum door and quantum wire optimization method |
-
2018
- 2018-08-02 CN CN201810872386.3A patent/CN109165741A/en active Pending
-
2019
- 2019-07-11 CN CN201910626565.3A patent/CN110363301B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8190553B2 (en) * | 2007-12-20 | 2012-05-29 | Routt Thomas J | Methods and systems for quantum search, computation and memory |
| US20150186587A1 (en) * | 2012-07-19 | 2015-07-02 | Microsoft Technology Licensing, Llc | Method and system for optimal decomposition of single-qubit quantum circuits using standard quantum gates |
| CN108334952A (en) * | 2017-11-24 | 2018-07-27 | 南京航空航天大学 | A kind of novel universal quantum door and quantum wire optimization method |
| CN107977541A (en) * | 2018-01-17 | 2018-05-01 | 合肥本源量子计算科技有限责任公司 | A kind of method for optimizing quantum wire emulation |
Non-Patent Citations (1)
| Title |
|---|
| 赵千川: "《量子计算和量子信息》", 31 January 2004 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113222155A (en) * | 2020-01-21 | 2021-08-06 | 合肥本源量子计算科技有限责任公司 | Quantum line construction method and device, electronic device and storage medium |
| CN113222155B (en) * | 2020-01-21 | 2023-08-11 | 本源量子计算科技（合肥）股份有限公司 | Quantum circuit construction method and device, electronic device and storage medium |
| CN111461334A (en) * | 2020-03-30 | 2020-07-28 | 北京百度网讯科技有限公司 | Quantum circuit processing method, device and equipment |
| CN112073126A (en) * | 2020-08-14 | 2020-12-11 | 合肥本源量子计算科技有限责任公司 | Method and device for ordering network node importance |
| CN114970872A (en) * | 2021-02-26 | 2022-08-30 | 合肥本源量子计算科技有限责任公司 | Quantum line compiling method, device, medium, and electronic device |
| CN114970872B (en) * | 2021-02-26 | 2024-06-14 | 本源量子计算科技（合肥）股份有限公司 | Quantum circuit compiling method and device, medium and electronic device |
| CN115618955A (en) * | 2022-12-19 | 2023-01-17 | 量子科技长三角产业创新中心 | Quantum line optimization method, device, equipment and storage medium |
| CN115618955B (en) * | 2022-12-19 | 2023-04-07 | 量子科技长三角产业创新中心 | Quantum line optimization method, device, equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109165741A (en) | 2019-01-08 |
| CN110363301B (en) | 2021-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110363301A (en) | Processing method, device, storage medium and the electronic device of quantum wire | |
| CN108769165A (en) | Data processing method, Internet of Things access system in a kind of Internet of Things | |
| EP3697063B1 (en) | Communication control device, communication control method, and communication system | |
| CN106056211B (en) | Neuron computing unit, neuron computing module and artificial neural networks core | |
| CN108184244B (en) | Industrial wireless network deterministic scheduling method supporting transmission delay optimization | |
| CN106056212A (en) | Artificial neural network calculating core | |
| CN102947813A (en) | Method for transmitting data via canopen bus | |
| CN106982222A (en) | The multi-protocol data cut-in method and device that can configure under a kind of industrial 4.0 environment | |
| CN107168971A (en) | The data processing method and device of web application | |
| CN109814482A (en) | Controller of robot, control method of controller and industrial robot | |
| CN110098906A (en) | Divide communication channel | |
| CN108040119A (en) | Data transmission scheme between car networking vehicle and platform | |
| CN108616524A (en) | Data transmission method and device and data converter | |
| CN108712200B (en) | Intelligent wireless satellite affair system for minisatellite and control method | |
| CN103929377A (en) | Wired network and wireless network combined dispatching method and system and related devices | |
| CN108200117A (en) | Intelligent hand-held terminal data synchronous system and method | |
| CN103973489B (en) | A kind of heterogeneous device centralized monitoring system | |
| CN107483330A (en) | A kind of repeater bridging method and gateway | |
| CN107659505A (en) | The route selecting method and SDN controllers of a kind of SDN | |
| DE112017007523T5 (en) | CREATE A COMPUTER SYSTEM | |
| CN112215326B (en) | Distributed AI system | |
| CN117332374A (en) | AI chip calculation and communication fusion method and device and AI chip | |
| CN107885691A (en) | Serial data transmission method, distributed apparatus and main frame | |
| CN107147698A (en) | The tele-control system of intelligent switch, method and apparatus | |
| EP3520351B1 (en) | Device and method for continuous and cross-media transmission of communication protocols without protocol conversion |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |