CN110350898A - A kind of carrier band chip start and close reset circuit and its working method - Google Patents
A kind of carrier band chip start and close reset circuit and its working method Download PDFInfo
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- CN110350898A CN110350898A CN201910642975.7A CN201910642975A CN110350898A CN 110350898 A CN110350898 A CN 110350898A CN 201910642975 A CN201910642975 A CN 201910642975A CN 110350898 A CN110350898 A CN 110350898A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/24—Storing the actual state when the supply voltage fails
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention provides a kind of carrier band chip start and close reset circuits, comprising: division module, level-one flip-flop module, energy-storage module and second level flip-flop module；Division module is suitable for dividing power supply, by first node voltage transmission to level-one flip-flop module；Energy-storage module one end is connected with power supply, and the second node voltage between the other end and level-one flip-flop module, second level flip-flop module is connected；When booting, first node voltage rises with the rising of power supply, to trigger level-one flip-flop module forward conduction；After level-one flip-flop module forward conduction, energy-storage module starts to store energy, is gradually reduced second node voltage, to trigger second level flip-flop module reverse-conducting output boot-strap reset voltage；When shutdown, first node voltage declines with the decline of power supply, to trigger level-one flip-flop module reverse-conducting；After level-one flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage.
Description
Technical field
The present invention relates to technical field of circuit design, more particularly to carrier band chip to be led with start and close reset circuit technology
Domain.
Background technique
In integrated circuit design in order to avoid when booting (power on) in circuit node (node) enter unknown state
(unknown state) and cause to malfunction or leak electricity, it is therefore desirable to allowed using boot-strap reset signal (power on reset)
Internal node can maintain predeterminated voltage, allow circuit that can enter preset state, therefore boot-strap reset circuit (power on
Reset circuit) design be extremely important for IC design.In the application of TFT liquid crystal display panel, shut down (power
Occurs unexpected picture when off) in shutdown process in order to avoid panel, therefore panel drive circuit chip needs to shut down
Shutdown programm is detected and carries out, therefore start and close reset circuit can star and be very important in chip design.
For figure first is that existing boot-strap reset circuit, existing boot-strap reset circuit is to utilize RC charge and discharge, anti-by two-stage
Boot-strap reset signal is generated to device.The timing diagram of existing boot-strap reset circuit as shown in Figure 2, when booting, V1 point because
When RC is charged to high input level (Vih) of first order flip-flop (MP1 and MN1 composition), V2 point will transition change to ground connection, this
When using level-one flip-flop (MP2 form with MN2) then can produce boot-strap reset signal (power on reset).However half
In conductor processing procedure resistance class value variation it is quite big, be easy to cause boot-strap reset signal generate starting voltage and reset time with
Emulation (simulation) is not inconsistent.This circuit, can be because RC retardation ratio be excessive, when V1 point drops during shutdown (power off)
To flip-flop low input level (Vil) when, power supply (VDD), which has been reduced to operating voltage or less, causes this circuit shutting down
It in the process can not actuation.Therefore existing reset circuit (reset circuit) is not switched on and can start with shutdown process,
And chip can be made to malfunction during switching on and shutting down.
Summary of the invention
For overcome it is existing in the prior art be unable to satisfy booting and operated with shutdown, and chip can be made in switching on and shutting down process
Middle the problem of malfunctioning, the present invention provides a kind of carrier band chip start and close reset circuits.
In order to solve the above-mentioned technical problems, the present invention provides a kind of carrier band chip start and close reset circuits, comprising:
Division module, level-one flip-flop module, energy-storage module and second level flip-flop module；Wherein the division module is suitable for power supply electricity
Source is divided, and by first node voltage transmission to the level-one flip-flop module；One end of the energy-storage module and power supply
Power supply is connected, and the second node voltage between the other end and level-one flip-flop module, second level flip-flop module is connected；Booting
When, first node voltage is suitable for the rising with power supply and rises, to trigger level-one flip-flop module forward conduction；One
After grade flip-flop module forward conduction, energy-storage module starts to store energy, is gradually reduced second node voltage, to trigger second level
Flip-flop module reverse-conducting exports boot-strap reset voltage；And when shutdown, first node voltage is suitable for power supply
Decline and decline, to trigger level-one flip-flop module reverse-conducting；After level-one flip-flop module reverse-conducting, second level flip-flop
Module forward conduction output shutdown reset voltage.
Further, the division module includes: resistance R1 and resistance R2；Power supply successively connects through resistance R1, resistance R2
Ground, and the voltage between resistance R1 and resistance R2 is as the first node voltage.
Further, the level-one flip-flop module includes: the first PMOS tube and the first NMOS tube；First PMOS tube
Grid accesses the first node voltage, and source electrode is connect with power supply；The grid access described the of first NMOS tube
One node voltage, source electrode ground connection；And the drain electrode of first PMOS tube and the drain electrode of the first NMOS tube are accessing second level just
Anti- device module.
Further, the level-one flip-flop module includes: third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third
NMOS tube, the 4th NMOS tube and the 5th NMOS tube；The grid of the third PMOS tube accesses the first node voltage, source electrode
It is connect with power supply；The grid of 4th PMOS tube accesses the first node voltage, drain electrode access second level flip-flop
Module；The drain electrode of the third PMOS tube accesses the source electrode of the 5th PMOS tube after connecting with the source electrode of the 4th PMOS tube；Described
The grounded drain of five PMOS tube, grid access second level flip-flop module；The grid access described first of the third NMOS tube
Node voltage, drain electrode access second level flip-flop module；The grid of 4th NMOS tube accesses the first node voltage,
Source electrode ground connection；The source electrode of the 5th NMOS tube is accessed after the source electrode of the third NMOS tube and the drain electrode connection of the 4th NMOS tube；
And the 5th the drain electrode of NMOS tube connect with power supply, grid accesses second level flip-flop module.
Further, the second level flip-flop module includes: the second PMOS tube and the second NMOS tube；Second PMOS tube
Grid accesses the output of level-one flip-flop module, and source electrode is connect with power supply；The grid access one of second NMOS tube
The output of grade flip-flop module, source electrode ground connection；And the drain electrode of second PMOS tube is connected with the drain electrode of the second NMOS tube,
And the voltage between the drain electrode and the drain electrode of the second NMOS tube of second PMOS tube is as the boot-strap reset voltage or described
Shut down reset voltage.
Further, the accumulator includes: electrolytic capacitor；One end of the electrolytic capacitor is connected with power supply,
The other end is connected with second node voltage.
Another aspect, the present invention also provides a kind of working methods of start and close reset circuit, comprising: the booting is closed
Machine reset circuit is suitable for exporting boot-strap reset voltage in booting；And the start and close reset circuit is suitable for during shutdown,
Output shutdown reset voltage.
Further, the start and close reset circuit includes: division module, level-one flip-flop module, energy-storage module and two
Grade flip-flop module；Wherein the division module is suitable for dividing power supply, and by first node voltage transmission to institute
State level-one flip-flop module；One end of the energy-storage module is connected with power supply, the other end and level-one flip-flop module, two
Second node voltage between grade flip-flop module is connected；When booting, first node voltage is suitable for the rising with power supply
And rise, to trigger level-one flip-flop module forward conduction；After level-one flip-flop module forward conduction, energy-storage module starts to store up
Energy is deposited, second node voltage is gradually reduced, to trigger second level flip-flop module reverse-conducting output boot-strap reset voltage；With
And when shutdown, first node voltage is suitable for the decline with power supply and declines, and is reversely led with triggering level-one flip-flop module
It is logical；After level-one flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage.
Further, the level-one flip-flop module includes: the first PMOS tube and the first NMOS tube；First PMOS tube
Grid accesses the first node voltage, and source electrode is connect with power supply；The grid access described the of first NMOS tube
One node voltage, source electrode ground connection；And the drain electrode of first PMOS tube and the drain electrode of the first NMOS tube are accessing second level just
Anti- device module.
Further, the level-one flip-flop module includes: third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third
NMOS tube, the 4th NMOS tube and the 5th NMOS tube；The grid of the third PMOS tube accesses the first node voltage, source electrode
It is connect with power supply；The grid of 4th PMOS tube accesses the first node voltage, drain electrode access second level flip-flop
Module；The drain electrode of the third PMOS tube accesses the source electrode of the 5th PMOS tube after connecting with the source electrode of the 4th PMOS tube；Described
The grounded drain of five PMOS tube, grid access second level flip-flop module；The grid access described first of the third NMOS tube
Node voltage, drain electrode access second level flip-flop module；The grid of 4th NMOS tube accesses the first node voltage,
Source electrode ground connection；The source electrode of the 5th NMOS tube is accessed after the source electrode of the third NMOS tube and the drain electrode connection of the 4th NMOS tube；
And the 5th the drain electrode of NMOS tube connect with power supply, grid accesses second level flip-flop module.
Compared with prior art, the beneficial effects of the present invention are:
The present invention is the reset circuit that can be operated during start and close, and when booting, first node voltage is with confession
The rising of power supply and rise, to trigger level-one flip-flop module forward conduction, after level-one flip-flop module forward conduction, storage
Energy module starts to store energy, is gradually reduced second node voltage, is opened with triggering the output of second level flip-flop module reverse-conducting
Machine reset voltage；When shutdown, first node voltage declines with the decline of power supply, anti-to trigger level-one flip-flop module
To conducting, after level-one flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage；This hair
Bright to set electrolytic capacitor for energy-storage module, reset time can be set in the size by adjusting electrolytic capacitor value；The present invention is set
It sets resistance R1 and resistance R2 divides power supply, and then the resistance value size by changing resistance R1 and resistance R2 can be adjusted
Save the voltage value of input.
Detailed description of the invention
Fig. 1 is the schematic diagram of existing boot-strap reset circuit；
Fig. 2 is the timing diagram of existing boot-strap reset circuit；
Fig. 3 is the start and close reset circuit figure in the embodiment of the present invention 1；
Fig. 4 is the timing diagram of the start and close reset circuit in the embodiment of the present invention 1；
Fig. 5 is the start and close reset circuit figure in the embodiment of the present invention 2；
Specific embodiment
Below in conjunction with drawings and examples, the present invention will be described in further detail.It should be appreciated that described herein
Specific examples are only used to explain the present invention, is not intended to limit the present invention.
Embodiment 1
As shown in figure 3, the present invention schematically illustrates a kind of carrier band chip start and close reset circuit, comprising:
Division module, level-one flip-flop module, energy-storage module and second level flip-flop module；Wherein the division module is suitable for
Power supply is divided, and by first node voltage transmission to the level-one flip-flop module；The one of the energy-storage module
End is connected with power supply, the second node voltage phase between the other end and level-one flip-flop module, second level flip-flop module
Even；When booting, first node voltage is suitable for the rising with power supply and rises, to trigger the positive guide of level-one flip-flop module
It is logical；After level-one flip-flop module forward conduction, energy-storage module starts to store energy, is gradually reduced second node voltage, with
It triggers second level flip-flop module reverse-conducting and exports boot-strap reset voltage；And when shutdown, first node voltage is suitable for confession
The decline of power supply and decline, to trigger level-one flip-flop module reverse-conducting；After level-one flip-flop module reverse-conducting, two
Grade flip-flop module forward conduction output shutdown reset voltage.
The division module includes: resistance R1 and resistance R2；Power supply is successively grounded through resistance R1, resistance R2, and electricity
The voltage between R1 and resistance R2 is hindered as the first node voltage.
The level-one flip-flop module includes: the first PMOS tube and the first NMOS tube；The grid of first PMOS tube connects
Enter the first node voltage, source electrode is connect with power supply；The grid of first NMOS tube accesses the first node
Voltage, source electrode ground connection；And the drain electrode of first PMOS tube and the drain electrode of the first NMOS tube access second level flip-flop mould
Block.
The second level flip-flop module includes: the second PMOS tube and the second NMOS tube；The grid of second PMOS tube connects
Enter the output of level-one flip-flop module, source electrode is connect with power supply；The grid access level-one of second NMOS tube is positive and negative
The output of device module, source electrode ground connection；And the drain electrode of second PMOS tube is connected with the drain electrode of the second NMOS tube, and described
Voltage between the drain electrode and the drain electrode of the second NMOS tube of second PMOS tube is as the boot-strap reset voltage or shutdown weight
Set voltage.
The accumulator includes: electrolytic capacitor；One end of the electrolytic capacitor is connected with power supply, the other end with
Second node voltage is connected.
Resistance R1 and resistance R2 is not limited to be designed with passive resistance, can also be set using transistor equivalent resistance
Meter.
A kind of working method of start and close reset circuit, comprising: the start and close reset circuit is suitable in booting,
Export boot-strap reset voltage；And the start and close reset circuit is suitable for during shutdown, output shutdown reset voltage.
The start and close reset circuit includes: division module, level-one flip-flop module, energy-storage module and second level flip-flop
Module；Wherein the division module is suitable for dividing power supply, and just by first node voltage transmission to the level-one
Anti- device module；One end of the energy-storage module is connected with power supply, the other end and level-one flip-flop module, second level flip-flop
Second node voltage between module is connected；When booting, first node voltage is suitable for the rising with power supply and rises, with
Trigger level-one flip-flop module forward conduction；After level-one flip-flop module forward conduction, energy-storage module starts to store energy, makes
Second node voltage is gradually reduced, to trigger second level flip-flop module reverse-conducting output boot-strap reset voltage；And when shutdown,
First node voltage is suitable for the decline with power supply and declines, to trigger level-one flip-flop module reverse-conducting；In level-one
After flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage.
The level-one flip-flop module includes: the first PMOS tube and the first NMOS tube；The grid of first PMOS tube connects
Enter the first node voltage, source electrode is connect with power supply；The grid of first NMOS tube accesses the first node
Voltage, source electrode ground connection；And the drain electrode of first PMOS tube and the drain electrode of the first NMOS tube access second level flip-flop mould
Block.
As shown in Figure 3 and Figure 4, a required first voltage is generated using the voltage divide function of electricity group R1 and resistance R2
Node V1, wherein V1=VDD* (R2/ (R1+R2)).When booting, first voltage node V1 with power supply (VDD) rise and
Rise, when the high input that first voltage node V1 point is higher than first order flip-flop (the first PMOS tube and the first NMOS tube composition) is quasi-
When position (Vih), second voltage node V2 horse back transition to ground connection.Therefore can by the voltage divide function of resistance R1 and resistance R2 with
High input level (Vih) of first order flip-flop controls when the first NMOS tube is opened, by change the first NMOS tube etc.
The capacitance of effect electricity group and electrolytic capacitor (Cap), in that case it can be decided that the resetting starting voltage and reset time of reset circuit；Shutdown
When, first voltage node V1 can decline as power supply (VDD) declines, therefore can design first voltage node V1 voltage
The low input level (Vil) of flip-flop is dropped to when carrying chip operating voltage section, the reset circuit that shuts down at this time can also be made
It is dynamic.When the variation of semiconductor resistor resistance value, because resistance R1 and resistance R2 can change simultaneously, first voltage section will not influence
The partial pressure of point V1 point can be consistent in this approach to design with emulation.The weight that can be operated during start and close of the invention
Circuits are divided by resistance R1 and resistance R2, and first voltage node V1 is through excessively high input level (Vih) and low input level
(Vil) adjustment circuit starts voltage to design resetting, and reset time, while the present invention on the other hand can be determined by capacitance
Also it can be operated in shutdown process to provide carrier band chip and carry out shutdown programm, there is marked improvement compared to the prior art.
Embodiment 2
As shown in figure 5, the present invention schematically illustrates a kind of carrier band chip start and close reset circuit, comprising:
Division module, level-one flip-flop module, energy-storage module and second level flip-flop module；Wherein the division module is suitable for
Power supply is divided, and by first node voltage transmission to the level-one flip-flop module；The one of the energy-storage module
End is connected with power supply, the second node voltage phase between the other end and level-one flip-flop module, second level flip-flop module
Even；When booting, first node voltage is suitable for the rising with power supply and rises, to trigger the positive guide of level-one flip-flop module
It is logical；After level-one flip-flop module forward conduction, energy-storage module starts to store energy, is gradually reduced second node voltage, with
It triggers second level flip-flop module reverse-conducting and exports boot-strap reset voltage；And when shutdown, first node voltage is suitable for confession
The decline of power supply and decline, to trigger level-one flip-flop module reverse-conducting；After level-one flip-flop module reverse-conducting, two
Grade flip-flop module forward conduction output shutdown reset voltage.
The division module includes: resistance R1 and resistance R2；Power supply is successively grounded through resistance R1, resistance R2, and electricity
The voltage between R1 and resistance R2 is hindered as the first node voltage.
The level-one flip-flop module includes: third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube,
Four NMOS tubes and the 5th NMOS tube；The grid of the third PMOS tube accesses the first node voltage, source electrode and power supply electricity
Source connection；The grid of 4th PMOS tube accesses the first node voltage, drain electrode access second level flip-flop module；It is described
The drain electrode of third PMOS tube accesses the source electrode of the 5th PMOS tube after connecting with the source electrode of the 4th PMOS tube；5th PMOS tube
Grounded drain, grid access second level flip-flop module；The grid of the third NMOS tube accesses the first node voltage,
Drain electrode access second level flip-flop module；The grid of 4th NMOS tube accesses the first node voltage, source electrode ground connection；Institute
The drain electrode of the source electrode and the 4th NMOS tube of stating third NMOS tube accesses the source electrode of the 5th NMOS tube after connecting；And the 5th NMOS
The drain electrode of pipe is connect with power supply, and grid accesses second level flip-flop module.
The second level flip-flop module includes: the second PMOS tube and the second NMOS tube；The grid of second PMOS tube connects
Enter the output of level-one flip-flop module, source electrode is connect with power supply；The grid access level-one of second NMOS tube is positive and negative
The output of device module, source electrode ground connection；And the drain electrode of second PMOS tube is connected with the drain electrode of the second NMOS tube, and described
Voltage between the drain electrode and the drain electrode of the second NMOS tube of second PMOS tube is as the boot-strap reset voltage or shutdown weight
Set voltage.
The accumulator includes: electrolytic capacitor；One end of the electrolytic capacitor is connected with power supply, the other end with
Second node voltage is connected.
A kind of working method of start and close reset circuit, comprising: the start and close reset circuit is suitable in booting,
Export boot-strap reset voltage；And the start and close reset circuit is suitable for during shutdown, output shutdown reset voltage.
The start and close reset circuit includes: division module, level-one flip-flop module, energy-storage module and second level flip-flop
Module；Wherein the division module is suitable for dividing power supply, and just by first node voltage transmission to the level-one
Anti- device module；One end of the energy-storage module is connected with power supply, the other end and level-one flip-flop module, second level flip-flop
Second node voltage between module is connected；When booting, first node voltage is suitable for the rising with power supply and rises, with
Trigger level-one flip-flop module forward conduction；After level-one flip-flop module forward conduction, energy-storage module starts to store energy, makes
Second node voltage is gradually reduced, to trigger second level flip-flop module reverse-conducting output boot-strap reset voltage；And when shutdown,
First node voltage is suitable for the decline with power supply and declines, to trigger level-one flip-flop module reverse-conducting；In level-one
After flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage.
The level-one flip-flop module includes: third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube,
Four NMOS tubes and the 5th NMOS tube；The grid of the third PMOS tube accesses the first node voltage, source electrode and power supply electricity
Source connection；The grid of 4th PMOS tube accesses the first node voltage, drain electrode access second level flip-flop module；It is described
The drain electrode of third PMOS tube accesses the source electrode of the 5th PMOS tube after connecting with the source electrode of the 4th PMOS tube；5th PMOS tube
Grounded drain, grid access second level flip-flop module；The grid of the third NMOS tube accesses the first node voltage,
Drain electrode access second level flip-flop module；The grid of 4th NMOS tube accesses the first node voltage, source electrode ground connection；Institute
The drain electrode of the source electrode and the 4th NMOS tube of stating third NMOS tube accesses the source electrode of the 5th NMOS tube after connecting；And the 5th NMOS
The drain electrode of pipe is connect with power supply, and grid accesses second level flip-flop module.
To improve high input level (Vih) of start and close reset circuit and the adjustable range of low input level (Vil),
The another framework for proposing embodiment 2, such as figure five.The high input of embodiment 1 prepares (Vih) and low input level (Vil) is limited respectively
The critical voltage of the first PMOS tube and the first NMOS tube in figure three.Third PMOS tube is denoted as mp11, the 4th PMOS tube is denoted as
Mp12, the 5th PMOS tube are denoted as mp13, third NMOS tube is denoted as mn11, the 4th NMOS tube is denoted as mn12 and the 5th NMOS tube is denoted as
mn13。
In start process, when power supply (VDD) rises, first voltage node V1 also can be with power supply
(VDD) rise.Before the non-transition of reset signal, second voltage node V2 voltage is VDD, and second voltage node V2 voltage is
VDD, the 5th NMOS tube is opened at this time, and voltage node VB voltage is VDD-Vthmn13.Rise when power supply (VDD) is lasting, the
When one voltage node V1 voltage is greater than Vthmn12+VB, the 4th NMOS tube could open transition, and second voltage node V2 switchs to connect
Ground.Using the second PMOS tube in second level reverser (the second PMOS tube and the second NMOS tube composition), reset signal at this time
It generates.In shutdown process, first voltage node V1 voltage with power supply (VDD) decline and decline, when reset signal not
Before transition, second voltage node V2 switchs to be grounded, and the 5th PMOS tube is opened at this time, and voltage node VA voltage is-Vthmp13.When
Power supply (VDD) continues to decline, and the voltage difference of first voltage node V1 and power supply (VDD) fall below VA+Vtmp12
When (wherein Vthmp12 be negative value), the 4th PMOS tube opens transition.Second voltage node V2 voltage is VDD at this time.Using two
The second NMOS tube in grade reverser (the second PMOS tube and the second NMOS tube composition), reset signal generates at this time.
The reset circuit that can be operated during start and close of the invention is divided by resistance R1 and resistance R2, the
One voltage node V1 designs resetting starting voltage through excessively high input level (Vih) and low input level (Vil) adjustment circuit, separately
On the one hand reset time can be determined by capacitance, while the present invention can be also operated in shutdown process to provide carrier band core
Piece carries out shutdown programm, there is marked improvement compared to the prior art.By the circuit design of embodiment 2, high input can be widened
The adjusting range of level (Vih) and low input level (Vil), and it is not only restricted to the critical voltage of transistor.
The preferred embodiment of the present invention has shown and described in above description, as previously described, it should be understood that the present invention is not office
Be limited to form disclosed herein, should not be regarded as an exclusion of other examples, and can be used for various other combinations, modification and
Environment, and can be changed within that scope of the inventive concept describe herein by the above teachings or related fields of technology or knowledge
It is dynamic.And changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, then it all should be appended by the present invention
In scope of protection of the claims.
Claims (10)
1. a kind of start and close reset circuit characterized by comprising
Division module, level-one flip-flop module, energy-storage module and second level flip-flop module；Wherein
The division module is suitable for dividing power supply, and by first node voltage transmission to the level-one flip-flop mould
Block；
One end of the energy-storage module is connected with power supply, the other end and level-one flip-flop module, second level flip-flop module
Between second node voltage be connected；
When booting, first node voltage is suitable for the rising with power supply and rises, positive to trigger level-one flip-flop module
Conducting；
After level-one flip-flop module forward conduction, energy-storage module starts to store energy, is gradually reduced second node voltage, with
It triggers second level flip-flop module reverse-conducting and exports boot-strap reset voltage；And
When shutdown, first node voltage is suitable for the decline with power supply and declines, reversed to trigger level-one flip-flop module
Conducting；
After level-one flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage.
2. a kind of start and close reset circuit according to claim 1, which is characterized in that
The division module includes: resistance R1 and resistance R2；
Power supply is successively grounded through resistance R1, resistance R2, and the voltage between resistance R1 and resistance R2 is as the first segment
Point voltage.
3. a kind of start and close reset circuit according to claim 2, which is characterized in that
The level-one flip-flop module includes: the first PMOS tube and the first NMOS tube；
The grid of first PMOS tube accesses the first node voltage, and source electrode is connect with power supply；
The grid of first NMOS tube accesses the first node voltage, source electrode ground connection；And
The drain electrode of first PMOS tube and the drain electrode of the first NMOS tube access second level flip-flop module.
4. a kind of start and close reset circuit according to claim 2, which is characterized in that
The level-one flip-flop module includes: third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube, the 4th
NMOS tube and the 5th NMOS tube；
The grid of the third PMOS tube accesses the first node voltage, and source electrode is connect with power supply；
The grid of 4th PMOS tube accesses the first node voltage, drain electrode access second level flip-flop module；
The drain electrode of the third PMOS tube accesses the source electrode of the 5th PMOS tube after connecting with the source electrode of the 4th PMOS tube；
The grounded drain of 5th PMOS tube, grid access second level flip-flop module；
The grid of the third NMOS tube accesses the first node voltage, drain electrode access second level flip-flop module；
The grid of 4th NMOS tube accesses the first node voltage, source electrode ground connection；
The source electrode of the 5th NMOS tube is accessed after the source electrode of the third NMOS tube and the drain electrode connection of the 4th NMOS tube；And
The drain electrode of 5th NMOS tube is connect with power supply, and grid accesses second level flip-flop module.
5. according to a kind of any start and close reset circuit of claim 3 or 4, which is characterized in that
The second level flip-flop module includes: the second PMOS tube and the second NMOS tube；
The output of the grid access level-one flip-flop module of second PMOS tube, source electrode are connect with power supply；
The output of the grid access level-one flip-flop module of second NMOS tube, source electrode ground connection；And
The drain electrode of second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode and second of second PMOS tube
Voltage between the drain electrode of NMOS tube is as the boot-strap reset voltage or the shutdown reset voltage.
6. a kind of start and close reset circuit according to claim 5, which is characterized in that
The accumulator includes: electrolytic capacitor；
One end of the electrolytic capacitor is connected with power supply, and the other end is connected with second node voltage.
7. a kind of working method of start and close reset circuit characterized by comprising
The start and close reset circuit is suitable for exporting boot-strap reset voltage in booting；And
The start and close reset circuit is suitable for during shutdown, output shutdown reset voltage.
8. a kind of working method of start and close reset circuit according to claim 7, which is characterized in that
The start and close reset circuit includes:
Division module, level-one flip-flop module, energy-storage module and second level flip-flop module；Wherein
The division module is suitable for dividing power supply, and by first node voltage transmission to the level-one flip-flop mould
Block；
One end of the energy-storage module is connected with power supply, the other end and level-one flip-flop module, second level flip-flop module
Between second node voltage be connected；
When booting, first node voltage is suitable for the rising with power supply and rises, positive to trigger level-one flip-flop module
Conducting；
After level-one flip-flop module forward conduction, energy-storage module starts to store energy, is gradually reduced second node voltage, with
It triggers second level flip-flop module reverse-conducting and exports boot-strap reset voltage；And
When shutdown, first node voltage is suitable for the decline with power supply and declines, reversed to trigger level-one flip-flop module
Conducting；
After level-one flip-flop module reverse-conducting, second level flip-flop module forward conduction output shutdown reset voltage.
9. a kind of working method of start and close reset circuit according to claim 8, which is characterized in that
The level-one flip-flop module includes: the first PMOS tube and the first NMOS tube；
The grid of first PMOS tube accesses the first node voltage, and source electrode is connect with power supply；
The grid of first NMOS tube accesses the first node voltage, source electrode ground connection；And
The drain electrode of first PMOS tube and the drain electrode of the first NMOS tube access second level flip-flop module.
10. a kind of working method of start and close reset circuit according to claim 8, which is characterized in that
The level-one flip-flop module includes: third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube, the 4th
NMOS tube and the 5th NMOS tube；
The grid of the third PMOS tube accesses the first node voltage, and source electrode is connect with power supply；
The grid of 4th PMOS tube accesses the first node voltage, drain electrode access second level flip-flop module；
The drain electrode of the third PMOS tube accesses the source electrode of the 5th PMOS tube after connecting with the source electrode of the 4th PMOS tube；
The grounded drain of 5th PMOS tube, grid access second level flip-flop module；
The grid of the third NMOS tube accesses the first node voltage, drain electrode access second level flip-flop module；
The grid of 4th NMOS tube accesses the first node voltage, source electrode ground connection；
The source electrode of the 5th NMOS tube is accessed after the source electrode of the third NMOS tube and the drain electrode connection of the 4th NMOS tube；And
The drain electrode of 5th NMOS tube is connect with power supply, and grid accesses second level flip-flop module.
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| CN201910642975.7A CN110350898B (en) | 2019-07-16 | 2019-07-16 | Power-on and power-off reset circuit for carrier chip and working method thereof |
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| CN201910642975.7A CN110350898B (en) | 2019-07-16 | 2019-07-16 | Power-on and power-off reset circuit for carrier chip and working method thereof |
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| CN110350898B (en) | 2023-06-16 |
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